JPH02309279A - Receiving system of sonar apparatus - Google Patents
Receiving system of sonar apparatusInfo
- Publication number
- JPH02309279A JPH02309279A JP12877289A JP12877289A JPH02309279A JP H02309279 A JPH02309279 A JP H02309279A JP 12877289 A JP12877289 A JP 12877289A JP 12877289 A JP12877289 A JP 12877289A JP H02309279 A JPH02309279 A JP H02309279A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- amplification
- delay circuit
- time constant
- circuits
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000003321 amplification Effects 0.000 claims abstract description 14
- 238000003199 nucleic acid amplification method Methods 0.000 claims abstract description 14
- 238000001514 detection method Methods 0.000 claims abstract description 6
- 238000006243 chemical reaction Methods 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 7
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Landscapes
- Measurement Of Velocity Or Position Using Acoustic Or Ultrasonic Waves (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は水中に音波を発射し、その反射波を利用して目
標物を探知するソーナー装置の受振方式に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a sound receiving system for a sonar device that emits sound waves into water and uses the reflected waves to detect a target.
従来ソーナー装置の受振系における自動利得制御回路の
構成は、受波器からの受振信号を増幅回路で一旦増幅し
、各受渡器の受振信号出力を遅延回路網により全て同位
相で合成した後の受振出力をもって、各受波器の受振出
力に対して自動利得制御を行なっていた。従って、前記
した遅延回路網の出力チャネル数が多くなると共に、自
動利得制御を行なうチャネル数が多くなって、各チャネ
ル特性をそろえることがむずかしく、かつ使用部品数が
多くなり、構成が複雑となるという欠点があった。The configuration of the automatic gain control circuit in the reception system of a conventional sonar device is such that the reception signal from the receiver is once amplified by an amplifier circuit, and the reception signal output of each receiver is synthesized in the same phase by a delay circuit network. Automatic gain control was performed on the received output of each receiver. Therefore, as the number of output channels of the above-mentioned delay circuit increases, the number of channels on which automatic gain control is performed also increases, making it difficult to match the characteristics of each channel, and increasing the number of parts used, making the configuration complex. There was a drawback.
また、遅延回路網の入力レベルの変化範囲は受波音圧レ
ベルに応じて広くなるので、ディジタル回路で遅延回路
網を構成した場合には、A−D変換器のビット数を多く
しないと良好な性能を得ることが出来なかった。第2図
のブロック図に従って、従来方式を簡単に説明する。第
2図において、1〜3は受波器、4〜6は増幅回路、7
は遅延回路、8〜10は可変利得増幅回路、11〜13
は制御回路であり、受波器1〜3からの受振信号は増幅
回路4〜6で増幅された後、遅延回路網7に入力される
。In addition, since the range of change in the input level of the delay circuit becomes wider depending on the received sound pressure level, if the delay circuit is configured with a digital circuit, it will not work well unless the number of bits of the A-D converter is increased. I couldn't get the performance. The conventional system will be briefly explained according to the block diagram of FIG. In Figure 2, 1 to 3 are receivers, 4 to 6 are amplifier circuits, and 7
is a delay circuit, 8 to 10 are variable gain amplifier circuits, and 11 to 13 are
is a control circuit, in which the received signals from the wave receivers 1 to 3 are amplified by amplifier circuits 4 to 6, and then input to a delay circuit network 7.
このあと、遅延回路網7では、ある基準面に対して生ず
る各受渡器への信号到達時間差をり、 C等の遅延素子
を通すことにより、各受波器の受振信号を全て同位相で
合成する。After this, in the delay circuit network 7, the received signals of each receiver are all synthesized in the same phase by calculating the difference in the arrival time of the signal to each receiver that occurs with respect to a certain reference plane, and passing it through a delay element such as C. do.
その遅延回路網7の出力信号は可変利得増幅回路8〜1
0に送られ、可変利得増幅回路の出力の一部を制御回路
11〜13の入力として、制御電圧をつくり自動利得制
御を行ない、残響に対して可変利得増幅回路8〜10の
出力レベルが一定になるように動作する。The output signal of the delay circuit network 7 is output from variable gain amplifier circuits 8 to 1.
A part of the output of the variable gain amplifier circuit is input to the control circuits 11 to 13 to create a control voltage and perform automatic gain control, so that the output level of the variable gain amplifier circuits 8 to 10 is constant against reverberation. It works so that it becomes.
上記した従来の遅延回路網の入力レベルの変化範囲は、
受波音圧レベルに応じて広くなるので、ディジタル回路
で遅延回路網を構成した場合には、A−D変換器のビッ
ト数を多くしないと良好な特性を得ることができなかっ
た。The range of change in the input level of the conventional delay circuit described above is
Since the width increases depending on the received sound pressure level, when the delay circuit network is configured with a digital circuit, good characteristics cannot be obtained unless the number of bits of the A-D converter is increased.
更に遅延回路網の後に設ける増幅回路の特性として、入
出力直線性範囲の広いものが要求され、受振系の構成が
複雑かつ大きくなり、高価なものになるという欠点があ
った。Furthermore, the characteristic of the amplifier circuit provided after the delay circuit network is that a wide input/output linearity range is required, resulting in the disadvantage that the configuration of the vibration receiving system becomes complicated, large, and expensive.
本発明の目的は上記従来技術の問題点を除去し、受振系
の構成を簡単に、安価に構成できるようにすることにあ
る。An object of the present invention is to eliminate the problems of the prior art described above, and to enable a vibration receiving system to be configured simply and at low cost.
上記発明の目的は可変利得増幅回路の出力の一部を増幅
検波する増幅検波回路と、各チャネル中の最大出力信号
を検出するアナログゲート回路と、インピーダンス変換
と増幅をする直流増幅回路と、信号の性質に適した時定
数を設定する時定数回路とをそれぞれ具備し、該時定数
回路の出力電圧によって、利得が制御される前記可変利
得増幅回路からなる自動利得制御回路を遅延回路網に前
置し、遅延回路網により各受波器の受振信号を同位相で
合成する以前に自動利得制御を行なうことで達成される
。The object of the invention is to provide an amplification and detection circuit that amplifies and detects a part of the output of a variable gain amplifier circuit, an analog gate circuit that detects the maximum output signal in each channel, a DC amplifier circuit that performs impedance conversion and amplification, and a signal and a time constant circuit that sets a time constant suitable for the characteristics of the variable gain amplifier circuit, the gain of which is controlled by the output voltage of the time constant circuit. This is achieved by automatically controlling the gain before combining the received signals of each receiver in the same phase using a delay circuit network.
本発明のソーナー装置の受振方式によれば、遅延回路網
により各受波器の受振信号を同位相で合成する以前に各
受振系の受振信号を増幅する増幅器の自動利得制御を増
幅検討回路、アナログゲート回路、および直流増幅回路
、時定数回路を介して前記遅延回路に入力する受振信号
レベルに応じて行なったあと、遅延回路網を通して各受
振系の位相を同位相で合成することで、自動利得制御を
行なうチャネル数を減少させ、遅延回路網の入力レベル
の変化範囲を小さくできる。According to the reception method of the sonar device of the present invention, before combining the reception signals of each receiver in the same phase using a delay circuit network, an amplification consideration circuit performs automatic gain control of an amplifier that amplifies the reception signals of each reception system. After this is done according to the received signal level input to the delay circuit via the analog gate circuit, DC amplifier circuit, and time constant circuit, the phase of each receiving system is synthesized in the same phase through the delay circuit network. The number of channels that perform gain control can be reduced, and the range of change in the input level of the delay circuit network can be reduced.
第1図は本発明の一実施例を示すものであり、各チャネ
ル中の最大出力信号レベルによって利得制御を行なう場
合の一例を示すものである。FIG. 1 shows an embodiment of the present invention, and shows an example of gain control based on the maximum output signal level in each channel.
本発明のソーナー装置の受振系は、第1図に示すように
受波器1〜3の各出力と遅延回路y47との間に可変利
得増幅器14〜16を設け、該可変利得増幅器14〜1
6に前記各増幅器の出力を、増幅検討回路20〜22、
アナログゲート回路23〜25で取出すように設け、前
記アナログゲート回路23〜25の出力を直流増幅回路
26にそれぞれ加えこの出力を時定数回路27を介して
加えるように構成し、遅延回路網7の出力に設けた増幅
器17〜19にては利得制御を行なわないように構成す
る。As shown in FIG. 1, the vibration receiving system of the sonar device of the present invention includes variable gain amplifiers 14 to 16 provided between each output of the receivers 1 to 3 and a delay circuit y47.
6 shows the output of each of the amplifiers, and amplification examination circuits 20 to 22,
The outputs of the analog gate circuits 23 to 25 are respectively added to the DC amplifier circuit 26 and the outputs are added to the DC amplifier circuit 26 via the time constant circuit 27. The amplifiers 17 to 19 provided at the outputs are configured so as not to perform gain control.
本発明のソーナー装置の受振系は以上のように構成され
ており、以下この系の動作を説明する。The vibration receiving system of the sonar device of the present invention is constructed as described above, and the operation of this system will be described below.
今、受渡器1〜3からの受振信号は、可変利得増幅回路
14〜16で増幅された後、遅延回路網7に加えられる
。この時可変利得増幅回路14〜16の出力の一部を増
幅検波回路20〜22でそれぞれ増幅し検波した後、ア
ナログゲート回路23〜25で各チャネル中の最大出力
信号を検出し、高人力インピーダンスの直流増幅回路2
6でインピーダンス変換と増幅を行ない、時定数回路2
7で信号の性質に適した時定数を設定して、前記可変利
得増幅回路14〜16の利得を制御する。本方式では、
可変利得増幅回路14〜16の出力信号レベルの最大値
は一定になり、かつチャネル間の人力信号のレベル差が
そのまま出力信号レベルの差となって現われる。遅延回
路M47ではある基準面に対して生ずる各受波器への信
号到達時間差をり、 C等の遅延素子を通すことにより
、各受渡器の受振信号出力を全て同位相で合成し、その
出力を増幅回路17〜19でそれぞれ増幅して次段へ送
る。Now, the received signals from the transfer devices 1 to 3 are amplified by the variable gain amplifier circuits 14 to 16 and then applied to the delay circuit network 7. At this time, after a part of the output of the variable gain amplifier circuits 14 to 16 is amplified and detected by the amplification and detection circuits 20 to 22, respectively, the maximum output signal in each channel is detected by the analog gate circuits 23 to 25, and the high human power impedance is detected. DC amplifier circuit 2
6 performs impedance conversion and amplification, and time constant circuit 2
In step 7, a time constant suitable for the characteristics of the signal is set to control the gains of the variable gain amplifier circuits 14 to 16. In this method,
The maximum value of the output signal level of the variable gain amplifier circuits 14 to 16 becomes constant, and the level difference of the human input signal between channels directly appears as a difference in the output signal level. The delay circuit M47 calculates the difference in signal arrival time to each receiver that occurs with respect to a certain reference plane, and by passing it through a delay element such as C, the received signal outputs of each receiver are all combined in the same phase, and the output is are respectively amplified by amplifier circuits 17 to 19 and sent to the next stage.
請求項1記載の受振方式によれば、自動利得制御を行な
うチャネル数が少なくてすみ、又遅延回路網の入力レベ
ルの変化範囲を小さく出来るので、ディジタルで各受波
器の受振信号出力を同位相にする場合にA−D変換器の
ビット数が少なくても、同等の性能を得ることが出来る
。更に遅延回路網の後に設ける増幅回路の入出力直線性
の範囲を余り必要としない。According to the reception method according to claim 1, the number of channels for automatic gain control can be reduced, and the range of change in the input level of the delay circuit network can be reduced, so that the reception signal output of each receiver can be digitally synchronized. Even if the number of bits of the A-D converter is smaller when converting into phase, the same performance can be obtained. Furthermore, the input/output linearity range of the amplifier circuit provided after the delay circuit network is not required to be large.
ちなみに、本方式を使用すれば増幅回路、遅延回路網自
動利得制御回路を含んだ受振系を、小形で経済的に製作
出来る等の数多くの利点を有する。Incidentally, if this method is used, there are many advantages such as the ability to economically manufacture a vibration receiving system including an amplifier circuit, a delay network automatic gain control circuit, and the like in a small size.
第1図は、本発明による自動利得制御回路の構成法の実
施例を示すブロック図で、第2図は、従来の自動利得制
御回路の構成法を説明するブロック図である。
1〜3・・・受渡器、4〜6.17〜19・・・増幅回
路、7・・・遅延回路網、8〜10.14〜16・・・
可変利得増幅回路、11〜13・・・制御回路、20〜
22・・・増幅検波回路、23〜25・・・アナログゲ
ート回路、26・・・直流増幅回路、27・・・時定数
回路。
特許出願人 日立湘南電子株式会社
代理人 弁理士 秋 本 正 実(外1名)FIG. 1 is a block diagram showing an embodiment of a method of configuring an automatic gain control circuit according to the present invention, and FIG. 2 is a block diagram illustrating a method of configuring a conventional automatic gain control circuit. 1-3... Delivery device, 4-6. 17-19... Amplifier circuit, 7... Delay circuit network, 8-10. 14-16...
Variable gain amplifier circuit, 11-13... control circuit, 20-
22... Amplification detection circuit, 23-25... Analog gate circuit, 26... DC amplifier circuit, 27... Time constant circuit. Patent applicant Hitachi Shonan Electronics Co., Ltd. Agent Patent attorney Masami Akimoto (1 other person)
Claims (1)
標物を探知するにあたり、可変利得増幅回路の出力の一
部を増幅検波する増幅検波回路と、各チャネル中の最大
出力信号を検出するアナログゲート回路と、インピーダ
ンス変換と増幅をする直流増幅回路と、信号の性質に適
した時定数を設定する時定数回路とをそれぞれ具備し、
該時定数回路の出力電圧によって、利得が制御される前
記可変利得増幅回路からなる自動利得制御回路を遅延回
路網に前置し、遅延回路網により各受波器の受振信号を
同位相で合成する以前に自動利得制御を行なうことを特
徴とするソーナー装置の受振方式。1. When emitting sound waves into the water and detecting a target using the reflection of the sound waves, an amplification/detection circuit that amplifies and detects a part of the output of the variable gain amplifier circuit, and a maximum output signal in each channel are used. Equipped with an analog gate circuit for detection, a DC amplifier circuit for impedance conversion and amplification, and a time constant circuit for setting a time constant suitable for the characteristics of the signal,
An automatic gain control circuit consisting of the variable gain amplifier circuit whose gain is controlled by the output voltage of the time constant circuit is placed in front of the delay circuit network, and the received signals of each receiver are synthesized in the same phase by the delay circuit network. A vibration reception method for a sonar device that is characterized by automatic gain control before the sonar device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12877289A JPH02309279A (en) | 1989-05-24 | 1989-05-24 | Receiving system of sonar apparatus |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12877289A JPH02309279A (en) | 1989-05-24 | 1989-05-24 | Receiving system of sonar apparatus |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02309279A true JPH02309279A (en) | 1990-12-25 |
Family
ID=14993090
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12877289A Pending JPH02309279A (en) | 1989-05-24 | 1989-05-24 | Receiving system of sonar apparatus |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02309279A (en) |
-
1989
- 1989-05-24 JP JP12877289A patent/JPH02309279A/en active Pending
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