JPS5830766B2 - delay circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a delay circuit, and more particularly to a delay circuit that provides an accelerated delay time to an input signal.

FIG. 1 is a block diagram of a delay circuit that changes the delay time at a constant speed, which is the background of the present invention.

In the configuration, an oscillator 1 provides its oscillation frequency to an n-bit binary counter 2.

The counter 2 has n output terminals, and each time it counts an input frequency signal, its output terminals l, 2 . . . . sequentially derive counting outputs for n.

This output terminal l, 2. . . , the numbers n are hereinafter referred to as "digits".

Now, a high level output (hereinafter referred to as "H") from the first digit terminal of the counter 2 is given to the delay circuit 31.

The "H" output from the second digit terminal is given to the delay circuit 32, and similarly, the rHJ output from the nth digit terminal is given to the delay circuit 3n.

These delay circuits 31, 32 . ...3n integrally form the delay circuit group 3.

In each of the delay circuits 31 to 3n of this circuit group 3, the delay time is manipulated by the rHJ output from each digit terminal 1 to n of the corresponding counter 2.

4 is a delayed input terminal, and the delayed signal applied to this input terminal 4 is applied to the delay circuit 31.

The delayed signal, which has been time-delayed by passing through this delay circuit 31, is further given to a delay circuit 32, and is subjected to a time-delay by passing through it.

Thereafter, in the same way, the delayed signal which has been temporally delayed by the delay circuit group 3 finally passes through the delay circuit 3n and is led out to the delayed signal output terminal 5.

FIG. 2 is a time chart of signal waveforms of various parts of the circuit for explaining in detail the operation of the constant speed variable delay time circuit shown in FIG.

FIG. 2a shows the output frequency of the oscillator 1, particularly in the form of pulses.

Figure 2 shows the output of the 1st digit of counter 2, Figure 2 C shows the output of the 2nd digit, etc. Similarly, Figure 2 e shows n.
It is raining the output of the digit.

Further, FIG. 2f shows the state in which the delay time received by the delayed signal applied to the terminal 4 changes.

Referring to FIG. 1 and FIG. 2, the output pulses of oscillator 1 are counted by binary counter 2, and binary counter 2 derives an output according to the counted value to each digit terminal, and delays circuits 31 to 3n.
give to

In each delay circuit 31 to 3n, only when the output from the corresponding digit terminal 1 to n of the counter 2 is "H", that is, as shown in FIG.
The corresponding delay circuit is activated and the delay operation is performed only in the shaded portion -e.

When the output of the corresponding digit terminal of counter 2 is at a low level, that is, the delay operation is not executed except for the shaded areas in FIG. 2 b - e, and the delayed signal is simply transmitted to the next stage. Only.

Further, the delay time settings of the delay circuits 31 to 3n are weighted, and assuming that the delay time of the delay circuit 31 operated by the rHJ output of the first digit of the counter 2 is the shortest<TSeC, The delay time in the delay circuit 32 operated by the 2nd digit "H" output is 2'I'5ec4 The delay time in the delay circuit 3n operated by the 1st digit IHJ output is 2 T
sec.

In this way, the delay time of the delayed signal input to the delayed signal input terminal 4 is changed at a constant speed with time, as shown in FIG. 2f.

By the way, in the circuit shown in FIG. 1, since the oscillation frequency of the oscillator 1 is constant, the delay time can only be changed at a constant speed.

Therefore, it would be desirable to have a delay circuit that can more dynamically vary the delay time.

Therefore, the main object of the present invention is to provide a novel delay circuit that can vary the delay time at an accelerated rate.

To summarize the invention, it is a delay circuit that uses an oscillator whose frequency changes depending on a control voltage, and allows the delay time to change at an accelerated rate by changing the control voltage over time.

The above objects and other objects and features of the present invention will become more apparent from the detailed description given below with reference to the drawings.

FIG. 3 is a block diagram of one embodiment of the present invention.

The circuit of FIG. 3 is similar to the delay circuit of FIG. 1 except for the following points.

That is, the oscillator 1 is the voltage controlled oscillator 1' (hereinafter referred to as "■
(abbreviated as "CO") and this VCO1
' is provided with a voltage generator 6 that applies a control voltage.

FIG. 4 is a time chart for explaining the operation of one embodiment of the present invention shown in FIG. 3, and corresponds to the conventional FIG. 2, and the waveforms indicated by corresponding lowercase letters correspond to each other. The output waveform of each digit of counter 2 is shown.

FIG. 4g shows the control voltage applied from the voltage generator 6 to the VCO 1' for changing the oscillation frequency.

Note that, in order to simplify the explanation, this control voltage is shown as a voltage that increases in proportion to the time axis.

FIG. 4f shows the state in which the delay time received by the delayed signal applied to the delayed signal input terminal 4 changes.

Referring to FIGS. 3 and 4, the voltage generator 6 generates a voltage that increases in proportion to time as shown in FIG. 4g.
If CO1'4 is given, VC01' will change accordingly to the fourth
The oscillation frequency is gradually increased as shown in Figure a.

This pulse signal with increased frequency is given to the counter 2, which counts the pulse signal for each digit l, 2 . ...,
Derive the count output to n.

Each delay circuit 31-3n is activated in response to this counting output, and the weighting time T, 2T, . . . is set for each delay circuit 31-3n.

The input delayed signal is delayed by a time of 2n-1·T.

Now, the delay time that the delayed signal will receive after 1 second is T
sec, 3TSeC after 2 seconds, 6T after 3 seconds
sec, and after 4 seconds it becomes lQ'l'sec, and the delay that the delayed signal receives increases with the acceleration of 2T as time passes.

In this way, the delay time of the delayed signal applied to the input terminal 4 can change with time at a uniform rate.

In the above embodiment, the binary counter 2 is used to count the oscillation frequency, but the invention is not limited to this. For example, a counting circuit that shifts the state of the previous stage to the next stage by an input trigger, such as a shift register, may be used. You can.

Further, in the above embodiment, the control voltage applied to VC01' is a voltage that increases linearly with respect to time, but it may be a voltage that decreases linearly with respect to time.

Furthermore, in general, by increasing or decreasing the output frequency of the VCO 1' with an arbitrary voltage, the delay time can be varied with a wide variety of accelerations.

As described above, according to the present invention, by using an oscillator whose oscillation frequency changes depending on the voltage and by varying the voltage, the delay time can be varied at any acceleration, so it has the advantage of excellent versatility. be.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional constant speed variable delay circuit which is the background of the present invention. FIG. 2 is a time chart for explaining the operation of the circuit shown in FIG. FIG. 3 is a block diagram of one embodiment of the present invention. FIG. 4 is a time chart for explaining the operation of the circuit shown in FIG. 3. In the figure, the same reference numerals indicate the same or equivalent parts, 1' is a voltage controlled oscillator, 2 is a binary counter, 3 is a delay circuit group, 31 to 3n are delay circuits, 4 is a delayed signal input terminal, and 5 is a delayed signal input terminal. Indicates the output terminal.

Claims (1)

[Claims] 1. A delayed signal input terminal, an output terminal for deriving the delayed signal, a plurality of delay circuits connected in cascade between the input terminal and the output terminal, and an output terminal that changes the output frequency over time. an oscillator that can be varied; and a counting means that performs a counting operation according to the output of the oscillator and sequentially derives outputs from a plurality of output terminals that differ for each counting operation, and each of the delay circuits performs a counting operation according to the output of the oscillator; A delay circuit operated by means of output. 2. The oscillator whose output frequency can be changed over time is a voltage generator whose output voltage can be changed over time, and whose output frequency is changed by applying the voltage generated by the voltage generator. The delay circuit according to claim 1, comprising a voltage controlled oscillator.