JPS5830119A - Composite circuit part and method of producing same - Google Patents

Composite circuit part and method of producing same

Info

Publication number
JPS5830119A
JPS5830119A JP56128432A JP12843281A JPS5830119A JP S5830119 A JPS5830119 A JP S5830119A JP 56128432 A JP56128432 A JP 56128432A JP 12843281 A JP12843281 A JP 12843281A JP S5830119 A JPS5830119 A JP S5830119A
Authority
JP
Japan
Prior art keywords
substrate
electrodes
electrode
capacitor
dielectric
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56128432A
Other languages
Japanese (ja)
Other versions
JPH0214770B2 (en
Inventor
池田 重元
久 長田
善伸 佐々木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Corp
Original Assignee
TDK Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by TDK Corp filed Critical TDK Corp
Priority to JP56128432A priority Critical patent/JPS5830119A/en
Publication of JPS5830119A publication Critical patent/JPS5830119A/en
Publication of JPH0214770B2 publication Critical patent/JPH0214770B2/ja
Granted legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 本発明は、コイルL及びコンデンtC等を含む複合m回
路部品及びそのjI造方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a composite circuit component including a coil L, a capacitor TC, etc., and a method for manufacturing the same.

例えばjlN1図に示すような複数のコイルLt=La
及びコンデンサC1〜CsからなるLCフィルタを一枚
の基板上に構成する場合O従来装置として第2図に示す
ものを挙げることができるOこrtは、方形状の誘電体
基板11 O1!IiK複数の表面電極12tプリント
すると共に、その裏面に前記複数の表面電極12に対応
するような大面積を有する第1の裏面電極12A′及び
小さな1112の裏面電極12B′をプリントシ、前記
誘電体基板11の一方の辺部に形成した4個OE!1s
18内にそnぞれドラム状コアにコイルL1〜Lat4
1回してなるコイル装置15〜16t−嵌合配置した後
、各コイル装置13〜16から引き出さnるコイル端末
19A及び中間タップ19Bt−そnぞj’L[t!a
ll電体基板11の他方の辺部に設けた複数の突起部1
1ムに絡げた状態で前記コイル端末19A及び中間タッ
プ19Bと各表面電極12との接触部分を半田付等によ
シミ気的に接続し、表面電極12の1つと2つの裏面電
極12A’、 12B’にリード線10A〜10Cをそ
nぞn半田付等により接続してなるものである。ここで
、表面電極12と裏面電極12A’ 、 12B’との
対向部分がそnぞn各コンデンサ01〜Csとして構成
さnることKなる。
For example, multiple coils Lt=La as shown in diagram jlN1
When configuring an LC filter consisting of capacitors C1 to Cs on one substrate, the conventional device shown in FIG. 2 is a rectangular dielectric substrate 11 O1! IiK prints a plurality of front surface electrodes 12t, and prints a first back electrode 12A' having a large area corresponding to the plurality of front surface electrodes 12 and a small back surface electrode 12B' of 1112 on the back surface of the dielectric. Four OEs formed on one side of the substrate 11! 1s
Coils L1 to Lat4 are installed in each drum-shaped core within 18.
After the coil devices 15 to 16t formed once are fitted and arranged, the coil terminals 19A and intermediate taps 19Bt are pulled out from each coil device 13 to 16. a
A plurality of protrusions 1 provided on the other side of the electrical board 11
The contact portions of the coil terminal 19A and the intermediate tap 19B and each surface electrode 12 are connected in a stain-free manner by soldering or the like while the coil terminal 19A and the intermediate tap 19B are tied together into a single layer, and one of the surface electrodes 12 and two back electrodes 12A', Lead wires 10A to 10C are connected to 12B' by soldering or the like. Here, the facing portions of the front surface electrode 12 and the back surface electrodes 12A' and 12B' are respectively configured as capacitors 01 to Cs.

しかしながら、前記装置ではコンデンサの容量を確保す
るための大面積の裏面電極12A′の高さ方向の寸法j
ssとコイル装置13〜16を固定支持させるために必
要な高さ方向の寸法)1意を確保しなけnばならない友
め、誘電体基板11の高さ方向の寸法1uは極めて大き
なものとな夛、複合!1回路部品の小型化を阻むという
問題がある◇又、高さ寸法の増大に伴ってコイル装置1
3〜16から引き出されるコイル端末19A及び中間タ
ツ719BO長さも増大することとな9、組立作業時に
断線事故を引き起す等の問題も有った。そO上コイル端
末19A等を絡げるための突起@11Aも素子数が増大
するに従って増加することになるので、折損事故が多発
するという不都合、或いは誘電体基板110両辺部に所
定の間隔を保持させた凹fl118及び前記突起111
1At複数個設けなけnばならないため製造工程の複雑
化、工数の増加を招く等の種々の不都合が生じていた。
However, in the above device, the dimension j in the height direction of the large-area back electrode 12A' to ensure the capacitance of the capacitor is
The height dimension 1u of the dielectric substrate 11 must be extremely large, as it is necessary to ensure a uniformity (height dimension required to fixedly support the coil devices 13 to 16). Complex, complex! ◇There is also a problem that the size of the coil device 1 is hindered as the height dimension increases.
The lengths of the coil terminals 19A and the intermediate tabs 719BO that are drawn out from the coil terminals 3 to 16 also increase in length, and there are also problems such as wire breakage occurring during assembly work. Moreover, the number of protrusions @ 11A for wrapping the coil terminals 19A, etc. increases as the number of elements increases, so there is a problem of frequent breakage accidents, or it is difficult to maintain a predetermined spacing on both sides of the dielectric substrate 110. The held concave fl118 and the protrusion 111
The necessity of providing a plurality of 1 At has caused various inconveniences, such as complicating the manufacturing process and increasing the number of man-hours.

本発明は前記事情に鑑みてなさ−rteものであり、小
型化及び実装密度の向上が図れると共に、製造工程の簡
略化及び工数の減少を図ることができる複合型回路部品
及びそのIl造方法を提供すること金目的とするもので
ある0 以下実施例により本発明を具体的に説明する。
The present invention has been made in view of the above circumstances, and provides a composite circuit component and its manufacturing method that can reduce the size and increase the packaging density, as well as simplify the manufacturing process and reduce the number of man-hours. The present invention will be specifically described below with reference to Examples.

185図は本発明複合1wtl1ssIi&o−実施例
を示す斜視図である。同図KThいて1は方形状の絶縁
基板であp、その下方KFi同一形状の第1の誘電体基
板1′及びjI2の誘電体基板が順次接着等によシ固着
さnて−る@こO絶鍬基111の表面には複数の受動素
子接続用電極2A1〜2Asが形成さnている。こnら
各電極のうち絶縁基板10表面の三方の辺部近傍に配置
さnる複数の電極2人l〜2AI間上表部にはそnぞa
ll数(図示のものFi411)のドラム型コアにコイ
ルが壱回さnてなるコイル装置6〜6が搭載されてお夛
、両端のコイル端末3A〜品が各電極Kli続さnてい
る0こnらコイル装置のうち6個は6枚鍔のドラム蓋コ
アにコイルを巻回したものであり、それぞn中間タップ
5B〜5Bが引き出さnて前記絶縁基板1の表面中間部
に形成さnた5個の電極部〜2んに接続さnている。
Figure 185 is a perspective view showing a composite 1wtl1ssIi&o-embodiment of the present invention. In the same figure, KTh is a rectangular insulating substrate 1, below which a first dielectric substrate 1' of the same shape as KFi and a dielectric substrate jI2 are successively fixed by adhesive or the like. A plurality of passive element connection electrodes 2A1 to 2As are formed on the surface of the O-type base 111. Among these electrodes, a plurality of electrodes are arranged near the three sides of the surface of the insulating substrate 10, and there are a plurality of electrodes on the upper surface between the two electrodes 1 and 2AI.
A coil device 6 to 6 is mounted in which a coil is wound around a drum-shaped core of 11 (the one shown is Fi411), and the coil terminals 3A to 3A at both ends are connected to each electrode Kli. Six of these coil devices are coils wound around a drum lid core with six flanges, and intermediate taps 5B to 5B are drawn out and formed in the middle part of the surface of the insulating substrate 1, respectively. It is connected to five electrode parts to two.

これら各電極は絶縁基板1の図示下辺部迄延在しており
、その辺部との交点には適宜形状(例えばV字状ンの切
込117g〜7fが設けらnているoff、前記電極2
Asと2Aa e”j上辺部迄延在し、その交点に切込
s7y、7ムが形成さnている0前記誘電体基板1′に
おける前記絶縁基板1との接合面側には複数のコンデン
サ用電極2Bt〜2B―(詳細は後述する)が形成さn
1裏面11には詳lIa’i後述するような形状のコン
デンサ用共通電極2Cと他の電極2DC裏面電極)が形
成さnている。前記コンデンサ用電極21b〜28sは
前記絶縁基板1表両O各電極の位置に対応するように下
辺部及び上辺sK迄延在しておシ、その交点には前記切
込み部と対応する複数の切込部86〜8fが形成されて
おシ、これら上下に対応配置さnる各切込sK共通に形
成さnた導電層を介して前記絶縁基板111E*の電極
と誘電体基板1′上のコンデンサ用電極とが電気的に接
続さnている。最下部に位置する第2の誘電体基板IA
t;を前記1!1の誘電体基板1′と殆んど同一の構成
を有し、画者のコンデンサ用共通電極S會接触させた状
態で接着されている0従って、V字状の切込1191〜
塾も前記各切込97a〜7A及び8G〜8にと一致する
ように配置され、そnぞれ切込部に形成さnた共通の導
電層によって電気的に接続さnている。なお、11g2
の誘電体基板1人の下辺部中央KFiコンデンサ用共通
電極引出し用切込部91%が設けらnてお夕、この切込
@9nt介してコンデンサ用共通電極が裏面に引き出さ
nて後述するリード線に接続し易いよう罠なっている。
Each of these electrodes extends to the lower side of the insulating substrate 1 in the figure, and the intersections with the side are provided with appropriate shapes (for example, V-shaped notches 117g to 7f). 2
As and 2Aa e"j extend to the upper side, and cuts s7y and 7m are formed at their intersections. A plurality of capacitors are provided on the side of the dielectric substrate 1' that is joined to the insulating substrate 1. Electrodes 2Bt to 2B- (details will be described later) are formed.
On the back surface 11, there are formed a capacitor common electrode 2C and other electrodes 2DC (back surface electrode) having shapes as will be described in detail later. The capacitor electrodes 21b to 28s extend to the lower side and the upper side sK so as to correspond to the positions of the electrodes on both sides of the insulating substrate 1, and a plurality of cuts corresponding to the notches are provided at the intersections thereof. Recesses 86 to 8f are formed, and the electrodes of the insulating substrate 111E* and the dielectric substrate 1' are connected to each other through a conductive layer commonly formed in each of the notches 86 to 8f, which are arranged correspondingly above and below. It is electrically connected to the capacitor electrode. Second dielectric substrate IA located at the bottom
t; has almost the same structure as the dielectric substrate 1' of 1!1 above, and is bonded in a state in which it is in contact with the common electrode S for the artist's capacitor. Therefore, a V-shaped cut is formed. Including 1191~
The crams are also arranged to coincide with each of the notches 97a to 7A and 8G to 8, and are electrically connected by a common conductive layer formed in each of the notches. In addition, 11g2
A notch 91% for drawing out the common electrode for the KFi capacitor is provided at the center of the lower side of the dielectric substrate.Then, the common electrode for the capacitor is drawn out to the back side through this notch @9nt, and the lead described later is drawn out. It has a trap so that it is easy to connect to the line.

そして、艙記飴鍬基板10両端の電極にはリード線10
A、100が、又前記第2の誘電体基板1Aの裏面(形
成さnたコンデンサ用共通電極引出し電極11にはリー
ドl1lOBがそnぞn電気的に接続さnており、この
ようにして前記第1図に示したようなLC結合フィルタ
が構成さnている。
Lead wires 10 are attached to the electrodes at both ends of the board 10.
A, 100 is also electrically connected to the capacitor common electrode extraction electrode 11 formed on the back surface of the second dielectric substrate 1A, and in this way, An LC coupling filter as shown in FIG. 1 is constructed.

次に第4図乃至第6図を参照して前記装置め各部分の具
体的構成及び製造方法を具体的に説明するO 第4囮は前記絶縁基板1の費面図である。この絶縁基板
iti板状の耐熱性絶縁材料(例えばセラミック基板)
k方形状に切夛出したものでToり、図示下辺i1には
略等間隔で複数個(図示のものは6個)のV字状の切込
部71〜7fを設けるとともに、上辺部にも複数個(図
示のものは5個)のV字状の切込11(7y、7ム等)
t−設ける0そして、基板表面の適宜個所Ks分的に銀
メッキ等を施して複数(図示のものF15個)の受動素
子接続用電極(2人!〜2A工)と中間タッグ接続用電
極(図示のものは6個) (2Aa〜2A@)を形成す
る。このとき、受動素子接続用電極2A1〜2A、0う
ちの奇数を付したもの2At 、 2As 、 2ム蓼
と、3個の中間タッグ接続用電極2Aa〜2Asはそれ
ぞn下辺部に設けらnた各切込117E〜7f011.
分に迄延長形成する。残りの受動素子接続用電極2A雪
−2ム4は上辺sの切込@ 7y 、 7A迄達するよ
うKJi長形酸形成0そして各切込部7α〜7にの端面
には導電層を形成し、後工程での電気的接続管容易にす
るようにしておく0 しかる後、3枚鍔コアにコイルを巻目しコイル端末!I
A”5Aを両側面の導電層30 、4C、5Cに電気的
に接続してなるコイル装置3〜5及び2枚鍔コアにコイ
ルを巻回し両187tiio導電層記にコイル端末6A
を接続したコイル装置6t−それぞn用意し、前記電極
2人1〜鵠の各対向端部に接着剤を塗布した後、この接
着部に各コイル装置5〜6を搭載して固定する。このと
き;イル装置3〜5の中間タツ19Bは中間タップ接続
用電極2A4〜2A−上にそnぞn接触するように配置
する。
Next, the specific structure and manufacturing method of each part of the device will be explained in detail with reference to FIGS. 4 to 6. The fourth decoy is a cost-cut diagram of the insulating substrate 1. This insulating substrate is a plate-shaped heat-resistant insulating material (for example, a ceramic substrate)
It is cut into a k-square shape, and a plurality of (six in the figure) V-shaped notches 71 to 7f are provided at approximately equal intervals on the lower side i1, and the upper side is provided with a plurality of V-shaped notches 71 to 7f at approximately equal intervals. Also, make multiple (5 in the illustration) V-shaped notches 11 (7y, 7m, etc.)
t-Provide 0 Then, apply silver plating or the like to appropriate locations Ks on the surface of the board, and attach a plurality of (F15 pieces in the figure) passive element connection electrodes (2 people! ~ 2A work) and intermediate tag connection electrodes ( The one shown is six) (2Aa to 2A@) are formed. At this time, the passive element connection electrodes 2A1 to 2A, those with odd numbers among them 2At, 2As, 2M, and the three intermediate tag connection electrodes 2Aa to 2As are provided on the lower side, respectively. Each cut 117E to 7f011.
Extends to form up to a minute. For the remaining passive element connection electrodes 2A, 4, form a KJi long acid 0 so as to reach up to 7A on the upper side s, and form a conductive layer on the end face of each of the notches 7α to 7. , to make the electrical connection pipe easier in the subsequent process 0 After that, wrap the coil around the 3-piece tsuba core and end the coil! I
Coil devices 3 to 5 are formed by electrically connecting A"5A to conductive layers 30, 4C, and 5C on both sides, and coil terminals 6A are wound around two flange cores and coil terminals 6A are connected to conductive layers 30, 4C, and 5C on both sides.
After preparing coil devices 6t-n connected to each other and applying adhesive to each opposing end of the two electrodes 1 to 1, each coil device 5 to 6 is mounted and fixed on the bonded portion. At this time, the intermediate tabs 19B of the coil devices 3 to 5 are arranged so as to be in contact with the intermediate tap connection electrodes 2A4 to 2A-.

纂5図は前記IE1の誘電体基板1′の表面図であり、
第6図は第2の誘電体基板1人の裏面図である。
Figure 5 is a surface view of the dielectric substrate 1' of the IE1,
FIG. 6 is a back view of one second dielectric substrate.

形状に切シ出したものである。そして、この@1の誘電
体基板1′の下辺部と上辺部にはそnぞ几前記絶縁基板
1の各切込部7ト0対応する位置に複数のV字状の切込
118@−84を設ける。この第1の誘電体基板1′の
表面に適宜形状の複数のコンデンサ用電極2B、〜2B
s (表面電極)を銀メッキ等によって形成する。こn
ら各電極のうち6個の電極2B+〜2Bs−21ht!
下辺11切込58P−8f K迄達するように1N延長
□し、残りの電極2Bm及び2B番は上辺部の切込@8
7.8ルに迄達するように延長する0各切込部端面には
導電層を施しておく。そして、裏面には周辺sを残すよ
うにして大面積のコンデンサ用共通電極2Cと小面積の
電極2D(裏面電極)と′に!!tr記同様な手法によ
り形成する0このようにして表裏面の電@によって挾ま
n、を部分が前記第1図の回路における各コンダン? 
Ct−Cmの一部容量(例えば1/2の容量)Csα〜
C8aとなる。
It is cut into a shape. In the lower and upper sides of the dielectric substrate 1' of @1, a plurality of V-shaped notches 118 are provided at positions corresponding to the notches 7 and 0 of the insulating substrate 1, respectively. 84 will be provided. A plurality of appropriately shaped capacitor electrodes 2B, -2B are provided on the surface of this first dielectric substrate 1'.
s (surface electrode) is formed by silver plating or the like. This
Of each electrode, six electrodes 2B+ to 2Bs-21ht!
Lower side 11 cut 58P-8f Extend 1N to reach K, and the remaining electrodes 2Bm and 2B are cut @8 on the upper side.
7. A conductive layer is applied to the end face of each notch extending to reach 8 mm. Then, leaving the periphery s on the back side, a large area common electrode 2C for capacitors and a small area electrode 2D (back electrode) and '! ! In this way, each capacitor in the circuit shown in FIG.
Partial capacity (for example, 1/2 capacity) of Ct-Cm Csα~
It becomes C8a.

2g6図は前記第2の誘電体基板1人の裏面図であり、
その形状及び各電極の構成は前記第1の誘電体基板1′
のそnとはぼ同様である。即ち、裏面にはコンデンサ用
共通電極2C’、2D’が形成さn1表面にはコンデン
サ用電極2B1′〜28s’ (表面電極)が形成さn
1下辺部及び上辺sKは前記切込部8aHμに対応する
V字状切込1ira〜9ムが設けらnている。各切込部
端面には導電層を施しておく。
Figure 2g6 is a back view of one person on the second dielectric substrate,
The shape and configuration of each electrode are determined by the first dielectric substrate 1'.
Noso n is almost the same. That is, the capacitor common electrodes 2C' and 2D' are formed on the back surface, and the capacitor electrodes 2B1' to 28s' (surface electrodes) are formed on the surface n1.
The lower side and the upper side sK are provided with V-shaped notches 1ira to 9, which correspond to the notches 8aHμ. A conductive layer is applied to the end face of each notch.

この場合、特にfs2の誘電体基板の裏面の共通電極2
C’は下辺中央部に迄延在し、その交点に電極引出し用
切込s9襲が設けられ、こfLK対応する位置の表面K
tj共通電極引出し用電極2Bル′が設けらnる0そし
て、電極引出し用切込s9ルの端面には導電層を施して
表裏の電極を電気的に接続できるようにしておく0こ几
らの裏面電極2C’、2D’と表面電極2B1′〜2B
 、’との間に挾tnた誘電体部分が前記第1図の回路
に示した各コンデンサC1”C@の容量の一部(例えば
1/2入C1h−C口h)’に構成することKなる。
In this case, especially the common electrode 2 on the back side of the dielectric substrate fs2.
C' extends to the center of the lower side, and a notch s9 for drawing out the electrode is provided at the intersection thereof, and the surface K at the position corresponding to fLK is provided.
An electrode 2B' for drawing out the common electrode is provided, and a conductive layer is applied to the end face of the notch s9 for drawing out the electrode so that the front and back electrodes can be electrically connected. back electrodes 2C', 2D' and front electrodes 2B1' to 2B
The dielectric part sandwiched between the capacitor C1 and the capacitor C1 shown in the circuit of FIG. K becomes.

次に前記1IL2の誘電体基板1人の裏面を上にしてそ
の全面又は部分的に適宜の導電性接着剤を塗布して前記
第1の誘電体基板1′の裏面が一致するようにして重ね
合せて接着固定する。その後再び第1の誘電体基板1′
の表面に適宜の接着剤を部分的K又は全面的に塗布した
後前記コイル装置を搭載した絶縁基板1を重ね合せた後
接着固定する。この結果、そnぞれ対応する各切込41
7s−71、E3x−8k 。
Next, with the back side of one of the dielectric substrates 1IL2 facing up, an appropriate conductive adhesive is applied to the entire surface or part of the dielectric substrate 1IL2, and the back sides of the first dielectric substrate 1' are aligned with each other. Glue and fix together. After that, the first dielectric substrate 1'
After applying an appropriate adhesive partially or completely to the surface of the coil device, the insulating substrate 1 on which the coil device is mounted is superimposed and fixed by adhesive. As a result, each corresponding notch 41
7s-71, E3x-8k.

911−9にはほぼ同一線上に重なることになる。911-9, they overlap almost on the same line.

しかる後絶縁基板1表面の両端部の電極2A*、2Ai
に接触させたリード線10A、10Cと、IX2の誘電
体基板1人の裏面のコンデンサ用共通電極引出し用電極
2B3′に接触させたリード線10Bとによって前記両
基板1.1”lr挾持させた状態で半田槽内に浸漬〔半
田ディツプ〕する0この結果、各コイル装置3〜60両
11面の導電層3 hCと接続用電極ハ1−2A、とが
半田付さn1中関タッグ3B−5Bと中間タッグ接続用
電極2A P2A、とが半田付され、絶縁基板1の衆面
の各電極と第1及び第2の誘電体基板1 ’、 IAの
表面のコンデンサ用電極とが各切込部7α〜7ム、8g
−8ル、9α−9Aの各端面の導電層に付着し乏半田に
よって半田付さn1更に各リード@10A〜10Cと各
1極と力砕田付さnlそnぞn電気的に接続さnること
になる。このようにして第6図に示した装置が構成さn
る。この場合、第1の誘電体基板1′の各コンデンサc
xg−c@aと第2の誘電体基板1人の各コンデンサC
+b−C*hFiそnぞ几が並列接続状態となるため各
容量が2倍になり、両者を加算し友値が前記第1図の回
路の各コンデンサCt〜C8の容量と等しいものとなる
0即ち、Cl=C*a+Cxb 、Qz=Csa+Ct
A e ””…p Cm−Cog+C@4となるわけで
ある。
After that, the electrodes 2A*, 2Ai at both ends of the surface of the insulating substrate 1 are
Both boards 1.1"lr were held between the lead wires 10A and 10C that were in contact with the dielectric board IX2, and the lead wire 10B that was in contact with the capacitor common electrode extraction electrode 2B3' on the back side of one of the dielectric boards of IX2. As a result, the conductive layer 3hC on the 11th side of each coil device 3 to 60, the connection electrode 1-2A, and the n1 Nakaseki tag 3B- are immersed in the solder tank in the state of soldering. 5B and the intermediate tag connection electrode 2A P2A are soldered, and each electrode on the entire surface of the insulating substrate 1 and the capacitor electrode on the surface of the first and second dielectric substrates 1' and IA are connected to each notch. Part 7α~7mu, 8g
-8le, 9α-9A attached to the conductive layer on each end face and soldered with thin solder n1 Furthermore, each lead @10A to 10C and one pole each were soldered nl so n z n electrically connected n That will happen. In this way, the device shown in FIG. 6 is constructed.
Ru. In this case, each capacitor c on the first dielectric substrate 1'
xg-c@a and each capacitor C of one person on the second dielectric substrate
Since +b-C*hFi is connected in parallel, each capacitance is doubled, and by adding the two, the value becomes equal to the capacitance of each capacitor Ct to C8 in the circuit shown in Figure 1 above. 0, Cl=C*a+Cxb, Qz=Csa+Ct
A e ""...p Cm-Cog+C@4.

従って、従来装置と同様な;ンデンサ容量を確保する場
合には、1枚の誘電体基板の面積は半分で足りることに
なり、この結果横方向(長手方向)の寸法11を一定と
した場合、高さ方向の寸法!、け従来装置のコンデンサ
電極部分の寸法CI!2図のノ11)の1/2で足りる
ことになる。
Therefore, in order to secure the same capacitor capacity as in the conventional device, the area of one dielectric substrate can be reduced to half, and as a result, if the lateral (longitudinal) dimension 11 is kept constant, Dimensions in height direction! , Dimension CI of the capacitor electrode part of the conventional device! 1/2 of No. 11) in Figure 2 will be sufficient.

このように2枚の誘電体基板全裏面電極部を共通に貼り
合せて1つのコンデンサ用基板を構成するものであるた
め、基板の高さ方向の寸法が従来の1/21!度に短縮
化でき、しかもこのようなコンデンサ形成用基板にコイ
ル装置ea載した絶縁基板を貼り合せたものであるため
従来のようにコイル装置嵌合用のスペースや、コイル端
末絡げ用の突起部を必要としない友め、全体の高さ寸法
上前記誘電体基板の高さ以内に抑えることができる。
In this way, since one capacitor substrate is constructed by bonding all the back electrode parts of two dielectric substrates in common, the height dimension of the substrate is 1/21 of the conventional size! Moreover, since the insulating substrate on which the coil device EA is mounted is bonded to such a capacitor forming substrate, there is no need for space for fitting the coil device or protrusions for binding the coil terminals, unlike in the past. Therefore, the overall height can be kept within the height of the dielectric substrate.

又、嵌合凹部やコイル端末絡げ用突起を必要としないの
でコイル端末の断線事故や突起の折損事故も発生せず、
製造1穫の簡略化、工数の減少化及び信頼性の向上金も
図ることがで籾る。
In addition, since there is no need for a fitting recess or a protrusion for binding the coil end, there is no risk of disconnection of the coil end or breakage of the protrusion.
It is also possible to simplify the manufacturing process, reduce man-hours, and improve reliability.

本発明は前記実施例に限定されず種々の変形実施が可能
である。例えば前記実施例では各基板1゜1’、IAの
寸法を全て同一のものとし友が、誘電体基板1’、IA
に対して絶縁基板1の高さ方向の寸法を僅か罠短かくし
てもよい。又、各基板毎の電極を接続するための切込部
の形状は7字状に限らすコ字状U字状等を採用してもよ
い。
The present invention is not limited to the embodiments described above, and various modifications can be made. For example, in the embodiment described above, the dimensions of each substrate 1°1' and IA are all the same, and the dielectric substrate 1', IA
In contrast, the height dimension of the insulating substrate 1 may be made slightly shorter. Further, the shape of the notch for connecting the electrodes of each substrate may be limited to a 7-shape, or may be a U-shape or a U-shape.

尚、前記実施例では絶縁基板に搭載する受動素子として
コイル装置を用いたが、この他にチップコンデンサ、抵
抗体等を用いてもよいし、或いはこnらを適宜組み合せ
たものを搭載してもよい。
In the above embodiment, a coil device was used as a passive element mounted on an insulating substrate, but a chip capacitor, a resistor, etc. may also be used, or an appropriate combination of these may be mounted. Good too.

更に、前記第1図に示したフィルタ回路と同一構成のも
のを直列゛接続或いFi並列接続した回路を複合部品と
して作り出す場合には、第7図に示すように前記実施例
の絶縁基板1.第1及び第2の誘電体基板1’、IAを
願次貼夛合せた構造のものに、第2の誘電体基板1Aの
表面にもう一枚の絶縁基板IBft貼り合せてその表面
に複数のコイル装[3’を搭載接続することによってそ
の目的を達成することができる。この場合、基板1,1
′からなる1組のフィルタ回路と、他の基板1人、1B
からなる1組のフィルタ回路との接続関係を適宜変更し
て所望の回路構成を得るようにすることが必要であるこ
とは言う迄もない。尚、リード1s10,10’はそn
ぞn表裏面に複数本取り付けらnることになる。
Furthermore, when creating a circuit in which the same configuration as the filter circuit shown in FIG. 1 is connected in series or in parallel in Fi as a composite component, the insulating substrate 1 of the embodiment as shown in FIG. .. The first and second dielectric substrates 1' and IA are laminated together, and another insulating substrate IBft is laminated on the surface of the second dielectric substrate 1A. This purpose can be achieved by mounting and connecting the coil arrangement [3'. In this case, substrates 1, 1
', one set of filter circuits, one other board, 1B
It goes without saying that it is necessary to appropriately change the connection relationship with a set of filter circuits consisting of the following to obtain a desired circuit configuration. In addition, the leads 1s10 and 10' are
Multiple pieces will have to be attached to the front and back sides.

以上詳述した本発明によnば、小型化及び実装密度の向
上が図nる複合型回路部品を提供できると共に、製造工
程の簡略化及び工数の減少が図nる複合型回路部品の製
造方法を提供することができる。しかも、コンデンサ用
基板とコイル装置用基板を別々に作ることができるため
、製造が極めて容易となり、コイル装置の電極を標準化
するこことが可能なため汎用性に優nたものとなる。
According to the present invention described in detail above, it is possible to provide a composite circuit component that is smaller in size and has an improved packaging density, and also to manufacture a composite circuit component that can simplify the manufacturing process and reduce the number of man-hours. method can be provided. Moreover, since the capacitor substrate and the coil device substrate can be made separately, manufacturing is extremely easy, and the electrodes of the coil device can be standardized, resulting in excellent versatility.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はLC複合フィルタの回路図、第2図はそnを複
合部品化した従来装置の正大図、第3図は本発明複合1
1回路部品の一実施例を示す斜視図、@4図乃至II6
図は前記実施例装置の具体的構成の一例及びその製造方
法を工程順に説明するための図であり、第4図は絶縁基
板の表面図、第5図は第1の誘電体基板の表m図、第6
図は尾2の誘電体基板の裏面図、第7図は本発明の他の
実施例を示す備面図である。 1・・・絶縁基板、i’、IA・・・誘電体基板、2A
t−2As・・・受動素子接続用電極、2B!〜2B−
・・・コンデンサ用電極、2C・・・コンデンサ用電極
電極、 3〜6・・・コイル装置、76〜74.8?8
ル、96〜9h・・・切込部、3A−→A・・・コイル
端末、3B−5B・・・中間タップ、  10A〜10
C・・・リード線。
Fig. 1 is a circuit diagram of the LC composite filter, Fig. 2 is a full-scale diagram of a conventional device in which it is made into a composite part, and Fig. 3 is a circuit diagram of the composite 1 of the present invention.
1. Perspective views showing one embodiment of circuit components, @Figure 4 to II6
The figures are diagrams for explaining an example of the specific configuration of the embodiment device and the manufacturing method thereof in the order of steps, FIG. 4 is a surface view of the insulating substrate, and FIG. Figure, 6th
The figure is a back view of the dielectric substrate of tail 2, and FIG. 7 is a front view showing another embodiment of the present invention. 1... Insulating substrate, i', IA... Dielectric substrate, 2A
t-2As...Passive element connection electrode, 2B! ~2B-
... Electrode for capacitor, 2C... Electrode for capacitor, 3-6... Coil device, 76-74.8?8
96~9h...notch part, 3A-→A...coil terminal, 3B-5B...intermediate tap, 10A~10
C... Lead wire.

Claims (2)

【特許請求の範囲】[Claims] (1)  両面に電極が形成さnた第1と第2の誘電体
基板の共通電極St対向させて固着してなるコンデンサ
基板と、裏面が前記コンデンサ基板の表面に固着さrt
表面に形成さnた複数の電極部に受動素子が搭載接続さ
n友少なくとも1枚の絶縁基板と、各基板の対向辺11
に設けられてそれぞnの電極同志を電気的に接続する複
数の切込部とを有することを特徴とする複合型回路部品
(1) A capacitor substrate formed of a common electrode St of first and second dielectric substrates having electrodes formed on both sides and fixed to face each other; and a back surface fixed to the surface of the capacitor substrate.
Passive elements are mounted and connected to a plurality of electrode portions formed on the surface of at least one insulating substrate, and opposing sides 11 of each substrate.
1. A composite circuit component comprising: a plurality of cut portions each provided in a plurality of cut portions for electrically connecting n electrodes to each other;
(2)少なくとも、両面に誘電体用電極を形成すると共
に辺11に複数の切込St−形成し7tjj11と第2
の誘電体基板を得る工程と、第1及び第2の誘電体基板
の共通電極St−貼着する工程と、絶縁基板の辺i11
Km記誘電体基板の切込部に対応する複数の切込Sを設
ける工程と、この絶縁基板の表面に前記各切込11に迄
達する複数の電極を形成すると共に、各電極間に複数の
受動素子を搭載接続する工程と、前記第1及び第2の誘
電体基板の表面に前記絶縁基板を貼着する工程と、こn
ら各基板の電極部同志會曽記各切込sを介して電気的に
接続する工程とを含むことを特徴とする複合蓋回路部品
の製造方法〇
(2) At least, dielectric electrodes are formed on both sides, and a plurality of cuts St- are formed on the side 11, and the 7tjj11 and the second
a step of obtaining a dielectric substrate of
A step of providing a plurality of notches S corresponding to the notches of the dielectric substrate Km, forming a plurality of electrodes reaching each notch 11 on the surface of this insulating substrate, and forming a plurality of notches S between each electrode. a step of mounting and connecting a passive element; a step of adhering the insulating substrate to the surfaces of the first and second dielectric substrates;
A method for manufacturing a composite lid circuit component, characterized in that it includes a step of electrically connecting the electrode portions of each substrate through each notch s.
JP56128432A 1981-08-17 1981-08-17 Composite circuit part and method of producing same Granted JPS5830119A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56128432A JPS5830119A (en) 1981-08-17 1981-08-17 Composite circuit part and method of producing same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56128432A JPS5830119A (en) 1981-08-17 1981-08-17 Composite circuit part and method of producing same

Publications (2)

Publication Number Publication Date
JPS5830119A true JPS5830119A (en) 1983-02-22
JPH0214770B2 JPH0214770B2 (en) 1990-04-10

Family

ID=14984596

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56128432A Granted JPS5830119A (en) 1981-08-17 1981-08-17 Composite circuit part and method of producing same

Country Status (1)

Country Link
JP (1) JPS5830119A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59149656U (en) * 1983-03-23 1984-10-06 ティーディーケイ株式会社 circuit device
JPS59177914A (en) * 1983-03-28 1984-10-08 日本電気株式会社 Composite part
JPS59213124A (en) * 1983-05-18 1984-12-03 日本電気株式会社 Composite part
JPS59213123A (en) * 1983-05-18 1984-12-03 日本電気株式会社 Composite part
JPS59213125A (en) * 1983-05-18 1984-12-03 日本電気株式会社 Composite part
JPS6258183U (en) * 1985-09-28 1987-04-10
JPWO2017057422A1 (en) * 2015-10-02 2018-04-19 株式会社村田製作所 Thin film type LC component and its mounting structure

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59149656U (en) * 1983-03-23 1984-10-06 ティーディーケイ株式会社 circuit device
JPS59177914A (en) * 1983-03-28 1984-10-08 日本電気株式会社 Composite part
JPS59213124A (en) * 1983-05-18 1984-12-03 日本電気株式会社 Composite part
JPS59213123A (en) * 1983-05-18 1984-12-03 日本電気株式会社 Composite part
JPS59213125A (en) * 1983-05-18 1984-12-03 日本電気株式会社 Composite part
JPS6258183U (en) * 1985-09-28 1987-04-10
JPWO2017057422A1 (en) * 2015-10-02 2018-04-19 株式会社村田製作所 Thin film type LC component and its mounting structure

Also Published As

Publication number Publication date
JPH0214770B2 (en) 1990-04-10

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