JPS582953A - Interruption controlling system - Google Patents

Abstract

PURPOSE:To simplify the control and to prevent the system from being complicated, by generating an interrupt at an optional time to execute a required processing, in the interruption controlling system for the information processing system using a real-time timer. CONSTITUTION:When values set to interrupt time registers 2-4 coincide with the value of a real-time timer 1, interrupt signals are outputted on a basis of contents of corresponding interrupt mask registers 8-10, and contents of registers 11-13 where instruction addresses to be executed next are held are stored in the next instruction address part of a new PSW area 22 for interruption processing on a main storage device, and the new PSW22 is loaded to the PSW of a central processing device, thus executing the interruption processing.

Description

[Detailed Description of the Invention] Regarding this actual wi#i, interrupt control method, III#I
C real time timer 1? This is for use in the EMS-included control system for information processing systems.

W Shikomi Function Company, OII request from outside the system, # & Ai JIklI that occurred inside the layer, and a certain %P due to barking that may occur in the input/output device, processing device 0IJIklI
When an interrupt occurs in %0 that changes the state S+, the execution of the regular operation is temporarily suspended, and the interrupt #I
0 lap 10 yo '3% when control is S to klI pudara^
I) If you divide the inclusive amount by factor, it will be! Shinchetsuta 1
11! ) interrupts, supervisor call interrupts), pre-Datsu five W call interrupts, external interrupts, and input/output interrupts.
Main memory @N is determined for each factor including 1m.

In the area, 111 m W (?regram #
tmtms Wed) is stored as ygv, and further K11f is included IF Katsuo - shouldering friend 01F1
111'& information board has been determined and stored in the castle. Then, the new ν8w is read and the 0 interrupt Jlllll programmer which is set to true) If is set to true, the procedure IIO which is enriched as as with the new ν1W is also very deep.

1*, Interrupt: Therefore, the stored old P8WK contains the address of the next Km line if no interrupt occurs.

rav#i, the operation of the central processing unit 3111F [The control basic tI 111 holds # control information, and its bit configuration is, for example, K, 21m! (1!
14 bits) and consists of Ishibasha, Pit) 11$-3
Ill111 in a snow fight on 1? Boasting code, bit 4
The next Km from 0 to 63, 1 life◆ ahead - Baisi address is a meal fraud. Then, when the central processing unit reads out the instruction and starts executing it, it updates the address of the next instruction with the processing of that instruction added.

Next, use +1 + 111 inclusive mask (110). Interrupts are self-funded when the interrupt master is 11" and is reserved when the interrupt master is 0. Jinrera no!
The star data is stored in the control register.

By the way, companies use real-time timers in information layered systems.
Conventionally, a method has been used to perform the basic operating sequence of a system by controlling interrupts (one type of external interrupts). For example, as shown in Figure 2, 1 real time tie! but! At time l, the system power is turned on and system initialization is executed by interrupt ω, and 〒2C)n
Execute program 1 of the system schedule with @0 interrupt■, and! At the time of 3 and self-interrupt e), the system power is turned off and after that the programmer AD) is executed.
Assuming you have set it. Now, when the input/output device and O information exchange are required during the depth of program 1, program B
As soon as the input/output command is issued, the input/output device starts up, temporarily interrupts the execution of BO, and executes program 0. If the operation of the input/output device ends in the middle of the boomerum 00 depth and you are ready to continue the boogram AB, then if the priority of the boogram 10 is program 0, the interrupt will be 0.
interrupts the execution of program0ram0 and restores the programwpitem IK.Finally, disconnect the source 1 at interrupt 4 of 〒3511.
Execute the program and complete system processing.

In this way, the interrupt control method using the real-time timer in the conventional control system is as follows:
Using the 1l1011111 interrupt time register, set the real-time tie v0411 interrupt time register to perform an interrupt operation when the value (!1~!凰) is -1 followed by the main memory. The new P8vl on the device is executed by the program based on kllW, and the number of layers required is 1. However, at any time, the 1111L central processing device can be interrupted by IAjJA In order to increase the required power operation, KFi, the interrupt time register and the new ysvO contents of the main memory must be managed from the AS 4C. In FIG. 2 IIC, the contents of the interrupt time register are displayed as follows: yl, t2. 'r3e order, the real time timer Φ value matches the above time element register #O contents, and the interrupt is Jl
! If L★Kameru, the tube layer program checks whether the control register #O■Import mask is @"11 or TI,"
l”, the current psvl main memory l!!
The data stored in the IiW area is read from the new pswll castle and set as Iysv meeting*psv. And the current P8W01 [These operations are performed by boogram for each 0 interrupt that updates the entry code and the next instruction address]? ? This has disadvantages, such as the need to rewrite the system, making the management program II#, which increases costs.

The purpose of the present invention is to eliminate such conventional drawbacks, and to provide a program-managed system for managing people and turtles (0#m虻劃).
An object of the present invention is to provide an intrusion sound control method Yt that generates an intrusion and performs necessary treatment.

The sews interrupt control system of the present invention has a cylinder number IIO interrupt time register, an interrupt master register corresponding to these on a one-to-one basis, and a self-replaceable turtle register that holds the address of the next instruction to be depthed. When the value set in the L%ms-included time register matches the value set in the interrupt master register O, the interrupt is set according to the contents of the corresponding interrupt master register.
After inputting the e-interrupt signal to ttm and then supplying the contents of the register holding the depth instruction address pipe to the next instruction address field of the new 281 area for interrupt processing on the main memory, the new PIIW is sent. It is Cao Hui's intention to carry out the PIWK four-card in the central part of the meeting and the IIM management.

Hereinafter, the implementation side pipe of the present invention, No. 381! ) Explain.

1111IKkVTR1In included 1ljlft, (1≦
Interrupt time register #2.3 holds the value of timer 1 and the value of timer 1 on each side. 5.6.7.1111>Include register 2, 3.4Km **Ilom* inclusion mask registers 8, 9゜10, respectively indicating whether or not m extraction is possible.
- Input time register 2, 5.4 ;il corresponding to 1i0
11jlK■) In order to ignore the 11th order command address rm i which should be executed in the order of death, multiple address registers 11.12.13. ν and a moving part circuit are provided.The theory 1llIII is a catfish, 1, and a smart circuit 5.6. ”
Includes the output of 7 and -! Star register 8. GL10
0 output and 0111kllllt 217 > YWi
im 14.15.16.7 > Ym circuit 4. I.J.
5.16 each output 01 & OR circuit 17 that takes the logical sum, and I! II 14.15.160 each output and 7 dresses
z Di and and l
ll118.19,200 Each output 01111 An OR 11 path 21 is provided to take the sum.

First, the operator inputs tiOI! to the eta control time register 2.3.4 using an initialization program when the power is turned on by the operator from the operation panel. Set the liI fables one after another. Similarly, 10% reduction mask register 8.9.10 and address register 11,1
2.13%, in advance, mask information "1' is 9"
0'', and each time JIll#/c sets the first address of the program to be executed 1t@next.

Now, when you go to the toilet to see that the real-time tie YlO value has reached tlK, you will see the real-time timer 10 value and the Tokishima register 20 value t including wb.
Since 1 and 1 match, the comparison circuit δ also sends out an output signal, which is input to AND circuit No. 1. From the other comparator circuit 6.7, the value of the real time timer l and the value of the transfer time register 5, 40 *3. *If x matches, 1/% decrease O
Then, the output signal is sent out tv''.

Output signal from ratio*W step 6, interrupt time register #2
The AND circuit 14 performs a logical product with the interrupt mask register 8 billion M1 corresponding to the interrupt signal, and if an interrupt is possible, an interrupt signal is sent out via the OR circuit 14.

On the other hand, the address race #llO value Ml corresponding to the -) included time register #2 is AND times! If the interrupt signal and logic are taken at - 818 and the AND 11 path 140 output value is sent, it passes through OR 1121,
It is written to the next instruction address section of the IW castle 22 on the main memory.

All of the above operations are performed by the eight-door in the third Wi. From this point on, the orb is normally run in one central processing location.
Just like the interrupt processing, the new interrupt processing is done by Poodaram. 11 is loaded into the psv (register) K from the new rev area 22, and the necessary interrupt layers are performed.

When real-time timer l reaches the value of t2, and tmO
When the value is reached, the operation is exactly the same as the operation when the value of t1 is reached. liJ! The value of the mask register 8.9.10 can be updated at any time by the pipe or operation panel.
In the figure, the value of the real-time timer reaches 1 before program O, which controls communication with the input/output device, is completed! 3, the m*input mask register O value t@o” corresponding to the interrupt time register set to %T3.
Toy3oII! When the program 0 is finished and the value of the write mask register is set to [1'', the value of the 1w read-in Tokishima register with #cT3 set is set to 〒3. 4K]! New.

As explained above, according to the present invention, if you generate a sword in any #model and execute the necessary 'tmm without being affected by the d1 program, you can Since there is no need to provide a large number of entry levels, control is simplified and the complexity of the operating system is prevented.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the PIIW 0 bit configuration, Fig. 2 is an explanatory diagram of control method O using a real-time timer, and Fig. 5 is an embodiment of the present invention. t7 post Ill! l
This is a logic diagram of the integrated control section. 1 is a real poem II tie! , time registers 2 to 10, 6 to 7g comparison circuits,
8-1051m? Inclusive master register, 11-13s
Address register, 14 to 21s gate circuit, new PSV area for interrupts on 22nd generation. Patent applicant: Nippon Telegraph and Telephone Public Corporation Representative: Bento clerk Isomura ■

Claims (1)

[Claims] When the real-time timer O value and the interrupt time register value match, a central processing 1IIIIIIc interrupt is generated, and the contents of the program state ■ are switched between 1 and 9 to handle the interrupt. A write-in temporary register, a write-in mask corresponding to the number of the read-in time register, and the instruction address 1 to the next depth.
Equipped with registers that can be changed by 1, and X at the time of the above interrupt.
The value set in the register and the actual value are displayed! Every time the values of ``K11ll'' and ``K11ll'' are matched, the above instruction address register X#O corresponding to the ``-)'' time is stored in the main memory next to the new program status word for ``-''. The liI mackerel control method is to write to the command address 111, change the contents of the yupudagutem-like mst, and perform ■) komi-number processing II.