JPS5829536B2 - I/O interface - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an I10 interface control scheme for channels and input/output devices I10.

Generally, in the case of a read operation (see Figure 2), when read data preparation is completed in Ilo, 5service I
While setting the n (SRVIN) signal, the BUSI
Set read data to N.

When 5RVIN is detected on the channel side, the read data is latched and the 5service Out signal (5RVIN
OUT).

When 5RVOUT is detected on the I10 side, 5RVIN and B
Reset the data on USIN, and when the next data is ready, Data In (DATIN) and BUSI
Place the next data on N.

The subsequent sequence is Da t instead of 5RVOUT.
a Out (DATOUT) is set and 5R
Processing proceeds in exactly the same way as for VIN.

Td above the sequence is the cable delay between the channel and I10, Tch is the 5RV-IN- in the channel)
Processing time up to SRVOUT set or DATII' + Autopsy M1 set, TIO is 5RVO at Ilo
UT-+DATIN set or DATOUT→5R
This is the processing time up to VIN.

Also, in case of write operation, 5RvOUT or DATOU
When setting T, the channel sets write data to BUSOUT and is controlled in exactly the same way as for reading, except that it is transferred to Ilo.

In the case of the conventional I10 interface, as the data transfer rate of the interface increases, it becomes necessary to reduce Td.
Cable length restrictions will become stricter.

The purpose of this invention is to make the data transfer rate of the high speed I10 interface independent of cable length and to maintain compatibility with conventional interfaces.

To provide an I10 interface control method.

This invention enables synchronous data transfer control for the I10 interface, and allows the interface cable length to be adjusted regardless of the data transfer rate.

The reason why there is a limit on the interface cable length with the conventional I10 interface control method is that Ilo is 5RVIN.
5RVOUT from the channel after sending /DATIN
/Waiting for response from DATOUT, 5RVIN/DATIN
This is to reset the .

So, the channel has 5RVIN/DATI from Ilo.
After N is input, the channel will reach 5RVIN/
If there is a guarantee that DATIN will be processed, the 5RVIN/DATIN signal will not be
Ilo is 5RV from the channel as long as it holds
5RVIN/DATI without waiting for OUT/DATOUT
Reset N and generate a new data transfer request signal 5RVIN.
/DATIN can be set.

A system in which data is transferred by sending out 5RVIN/DATIN pulsed by Ilo while guaranteeing the processing time of such a channel will hereinafter be referred to as synchronous data transfer.

In the case of this synchronous data transfer, Ilo can control the reset of SR■■N/DATIN without waiting for the 5RVOUT/DATOUTCD response from the channel.
This means that there are no restrictions on the length of the interface cable.

Therefore, synchronous data transfer is advantageous in situations where the processing time from the channel can be guaranteed.

The present invention enables Ilo to control both the conventional method and the synchronous method, and allows one to be arbitrarily selected.

Figure 1 shows the circuit at Ilo, and flip-flop 7' (FF) is a flip-flop that selects whether to control according to the conventional 110 interface or to use the synchronous data transfer method, and outputs II I It. When the output is If □ II, the conventional method is used.

Which method to use is 5ETSYN-P and 5ET
It is controlled by the ASYN-P signal, and the signal source may be a command type code output or a preset signal.

If FF1 is reset, 5 from channel
When RVOUT falls (SRVOUT-N="1") F
F2 is set and read data is ready at Ilo (DATAREADY-p=!l I I
I), AND gate 8 and OR gate 9 operate, and 5RVIN is set (SRVIN-P=II I
f) be done.

This 5 RVIN is retained and this S RV
When 5RVOUT from the channel for IN is input (SRVOUT-N="O"), inverter 3 and AND gate 5 operate, FF2 is reset, and S
RVIN is reset.

As described above, conventional I10 interface control is realized.

If FFI is set, 5R from channel
When VOUT falls, FF2 is set.

After that, the read data is ready at I10 (DA
When TAREADY-P="1") and an appropriate input pulse is input from TP-P, AND gate 7 and OR gate 9 operate, and a pulse is set as SRVIN.

The output of the AND gate is output from the delay line 4 and the AND gate 6 to the FF after a certain period of time with an appropriate delay, without depending on the 5RVOUT from the channel.
2 will be automatically reset.

Through the above steps, synchronous data transfer is realized. DAT I N
-The logic regarding DATOUT can also be realized by the logic exactly the same as that in FIG.

Control regarding BUSOUT and BUSIN can be realized with exactly the same control between the conventional method and the synchronous data transfer method.

That is, for read operations, Ilo is 5RVIN
Or while DATIN is set, BUSIN
Data is set on the channel, and the data is latched at the rising edge of 5RVIN or DATIN.

Regarding the write operation, data is set to BUSOUT during the 5RVOUT or DATOUT set period in the channel, and 5RVOUT/DATOUT is set in Ilo.
Data is received at the rising edge of T.

By realizing synchronous data transfer on the I10 interface, this invention eliminates cable length limitations for high-speed I10, and also enables conventional VO interface control.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention, and FIG. 2 is a diagram showing a conventional control sequence. 1.2...Flip-flop, 3...
Ita, 4...delay line. Nnoku-

Claims (1)

[Claims] 1 A transmission line for a data transfer request signal sent from an input/output device to a channel, and a signal sent from a channel to an input/output device that is set in response to the setting of the data transfer request signal and in response to a reset. A transmission line for a data transfer request acceptance signal to be reset, a data bus line from an input/output device to a channel through which data is transferred when data is transferred from an input/output device to a channel, and when the data transfer request signal is sent, and a channel. In an I10 interface having a data bus line from a channel to an input/output device through which data is transferred when transmitting the data transfer request acceptance signal when data is transferred from the input/output device to the input/output device, and a first means for transmitting the data transfer request signal until a data transfer request acceptance signal is returned from the channel in response to the request signal;
a second means for transmitting a pulsed data transfer request signal by resetting the data transfer request signal in response to the data transfer request signal after transmitting the data transfer request signal; I10 characterized by comprising means for selecting one of the means, and means for applying the output of one of the first means and the second means selected by the selection means to the transmission line of the data transfer request signal. Interface control method.