GB1579224A - Handling of independently requested operations in an electronic circuit - Google Patents

Description

(54) IMPROVEMENTS IN OR RELATING TO THE HANDLING OF INDEPENDENTLY REQUESTED OPERATIONS IN AN ELECTRONIC CIRCUIT (71) We, SIEMENS AKTIEN GESELLSCHAFT, a German Company, of Berlin and Munich, Federal Republic of Germany, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement:- This invention relates to the handling of independently requested operations in an electronic circuit.

In complex electronic circuits it is frequently necessary to handle requests for different types of operations, the execution of which requires common components of the circuit and so can not be carried out simultaneously, which requests occur exactly or virtually simultaneously and independently of one another. An important example of such operations in dynamic semiconductor stores (MOS stores) consists in externally requested store accesses and internally triggered operations for regeneration or refreshment of the stored information.

Because the operations can not be carried out simultaneously, provisions must be made for the requests to be classified in time. Previously this problem has been solved by dividing the time into pulse train intervals and by assigning the various operations to different pulse train intervals.

This results in specific requests being handled only at specific times, so that waiting times can occur. Furthermore, in the event of overlaps between timing pulses and request signals, indeterminate triggering pulses for the control unit can arise, the effects of which can only be cancelled by providing additional waiting times (see "IEEE Trans. Electron. Compt." Vol EC-I5, Feb. 1966, pages 108-111 and "IEEE Trans. Comput." April 1973, pages 421, 422).

In many cases it is not possible to dispense with á, possibly regularly, repeated execution of operations of one type, although only operations of another type correspond to the actual purpose of the circuit system. In a dynamic semiconductor store refresh operations are of the one type and external store accesses are of the other type. In this case waiting times which occur in the event of store accesses are particularly disturbing. Therefore this invention seeks to enable a reduction in the occurrence of such waiting times.

According to this invention there is provided a method of handling independent requests for operations of a first and a second type in an electronic circuit, which operations require common parts of the circuit for their execution, wherein in response to each request for an operation of the first type a delay period is commenced, the requested operation of the first type being executed at the earliest at the end of the delay period, wherein in the event of a time relationship between a request for an operation of the first type and a request for an operation of the second type such as to lead to metastable states of control signals required for the execution of the operations, an additional signal is produced which immediately converts the metastable signal states into clearly defined signal states, wherein following the execution of an operation of the first type requests for operations of the second type are handled without substantial delay until the end of the delay period following the next request for an operation of the first type, and wherein the requested operation of the first type is executed directly after the execution of an operation of the second type if the latter lasts until the end of the respective delay period or until a later time than the end of the respective delay period.

In particular the operations of the first type may be substantially regularly requested and the operations of the second type may be irregularly requested. For example if the electronic circuit comprises a store the operations of the first type may be store refresh cycles and the operations of the second type may be external store accesses.

The invention also extends to circuit arrangements for use in carrying out the method recited above. One such circuit arrangement comprises a first gate for controlling the forwarding to a control unit of requests for operations of the first type a second gate for controlling the forwarding to the control unit of requests for operations of the second type, means for determining the delay period in response to each request for an operation of the first type and for con trolling the first gate, a NAND gate the output signal of which serves to control the second gate, an AND gate, inputs of which are supplied with the output signal of the NAND gate, a signal characterising whether the control unit is busy and each request for an operation of the second type, a bistable stage having an asynchronous setting input connected to an output of the AND gate and an inverting output connected to an input of the NAND gate, and means coupling an output of the means for determining the delay period to another input of the NAND gate.

Another such circuit arrangement comprises a first gate for controlling the forwarding to a control unit of a triggering signal, means for determining the delay period in response to each request for an operation of the first type and for producing the triggering signal at the end of the delay period, a second gate for controlling the forwarding to the control unit of requests for operations of the second type, a bistable stage, an AND gate an output signal of which serves to asynchronously set the bistable stage in response to the simultaneous occurrence at inputs of the AND gate of a request for an operation of the second type and a signal formed by inversion and delay of a request for an operation of the first type, a delay circuit connected to an inverting output of the bistable stage, and means for producing a pulse as a result of coincidence of a signal present at a non-inverting output of the bistable stage and a signal produced at an output of the delay circuit and for supplying this pulse to the second gate to bring about a clearly defined opening of the second gate for the request for an operation of the second type.

The invention will be further understood from the following description by way of example with reference to the case of a dynamic semiconductor store and with reference to the accompanying drawings, in which: Fig. 1 is an explanatory diagram; Fig. 2 is a block circuit diagram schematically illustrating devices which are essential for the classification of operations; Fig. 3 schematically illustrates in more detail parts of the circuit shown in Fig. 2 in accordance with an embodiment of the invention Fig. 4 illustrates signals which can occur in operation of the circuit illustrated in Fig. 3; Fig. 5 schematically illustrated another embodiment of the invention; and Figs. 6 and 7 illustrate signals which can occur in operation of the circuit illustrated in Fig. 5.

As already mentioned, items of information stored in a dynamic semiconductor store must be refreshed or regenerated at more or less regular intervals. The period of the refresh cycles is generally selected to be such that the interval of time between two consecutive refresh cycles can be slightly extended without jeopardising the stored information.

Refresh cycles are triggered by refresh requests which are produced in a regular sequence in a refresh control unit. The refresh requests divide the time flow into regular intervals, which are considerably longer than the period of time required for the execution of a refresh operation. Row a of Fig. 1 shows two refresh requests RR which are indicated as being positive pulses.

in response to each of which a refresh operation is carried out as indicated in row c of Fig. 1 after a delay which is determined, for example as shown in row b of Fig. 1, by counting pulses of a relatively high-speed pulse train pulses of which are produced in response to the occurrence of each refresh request. The time between the end of a refresh operation and the arrival of the next refresh request, the delay time, and the duration of each refresh operation are represented in Fig. 1 as time zones 1 to 3 respectively.

A request for a store access for a write or read operation can arrive at any instant of the time flow represented in Fig. 1. Such an operation, like each refresh operation, not only requires access to the storage cells themselves but also requires the use of the associated flow control unit, write and read amplifiers, and so on. External store accesses and refresh operations therefore cannot be executed simultaneously.

External requests which fall into the time zones 1 are handled without delay, as is generally the case for external requests which arrive in the time zones 2. Now, however, measures are undertaken for time classification of the requests. In specific situations which are described in detail below waiting times can arise. External requests cannot be executed in the time zones 3 as refresh operations are already in progress. It should be noted that the time zones 2 and 3 are very much shorter than the time zones 1.

The conditions prevailing in dynamic semiconductor stores also apply to other circuits in which requested operations of two different types require at least part of the circuit commonly for their execution. It is not always necessary for operations of one type to be requested at substantially uniform intervals as is the case with the described refresh operations. However it should be noted that the two types of operation are not handled with entirely equal priority. The operations of the one type are always executed after a delay, whereas the operations of the other type are carried out immediately on request, apart from the slight delays arising from unavoidable signal transit times, except when an operation of the first type is already in progress or the two requests coincide in a quite specific manner.

Fig. 2 schematically illustrates devices required for the classification of requests for refresh operations and requests for external store accesses to a dynamic semiconductor store which is also shown and referenced SP. An assigned flow control unit AST, which is also shown in Fig. 2 and controls the individual processes for the execution of refresh write and read operations, and the store SP will not be considered in detail here as their construction and mode of operation are known and they play no direct role in relation to the invention.

A refresh control unit RST produces refresh requests RR in a regular sequence.

Two gating circuits VSI and VS2 serve to switch through either a refresh request RR or an external request START to the flow control unit AST, the switch through being prevented by a signal BUSY supplied by the flow control unit AST when the store is engaged in a preceding operation. The circuits VSI and VS2 are controlled by output signals of a synchronising circuit SS which, in the event of the simultaneous arrival or overlap of two requests, makes a decision as to which request is to be passed to the flow control unit AST. The forwarding of both requests is prevented for such time as the store is engaged. In the synchronising circuit SS the aforementioned high-speed timing pulses are also formed, from which pulses, by counting, the delay time between the arrival of a refresh request and the beginning of the refresh operation is formed.

The measures provided by the invention considerably reduce the waiting times for externally requested operations in comparison to the average waiting times occurring in the case of constant synchronisation. In particular the danger of the occurrence of metastable stages is reduced; such states can arise in the event of simultaneous requests or the coincidence of a timing pulse with the beginning of a request signal, and necessitate the provision of additional waiting times until they have died out. It is, however, basically impossible to entirely avoid conflicts of this type, but it should be noted that now conflicts can only occur when a refresh request and an external request possess a quite specific time relationship to one another; on average this will rarely be the case. Nevertheless, by appropriate design of the synchronising circuit it must be ensured that even then a non-ambiguous decision is arrived at in favour of an operation of one or the other type.

In the following two alternative forms of the synchronising circuit SS are described for dealing with the conflict situation in different ways.

Referring to Fig. 3, a circuit emphasised by a border of dash-dotted lines constitutes the synchronising circuit SS of Fig. 2, and gates G1 and G9 constitute the gating circuits VSI and VS2 respectively. Fig. 3 also shows a delay element TD. The synchronizing circuit SS comprises edge triggered D-type flip-flops FF1 and FF2, a 4bit synchronous counter Zl, the Schmitttrigger NAND gate G2, AND gates G3, G5, and G10, an inverter G4, Schmitt-trigger inverters G6 and G7, a NAND gate G8, and an RC element comprising a resistor Rl and a capacitor Cl.

Each refresh request RR supplied by the refresh control unit RST passes directly to the gate Gl and also releases the flip-flop FFI, which otherwise is held in a state in which its output Q=0, via a pulseindependent resetting input R. The refresh request RR also starts a start-stop pulse generator which consists of the gate G2 and the feed-back RC element and which produces the counting pulses represented in row b of Fig. 1. The counting pulses are conducted via the gate G3, which is enabled at this time, to the counting input Cup of the counter Zl. When the counter Zl has reached a count of 15, at its carry output CY there is produced a 0 signal, which blocks the gate G3 and prevents the further counting of pulses. The carry signal is inverted by the inverter G4 the output of which is fed to the gate Gl. Upon the occurrence of the carry signal, if the signal BUSY also possesses the logic value 1, indicating that the store is not engaged in an operation, the gate G1 supplies an output signal to the flow control unit AST, representing the delayed refresh request.

The flow control unit AST commences a refresh operation and produces the signal BUSY=0. At the same time, by means of connections which are not illustrated, the refresh request RR is ended and the counter Zl is reset to its initial count of zero.

Shortly before the counter ZI has reached its highest count of 15, i.e. at the count of 14, a signal having the logic value 1 is produced at the output of the gate G5 whose inputs are connected to outputs B, C, and D of the counter (see Figure 4).

Consequently the flip-flop FF2, which has previously been held in a state in which its output Q=0 and which possesses pulseindependent setting and resetting inputs S and R, is released for setting. After a short delay time corresponding to the transit time of the inverters G6 and G7 the flip-flop FFI is set to produce an output signal Q=l, so that a logic 0 is produced at the output of the gate G8. This signal, which in the following is referred to as a start-blocksignal STARTSP, prevents any external request START which may occur from being switched through to the flow control unit AST via the gate G9. Normally, the signal STARTSP retains its (active) logic value 0 until the refresh request RR is terminated on commencement of the refresh operation. Until the conclusion of the refresh operation the signal BUSY then blocks the gate G9 for an external request START.

At all other times an external request START is forwarded to the flow control unit AST with a slight time delay, which compensates the signal transit times in the logic elements and is produced by the delay element TD, provided the flow control unit AST is not currently indicating, by the signal BUSY=0, that the store is already engaged in a previous externally requested operation.

A conflict situation occurs only when an external request START (transition from 0 to I ) arrives simultaneously to the startblock-signal STARTSP (transition from 1 to 0) at the inputs of the gate G10. In this case a narrow pulse can arise at the setting input S of the flip-flop FF2 (which has been released shortly beforehand) and can produce a metastable state at the output Q of this flip-flop. However it is extremely improbable that such a state will arise as a result of the connections, illustrated in Fig.

3, of the flip-flop FF2.

Fig. 4 illustrates signals which can occur at some points of the circuit illustrated in Fig. 3, under the assumption that the startblock-signal STARTSP and an external request START arrive simultaneously at the inputs of the gate G10. Following the occurrence of a refresh request RR (Fig. 4, row a), a relatively long time passes until the counter Zl has reached the count 14, and a signal (row b) having the logic value 1 occurs at the output of the gate G5. The signal at the output of the gate G5 serves to switch over the flip-flop FFI after a short time delay, the output Q of which flip-flop likewise assumes the value 1 (row c) so that the output of the gate G8 becomes 0 (row d).

If, as is assumed, an external request signal START (row e) now arrives simultaneously to the start-block-signal STARTSP at the inputs of the gate G10, a narrow pulse, having an amplitude which may fully or only partially reach the level of the logic 1, occurs at the output of the gate G10 (row t).

This positive-going narrow pulse is only able to set the flip-flop FF2 into a metastable state (row g) which, however, is sufficient to control the gate G8 in a clearly defined fashion, so that the output of the gate G8 reassumes the logic value I (row d). As a result, the narrow pulse at the output of the gate GlO is followed by an additional signal having the value I whereby the flip-floQFF2 is now set in a clearly defined fashion (Q=0).

The metastable state produced in the flipflop FF2 is thus cleared. Shortly afterwards the start signal which has been delayed in the delay element TD arrives at the input of the gate G9 (row h) and meets with clearly defined conditions and is switched through to the flow control unit AST. The externally triggered operation, which is designated in detail by further signals (write, read) thus commences and the signal BUSY=0 which indicates that the store is engaged blocks the gate GI. The signal which arises at the output of the inverter G4 when the counter ZI has reached the count 15 is therefore initially unable to reach the flow control unit AST, and is effective only when the store is no longer engaged, when it triggers a slightly delayed refresh operation.

Fig. 5 illustrates an alternative circuit which can be used to constitute the synchronising circuit SS and gating circuits VSI and VS2 illustrated in Fig. 2. The circuit illustrated in Fig. 5 comprises a start-stop generator SG, a pulse shaper PF, a counter Z2, D flip-flops RF, SF, BF, and NF, delay elements DLI and DL2, a delay element comprising a resistor R2 and a capacitor C2, and gates Gull, G12, G17, G18, and G21, NAND gates G13 to G16 and Gl9, and an inverter G20. Fig. 5 also illustrates the flow control unit AST.

In the circuit of Fig. 5 the known pulse train synchonisation process of dividing the time flow into small intervals and assigning the external requests to these intervals is employed when a refresh operation is to be introduced by a refresh request. At all other times an external request START is processed asynchronously and thus without delay, provided the store is not still engaged with a previous operation. If, however, it is assumed that the store and the flow control unit AST are available (BUSY=I), then a gate control signal BYE=l and the gate G18 conducts an external request START to the flow control unit AST. When no refresh request RR is present the flip-flop BF is asynchronously set to produce a signal S3=1 and other signals Si, S2, and S4 which are combined in the gates Gll,G15,G16, and G17 and which are described further below possess the logic values Sl=0, S2=1, S4=0.

The time intervals for the synchronisation are supplied by the start-stop generator SG which is started by each refresh request RR (Fig. 6, row a). The pulse shaper PF is connected following the start-stop generator SG and supplies two pulse trains TN and TP which are shown in Fig. 6, rows b and c. The pulses of the two pulse series alternate with a mutal spacing of approximately 80 to 100 ns. The pulses of the pulse series TN are counted in the counter Z2 which, following the arrival of the fifteenth pulse, emits the signal Sl which stops the start-stop generator SG.

The signal Sl is also fed to the AND gate Gil and an inverter G22. The signal BUSY, which indicates the current state of the store and has the value 1 when the store is not engaged, is applied to the second input of the AND gate Gull. The output signal BY of the AND gate Gl I thus assumes the logical value 0 whenever the store is engaged or the counter Z has reached its maximum count following a refresh request.

The "0" at the data input D of the flipflop is entered into the flip-flop RF with a falling edge of the signal Sl which is converted into a rising edge by the inverter G22. The signal ZWR at the Q output of the flip-flop RF assumes the value logic 1. The forwarding of the signal ZWR, which serves to initiate a refresh operation, to the store flow control unit AST is however prevented by means of the AND gate G12 until BYZ=I.

Here, the signal BYZ differs from the signal BUSY only by a delay of the falling edges, effected by a delay circuit DLI. After the maximum count has been reached in the counter ZS, the requested refresh operation is thus executed as soon as the store is free.

After commencement of the refresh operation the counter Z2 is reset and the flip-flop RF set, via connections riot shown in Figure 5.

It is assumed above that no external request occurs. The flip-flop SF (startsynchronising flip-flop) which has been reset, assuming a previous store operation, by pulses TP therefore is not set either in pulse-controlled fashion or asynchronously.

Accordingly the output of the gate G13 is high and the signal S2 produced at the output of the gate G14 is inverse to the refresh request RR. The signal S2 when low blocks the direct access of external requests START to the flow control unit AST, but this blockage can be discontinued by means of the flip-flop SF. Thus if an external request START arrives during the interval of time between the commencement of a refresh request RR=I and the execution of the requested refresh operation (see Fig. 6, row e), the externally requested operation is still executed. Fig. 6 shows the most important signals which are of importance here. The signal designations which have been used are referred to in the following.

In row k the portions EXOP and ROP designate an externally requested operation and a refresh operation respectively.

With the first pulse of the pulse series TP following the arrival of an external request (row e), the request is transferred into the flip-flop SF (row n-i.e. SF is set. While the flip-flop SF is set, pulses of the pulse series TN occur at the output of the gate G14 in the signal S2 (row cut). At least one such pulse occurs. If it is assumed that at this time the store is not engaged with a previous operation, this pulse passes through the gates G15, G16, and G17 and, as the signal BYE, opens the gate circuit G18 for the external request START. The external request thus reaches the flow control unit AST and triggers the requested operation. As a result, the signal BUSY supplied by the flow control unit AST and the signal BYZ assume the value 0, so that the gate G12 is prevented from forwarding the refresh request to the flow control unit AST if the counter Z2 reaches the count of 15 before the conclusion of the store operation. At the same time, the signal BY at the ouput of the gate Gl 1 becomes 0, and the next pulse of the pulse series TP enters this value into the flip-flop BF. The output signal S3 of the flip-flop BF causes the signal BYE also to become 0 to block the gate G18 from forwarding any new external request START which may possibly arrive. If a new external request START arrives after the end of the previously externally requested store operation but before the maximum count of the counter Z2 is reached, this new external request is also processed, but if the maximum count of the counter Z2 is reached during the execution of the externally requested store operation, the waiting refresh operation is executed immediately at the end of the store operation.

By making available the two phaseshifted pulse series TP and TN after the arrival of a refresh request RR, and by providing an interval between the end of each pulse of one pulse series and the beginning of each pulses of the other pulse series, it is possible to classify in time the asynchronously arriving requests in such a way that metastable states of the control signals for the flow control unit AST, which could jeopardize the latter's satisfactory functioning generally do not occur. If, however, an external request START arrives at approximately the same time at which the gate control signal BYE assumes the binary value 0, as a result of a refresh request RR which has arrived shortly beforehand, at the output of the gate G18 there is produced a very narrow pulse whose amplitude may be smaller than the normal signal range. As a result of differing response sensitivities and response times of the elements in the flow control unit AST, such a pulse can cause individual elements to respond, whereas it leaves other uninfluenced or sets these into metastable states.

Since it is basically impossible to entirely prevent the occurrence of ambiguous signal states during the processing of asynchronous and independent requests, as already mentioned a subsequent elimination of the disturbing outcomes must be provided as rapidly as possible. In the circuit illustrated in Fig. 5 this is effected by a re-start device which consists of the flipflop NF, the gate Gl9, and the delay element composed of the resistor R2 and the capacitor C2.

For a short length of time following the arrival of the request signal RR, a signal RR*, which is derived from the request signal RR by inversion and delay in the delay element DL2 by approximately 50 ns, retains the value 1. As it has been assumed that an external request START arrives approximately simultaneously, and the store is not engaged in an operation (BY=I), at the output of the gate G21 there occurs a signal which asynchronously sets the flipflop SF via its input S. The flip-flop NF in the re-start device is set at the end of a previous refresh request. Following the asynchronous setting of the flip-flop SF, the gate Gl9 emits a pulse, the duration of which is determined by the delay of the delay element R2, C2. The signal S4 produced at the output of the gate G19 is fed to the gate G16, and, via G17, brings about a short but clearly defined opening of the gate G18 for the external request START. The flip-flop NF is reset again with the first pulse of the pulse series TN, this preventing a re-start pulse occurring at any other time. Fig. 7 illustrates signals concerned in the production of a re-start pulse, the time scale in Fig. 7 being considerably enlarged in relation to that in Fig. 6.

WHAT WE CLAIM IS: 1. A method of handling independent requests for operations of a first and a second type in an electronic circuit, which operations require common parts of the circuit for their execution, wherein in response to each request for an operation of the first type a delay period is commenced the requested operation of the first type being executed at the earliest at the end of the delay period, wherein in the event of a time relationship between a request for an operation of the first type and a request for an operation of the second type such as to lead to metastable states of control signals required for the execution of the operations, an additional signal is produced which immediately converts the metastable signal states into clearly defined signal states, wherein following the execution of an operation of the first type requests for operations of the second type are handled without substantial delay until the end of the delay period following the next request

Claims (9)

**WARNING** start of CLMS field may overlap end of DESC **. asynchronously arriving requests in such a way that metastable states of the control signals for the flow control unit AST, which could jeopardize the latter's satisfactory functioning generally do not occur. If, however, an external request START arrives at approximately the same time at which the gate control signal BYE assumes the binary value 0, as a result of a refresh request RR which has arrived shortly beforehand, at the output of the gate G18 there is produced a very narrow pulse whose amplitude may be smaller than the normal signal range. As a result of differing response sensitivities and response times of the elements in the flow control unit AST, such a pulse can cause individual elements to respond, whereas it leaves other uninfluenced or sets these into metastable states. Since it is basically impossible to entirely prevent the occurrence of ambiguous signal states during the processing of asynchronous and independent requests, as already mentioned a subsequent elimination of the disturbing outcomes must be provided as rapidly as possible. In the circuit illustrated in Fig. 5 this is effected by a re-start device which consists of the flipflop NF, the gate Gl9, and the delay element composed of the resistor R2 and the capacitor C2. For a short length of time following the arrival of the request signal RR, a signal RR*, which is derived from the request signal RR by inversion and delay in the delay element DL2 by approximately 50 ns, retains the value 1. As it has been assumed that an external request START arrives approximately simultaneously, and the store is not engaged in an operation (BY=I), at the output of the gate G21 there occurs a signal which asynchronously sets the flipflop SF via its input S. The flip-flop NF in the re-start device is set at the end of a previous refresh request. Following the asynchronous setting of the flip-flop SF, the gate Gl9 emits a pulse, the duration of which is determined by the delay of the delay element R2, C2. The signal S4 produced at the output of the gate G19 is fed to the gate G16, and, via G17, brings about a short but clearly defined opening of the gate G18 for the external request START. The flip-flop NF is reset again with the first pulse of the pulse series TN, this preventing a re-start pulse occurring at any other time. Fig. 7 illustrates signals concerned in the production of a re-start pulse, the time scale in Fig. 7 being considerably enlarged in relation to that in Fig. 6. WHAT WE CLAIM IS:

1. A method of handling independent requests for operations of a first and a second type in an electronic circuit, which operations require common parts of the circuit for their execution, wherein in response to each request for an operation of the first type a delay period is commenced the requested operation of the first type being executed at the earliest at the end of the delay period, wherein in the event of a time relationship between a request for an operation of the first type and a request for an operation of the second type such as to lead to metastable states of control signals required for the execution of the operations, an additional signal is produced which immediately converts the metastable signal states into clearly defined signal states, wherein following the execution of an operation of the first type requests for operations of the second type are handled without substantial delay until the end of the delay period following the next request for an operation of the first type, and wherein the requested operation of the first type is executed directly after the execution of an operation of the second type if the latter lasts until the end of the respective delay period or until a later time than the end of the respective delay period.

2. A method as claimed in Claim 1 wherein the operations of the first type are substantially regularly requested and the operations of the second type are irregularly requested.

3. A method as claimed in Claim 2 wherein the electronic circuit comprises a store, the operations of the first type are store refresh cycles, and the operations of the second type are external store accesses.

4. A method of handling independent request for operations substantially as herein described with reference to Figures 1 to 4 of the accompanying drawings.

5. A method of handling independent requests for operations substantially as herein described with reference to Figures 5 to 7 of the accompanying drawings.

6. A circuit arrangement for use in carrying out the method of any one of claims I to 3 comprising a first gate for controlling the forwarding to a control unit of requests for operations of the first type, a second gate for controlling the forwarding to the control unit of requests for operations of the second type, means for determining the delay period in response to each request for an operation of the first type and for controlling the first gate, a NAND gate the output signal of which serves to control the second gate, an AND gate, inputs of which are supplied with the output signal of the NAND gate, a signal characterising whether the control unit is busy and each request for an operation of the second type, a bistable stage having an asynchronous setting input connected to an output of the AND gate

and an inverting output connected to an input of the NAND gate, and means coupling an output of the means for determining the delay period to another input of the NAND gate.

7. A circuit arrangement as claimed in Claim 5 and substantially as herein described with reference to Figures 3 and 4 of the accompanying drawings.

8. A circuit arrangement for use in carrying out the method of any one of Claims I to 3 comprising a first gate for controlling the forwarding to a control unit of a triggering signal, means for determining the delay period in response to each request for an operation of the first delay period, a second gate for controlling the forwarding to the control unit of requests for operations of the second type, a bistable stage, an AND gate an output signal of which serves to asynchronously set the bistable stage in response to the simultaneous occurrence at inputs of the AND gate of a request for an operation of the second type and a signal formed by inversion and delay of a request for an operation of the first type, a delay circuit connected to an inverting output of the bistable stage, and means for producing a pulse as a result of coincidence of a signal present at a non-inverting output of the bistable stage and a signal produced at an output of the delay circuit and for supplying this pulse to the second gate to bring about a clearly defined opening of the second gate for the request for an operation of the second type.

9. A circuit arrangement as claimed in Claim 7 and substantially as herein described with reference to Figures 5 to 7 of the accompanying drawings.