JPS5828609B2 - Tokushiyumei Reishiori Sochi - Google Patents

Description

[Detailed description of the invention]

TECHNICAL FIELD This invention relates generally to data processing devices, and more particularly, to data processing devices capable of executing distinct classes of instructions. BACKGROUND OF THE INVENTION A central processing unit in a data processing device is characterized by being capable of executing a set of instructions, commonly known as machine instructions. These instructions are typically ``word-oriented.'' That is, an instruction operates on a single data food whose length is equal to the number of digital bits in a word in the storage device storing the instruction. However, like floating point arithmetic operations,
It is sometimes desirable to perform operations on data that require two or more words of storage. Data used in floating point functions is usually stored as fixed point binary numbers with a decimal point separating the integer and fractional parts. However, floating point operations are performed on numbers in floating point format. Therefore, it is necessary to convert fixed point numbers to floating point format consisting of an exponent and a mantissa. In binary notation, the mantissa has the binary point immediately to the left,
It is a decimal number with a sign bit to the left of the binary point. The exponent value represents the power of "2" by which the mantissa is multiplied to obtain fixed point format. Typically, the mantissa is "normalized" by removing leading zeros, shifting the mantissa to the left, and simultaneously decreasing the exponent. Normal "word-oriented" instructions cannot operate on floating point numbers. Therefore, it is common to have a separate class of instructions, such as floating point instructions, that can handle this data. Even though the instructions are in a separate class, programs can use them to simplify their programming tasks.
It is highly desirable to be able to mix both machine and floating point instructions. Floating point instructions represent a special class for special applications. Other classes may be defined for other applications. For example, a class of instructions may be based on various trigonometric functions, such as instructions for directly obtaining sine and cosine. Thus, a data processing device capable of executing a special class of instructions becomes more flexible if the functions performed by that class can be easily modified without requiring significant transformations to the central processing unit. is desirable. Although floating point instructions are described in this specification as an example of a class of instructions that are distinct from ordinary machine instructions that a central processing unit can normally execute, the present invention In addition to decimal point instructions, there may be other special classes of instructions that are different from ordinary machine instructions that a central processing unit can normally execute, and the present invention applies equally to all these special classes of instructions. Therefore, in this specification, the term "special instructions" is used to mean all of these special classes of instructions, including floating-point instructions; The term "special instruction processing unit" is used to refer to a specially designed processing unit capable of executing instructions. In some prior art data processing machines, the central processing unit includes special circuitry for executing special instructions. Even with this "hardware" method, floating point instructions are
Typically, significantly more time is required to complete the operation than it would take to perform a normal machine instruction. When a central processing unit executes all instructions sequentially, including floating point instructions, the addition of floating point instructions greatly increases the total time required to complete a given program. Furthermore, the hardware method requires that the circuit be incorporated into the central processing unit when manufactured, so that special classes of instructions in the central processing unit are predefined. Functions performed by special classes are less easily modified. Another method is to use subroutines from the set of machine instructions to implement floating point functions. The central processing unit only uses floating point instructions as instructions to direct the processor to execute the appropriate subroutine. This method allows the functions performed by special classes of instructions to be changed relatively easily. However, this method is usually much slower than hardware methods. Other prior art data processing devices use separate functional modules in parallel. Each module performs a separate function. It operates independently by retrieving data directly from, or conversely storing, data directly from the storage device. For floating point instructions, each module operates according to a single floating point instruction or at most a limited group. The modules operate in parallel, so two or more operate at the same time. Although the time required to perform a single operation is approximately the same as traditional hardware methods, the parallel nature of the modules significantly reduces the time required to execute programs containing special instructions. Decrease. Circuit redundancy is necessary because each module must be able to operate independently. Each module typically performs only one function and cannot be easily converted for other functions. Until now, this method of using parallel modules has been limited to large data processing equipment. Problems with the Prior Art The first two of the three conventional methods described above for processing special instructions (e.g., floating point), i.e., the central processing unit simply processes the special instruction as any other instruction. In the subroutine method in which the central processing unit jumps to a subroutine in order to process the special instruction, the central processing unit is already used to process the special instruction. It has the disadvantage that other processing cannot be performed. In addition, the third conventional method has the problem that a large number of processing devices are connected in parallel, and each module requires an additional circuit to enable parallel operation. ing. OBJECTS OF THE INVENTION Accordingly, it is an object of the present invention to provide an apparatus connectable to a central processing unit for executing a special class of instructions that can be mixed with normal machine instructions. It is another aspect of the invention to provide an apparatus for processing special classes of instructions operating in parallel with a central processing unit.
This is one purpose. Yet another object of the invention is to provide an apparatus for executing a specialized set of instructions, yet in which the functions performed by the instructions can be easily changed. SUMMARY OF THE INVENTION The present invention provides interconnection and synchronization between the operation of a central processing unit and the operation of a special instruction processing unit for processing special instructions such as floating-point instructions. The purpose is to enable these devices to operate in parallel while avoiding connections, thereby reducing the overall cost of the device and increasing the processing speed of the device. That is, according to the present invention, the central processing unit is enabled to transfer a special instruction to the special instruction processing unit, and while the special instruction processing unit is executing the special instruction,
The central processing unit is enabled to perform other processing operations. For example, the central processing unit may perform interrupts or perform other housekeeping operations that do not depend on results from the special instruction processor while the special instruction processor is executing the special instruction. More specifically, according to the present invention, a special instruction processing unit is provided for executing special instructions of an independent class identified by specific instruction codes, and a central processing unit is configured to execute these codes. Through a series of control signals that identify, disable itself, and are sent between the central processing unit and its special instruction processing unit, the special instruction processing unit executes its special instructions in parallel with the central processing unit. Execute. After some preparatory steps, the central processing unit can return to its operating program and execute any other machine instructions in sequence, while the special instruction processing unit also operates. Therefore, if many machine instructions are placed between special instructions, the central processing unit will not experience too much delay in operation. Within the special instruction processing unit that actually executes the special instructions, A control circuit decodes the instruction and generates the signals necessary to execute it. The device also includes storage registers to hold data. The control circuit is independent of the central processing unit. Because
Various devices can be connected to the central processing unit to create a data processing device that is responsive to other classes of instructions. The invention is pointed out with particularity in the claims. A more complete understanding of these and other objects of the invention will be gained from the following description, taken in conjunction with the accompanying drawings. Although the invention is applicable to many data processing devices, it is most readily understood with respect to specialized data processing devices. One such device is disclosed in U.S. Pat. No. 614,741, which patent is assigned to the assignee of the present invention and is incorporated herein by reference. Now, looking at FIG. 1, the central processing unit 10
It is located at the center of the data processing device shown in the figure. It typically executes program instructions obtained sequentially from storage 11. Peripheral devices 12, such as input/output typewriters and magnetic disk or drum memories, are also connected in parallel to the central processing unit 10 and the storage device 11 by busbars. When central processing unit 10 decodes a special class of floating point instructions, or other instructions, a series of interactive steps occur between central processing unit 10 and the unit 13 that actually executes the special class of instructions. It happens in During these steps, instructions pass to the device (hereinafter referred to as floating point unit 13). Once an interactive step is completed, the floating point unit 13 performs the instructed function without further interaction with the central processing unit. A floating point unit 13 is used to execute floating point instructions.
operates on floating point numbers and contains circuitry for this purpose. Still referring to FIG. 1, index calculation logic 14 processes index and other data information. Fraction calculation logic 15 processes the fractional portion of floating point numbers. Scratch pad accumulator register device 1
6 contains several general purpose registers used to store data and transfer between registers. Each register in the register device 16 is designated by a number of ``words'', using the term ``words'' to identify a group of n digital bits that are typically stored as a ``word'' in the storage device 11. Scratch pad accumulator register device 1
6, each word constitutes a register byte, and the location of the register byte is identified by the register number and byte number. For example, Ac1

[0] identifies the lowest register byte location of device 16, while Ac1[3] identifies the highest register byte location. Several busbars connect central processing unit 10 with floating point unit 13 and circuitry within floating point unit 13. Address information is sent from the arithmetic processing unit 10 to the address bus 11
move through. Whenever central processing unit 10 "wants" the result of an operation performed within floating point unit 13, it receives the data via bus 18. Data transfer from central processing unit 10 occurs through data bus 19. Bidirectional bus 20 routes control signals between the two devices, as will be explained later. Bus 21 within floating point unit 13 transfers data from device 14 to device 16, while bus 23 returns information therefrom. Similarly, the busbars 23 and 24 are connected to the fraction calculation logic unit 15.
and vice versa, respectively. When the central processing unit 10 executes a series of machine instructions,
It performs the basic operations shown in Figure 3A. Step 201 takes an instruction from the location identified by program counter 51 of storage device 11 shown in FIG.
increase. It then executes the instruction in step 202 if step 203 determines that the instruction is not a floating point instruction. This process occurs iteratively until instruction decoder 52 (FIG. 1) receives a floating point instruction. Whenever instruction decoder 52 receives a floating point instruction, step 203 branches to step 204. The program counter 51 is automatically incremented (advanced) as usual when an instruction is fetched, but if the instruction is decoded as a special instruction (floating point instruction), the program counter 51 Counter 51 is decremented (advanced) and therefore returned to its original position (step 204). At this location, program counter 51 points to floating point instructions in storage. The contents of the program counter 51 are as follows:
13 and then loaded into the special instruction processing unit (step 107). Therefore, even if the central processing unit is interrupting or performing other operations in parallel with the operations of the special instruction processing unit, the special instruction processing unit has a record of the storage location of the instructions it is processing. This means that In step 205, controller 53 (FIG. 1) responds to the signal in command decoder 52 by generating the FPATTN signal through a line in control bus 20. Once step 205 is completed, central processing unit 10 returns to a wait state until floating point unit 13 transfers the FPSYNC signal. However, during this state, the central processing unit 10
It can execute interrupt routines or perform other functions. However, it cannot process any instructions within the program that is being executed. At the time of generating the FPATTN signal in step 205, floating point unit 13 may or may not be processing a previous floating point instruction. If floating point unit 13 is occupied, central processing unit 10 remains in a wait state until floating point unit 13 finishes its previous operation. As floating point unit 13 completes each instruction, it follows steps 101, 102 and 103 shown in FIG. 3A.
Execute. In step 101, control 55 (shown in FIG. 2) disables the FPREQ signal. When the FPREQ signal is asserted, floating point unit 13
indicates that it expects data transfer through one of the buses 18 or 19. Then, the control circuit 55 controls the floating point status register 31
The contents of the accumulator multiplexer (ACMX
) 35, this ACMX: can selectively transfer 1 or 2 words in parallel into the register device 16. In this case, the status word moves to the Ac1[O] register byte location. A bus multiplexer (BMX) 37 connects the contents of the Ac1[O] byte position to the scale register 30, and the λ register 30 connects the contents of the Ac1[O] byte position to the scale register 30 onto the bus 18 or the exponential logic unit 34.
Store data for transfer to. In step 103, control 55 causes the address on bus 17 to be transferred to register device 16 through data input multiplexer (DIMX) 32 and exponent multiplexer (EMX) 33, exponent logic unit 34 and accumulator multiplexer 35. Open the passage. Once this path is open, control 55 enters a wait state and does not perform any other functions until it receives the FPATTN signal from central processing unit 10 via control bus 20. Still referring to FIGS. 2 and 3, after controller 55 in floating point unit 13 enters the wait state in FIG. 3A, the central processing unit generates the F PAT T N signal in step 205. Assuming that, controller 55 responds to the FPATTN signal by performing steps 104-110. When the F PAT T N signal reaches control 55, the BR
The contents of register 55 are transferred onto data bus 19 and into instruction register (FIR) 43. After performing these functions in step 104, the controller performs step 105 by nosetting registers 44s and 44d that store sign information within floating point unit 13. Then, in step 106, control 55 generates the FP pan Q signal. At the same time, the program counter 51 (10th) contains the storage address for the floating point instruction. This address is passed through the address bus 17 and the previously opened path to the Ac1 [1] Move into the register byte location. This instruction register 43 is associated with an instruction decoder provided in the control circuit 55 of FIG. 2. One group of instructions in the floating point class is the fixed point number to a floating point number and vice versa. If the instruction is a conversion instruction, step 108 branches to step 109, which converts the floating point unit 1 to a floating point number and vice versa.
3 to execute the conversion. Step 110 enables the next generation of the FPSYNC signal. Next, control 55 causes central processing unit 10 to perform FPAT again.
It returns to the waiting state until it generates a TN signal. The FPSYNC signal is transmitted after a short delay to allow certain signals to be processed and certain other preparatory operations to occur. Referring now to Figures 1 and 3C, when floating point unit 13 enters this wait state, central processing unit 10 and particularly control 53 is waiting for the FPSYNC signal. When this occurs, central processing unit 10 sends the status word in input register 30 (FIG. 2) to bus 18 and BR
Processing is performed by loading the BR register 55 through the MX multiplexer 54. If further address calculations are required to define the data, control 53 performs them in step 201. Control 53 then generates a PPATTN signal for transmission through control bus 20 to control 55 of FIG. After performing step 208, the system enters one of two wait states depending on the data address contained by the floating point instruction. Each floating point instruction has a specified address that can be in one of several modes. One of these is the mode O address. When a mode O address exists, data for the floating point unit is stored in a general-purpose register within the central processing unit 10, or
or in a register within device 16. If this is true, step 209 branches to wait state 210; otherwise the system branches to wait state 211. When floating point unit 13 receives the FPATTN signal, it branches according to these specific instructions. Generally speaking, the device 13 and the central processing unit 10
then FPSYNC from floating point unit 13
and FPREQ signals and interact under the control of the FPATTN signal from central processing unit 10. Figure 3D is a general flow for the operation of the central processing unit during this interoperating state. If the control 55 generates the FPSYNC signal when the processor is waiting for a specified address in mode O, the central processing unit 10 determines whether a "write register" signal is issued. Step 212 is used to determine . This signal indicates whether data needs to be loaded into one of the general purpose registers within processing unit 10. If the signal is asserted, step 212 branches to step 213 where data bus 18 and bus multiplexer 5 are transferred from accumulator register 16 to bus multiplexer 5.
4, data is transferred for storage into registers. Since no further interaction is required between the central processing unit 10 and the floating point unit 13, step 21
3 returns control 53 to step 201 and central processing unit 10 fetches the next instruction. On the other hand, while the arithmetic processing unit 10 is in the waiting state 211,
If floating point unit 13 generates the FPSYNC signal, control 53 uses step 214 to check the state of the FPREQ signal. If there is no FPREQ signal, meaning no further interaction is required, step 214 returns control 53 to step 201. If the FPREQ signal is present, the incoming data should be transferred. Other control signals generated by floating point unit control 55 determine the direction of data transfer. In order to load data into the storage device 11, step 2
15 goes to step 216 where the central processing unit 10 loads the contents of the BR register 55 into the storage device 11. If the data is to be loaded from storage 11, step 217 performs this function and transfers the data to BR.
Load into register 55. A busbar address register (not shown) within central processing unit 10 is incremented at step 218, completing one cycle of sea fencing for central processing unit 10, so that at step 219, control 53
generates the FPATTN signal and then enters the wait state 211
Move to. As previously mentioned, this processing cycle occurs in central processing unit 10 regardless of the particular instruction. Figures 3E, 3F and 3G generally illustrate the steps used by floating point unit 13 in response to different instructions. In FIG. 3C, step 112 goes to step 113 for instructions that are not appropriate. When this occurs, step 113 causes the FPSYNC pulse to be generated, immediately after step 114 disables the F P REQ signal. Control 55 also sets a constant indicating the nature of the inappropriate instruction to AC7[
0) Store in register byte locations, generate any necessary interrupt signals, and store associated data in steps 115 and 116. The system then automatically returns to step 101. When the FPSYNC signal goes to the central processing unit 10,
Step 214 of FIG. 3D takes the 1-NOJ branch and central processing unit 10 immediately begins executing its next instruction, depending on any possible interrupts. At the time of the branch, step 111 branches to steps 118-120 if storage cycles are no longer needed for data transfer to or from memory. Step 118 enables control 55 to generate the FPSYNC signal, and then step 119 disables the FPREQ signal. The command is then executed. During this time control 55 generates the FPSYNC signal. Central processing unit 10 immediately returns to the next program instruction. Once the repeat instruction is complete, step 120 returns control to step 101 so that a termination sea fence is executed. When it is necessary to obtain data from storage device 11, step 121 (FIG. 3E) takes control to step 122.
-132 are executed. In step 122, control asserts the FPSYNC signal. If any address modification is required, control 55 outputs the INCADR signal (steps 123 and 1 of FIG. 3F).
24), and the central processing unit 10 generates this signal,
Used to control whether it executes step 218. Next, in step 125 the control generates an FPCI signal;
Then wait for the F PAT T N signal. When control 55 receives that signal, it loads the data into the designated register within device 16. The FPCI signal indicates the direction in which data is moving. If more data is to be loaded, step 127 goes to step 128 and control 55 loads another F P
Generate the SYN C signal and return to step 123. Once all words have been loaded, step 127
goes to step 130 where it again energizes the FPSYNC signal, followed by step 131 where it de-energizes the FPREQ signal. Central processing unit 10 may then return to step 201. In step 132, control 55 executes floating point instructions before returning to the termination routine that began in step 101. A similar set of steps occurs when it is necessary to load data from register device 16 into storage device 11. When control 55 decodes a store instruction, it moves the data to input register 30, then asserts the FPSYNC signal and causes the FPC■ signal to indicate an output operation. When central processing unit 10 receives the F PS YN C signal, it stores the data according to step 217 (Figure 3D). If another word is to be stored, step 135 branches to step 136 after the next FPATTN signal, where the need for address modification is determined. If address correction is necessary, step 137
Generate ADR signal. Once all words have been stored, control 55 takes the "NO" branch from step 135, sets flip-flop 76 at step 141, and returns to the termination routine beginning at step 101. A better understanding of the manner in which control signals are exchanged will be gained by reference to FIG. 4, which shows some details of control 55. The leading edge of the FPATTN signal sets flip-flop 70, thereby energizing the AND gate and providing a set signal to flip-flop 73, which when set generates the FPREQ signal. This signal indicates that a data transfer is about to occur, and control 55 responds to the DSEL signal to generate the DSEL signal, step 106 of FIG. 3B.
Occurs when corresponding to a step such as NAND gate 301 produces a positive FPCI signal when flip-flop 73 is set, and the flip-flop represented by its output conductor 85 does not issue a READ signal. This means that a write operation will occur. When an instruction requests the transfer of data in a read operation? 1ilt 155 issues a READ signal on conductor 85 so that no FPCI signal is issued. Flip-flop 73 continues to generate the FPREQ signal until flip-flop 304 is reset. The trailing edge of the clock pulse from NAND gate 305 resets flip-flop 304. This indicates that some internal condition has occurred that requires termination with the subsequent T2 clock pulse.
Occurs in response to a signal. The rear end of the shellfish RESET signal is also clocked into the flip-flop 73 to reset it, thereby deactivating the FPREQ signal. In FIG. 3, setting flip-flop 76 to assert the FPSYNC signal (eg, step 110 in FIG. 3C) respectively causes timing and control unit 302 to generate the 5YNC signal. This signal energizes the gate door 4 so that the subsequent device 302
The T3 timing pulse from
The set of S will direct you towards energy. The output of flip-flop 76 energizes a NAND gate and subsequent inverter 307 to generate a positive T2 pulse at FP.
It is sent to the bus bar 20 as a SYNC pulse. The output from NAND gate 306 causes the trailing edge of each FPSYNC pulse to reset flip-flop 76, disabling further FPSYNC pulses until device 302 generates the next 5YNC signal. Whenever flip-flop 304 resets,
It disables flip-flop 16 by providing an overriding reset signal to the reset Rλ force through OR gate 311. Flip-flop 76 also resets in response to certain conversion commands. When these conditions occur, device 302 generates the C0NV and T4 signals and provides two inputs to AND gate 310. A subsequent clock (CLK) pulse is sent through enabled AND gate 310 and OR gate 311 to reset flip-flop 76. Two other signals act on flops 73 and 76. Central processing unit 10 decodes the floating point instruction;
If an interrupt signal is received, it is
You may terminate further communication with. When this occurs, control 53 within the central processing unit
Generates the TRCLR signal, which resets flip-flop 10 directly through OR gate 312, thereby disabling gate 72. When control 55 subsequently generates the DSEL signal, gate 7
2 prevents it. If the flip-flop was previously set when the INTRCLR signal appears, gate 313 will
4 is activated to send the INIT signal and directly set the flip-flop 304. The central processing unit outputs INI every time it is turned on.
A T signal is generated, which constitutes the start signal. Setting flip-flop 304 removes one of the reset inputs to flip-flop 76 so that subsequent 5YNC and T3 pulses can set flip-flop 76. Control 302 also generates the INCADR and "Write Register" signals mentioned above in response to signals that depend on the particular instruction being decoded. Here, as mentioned above, the FPATTN signal (transfer signal), which plays an important role in the operation of the device of the present invention, and the FP
The SYNC signal (synchronization signal) and FPREQ signal (control signal) will be explained together. FPATTN (Floating point Att
The CPU 20 signal is generated by the central processing unit to indicate that the central processing unit is requesting some operation of the special instruction processing unit. For example, when the central processing unit transfers a special instruction to the special instruction processing device (see step 205) or when transferring an operand to the special instruction processing device (step 125),
After ``Wait for FPATTN signal''), this FPA
Generates TTN signal. In addition, when the central processing unit receives data from the special instruction processing unit for transfer to the storage device, the central processing unit
generate a TTN signal (following step 140)
(See Waiting for TTN signal). FPSYNC signal (Floating Port S
The ynch-ronizing signal is generated by the special instruction processor to indicate that the special instruction processor requires service by the central processing unit. For example, if the instruction is an illegal instruction, the special instruction processor generates this FPSYNC signal to cause the central processing unit to retrieve the contents of the special instruction processor's status register (step 113). reference). The special instruction processing unit may also be used with the FPSY when it is necessary to transfer data to or from the storage device.
1'C signal is generated (steps 134 and 122).
est) signal is generated by the special instruction processor to indicate that the special instruction processor requires service by the central processing unit regarding an operand. For example, if the special instruction processor requires address calculation, the special instruction processor will generate this FPREQ signal (see step 106). What should be noted here is that the special instruction processing device
If the central processing unit only generates the REQ signal, the central processing unit will not operate, and the FPSYNC signal will be sent from the special instruction processing unit.
This means that it operates only after receiving a signal (see step 110). The special instruction processing unit also generates this FPREQ signal (set in step 106) when it is necessary to transfer data to or from the storage device.
In fact, the FPREQ signal is canceled if the special instruction processor does not need to transfer data to or from storage, or if address calculations are not required. Similarly, what should be noted here is that if the special instruction processing unit only generates this FPREQ signal, the central processing unit will not perform any operation;
This means that it operates only after receiving the PSYNC signal. That is, the central processing unit starts its operation only in response to the FPSYNC signal generated by the special instruction processing unit, and the FPREQ signal generated by the special instruction processing unit is indicative of the operation to be performed by the central processing unit. It is only used to indicate type. As mentioned above, the instruction decoder 52 of the central processing unit
When the central processing unit receives a floating point instruction that is a special instruction, the central processing unit generates the FPATTN signal to transfer the special instruction to the special instruction processing unit. The special instruction processing unit executes the special instruction. When the special instruction processing unit requires an auxiliary operation by the central processing unit for address calculation, data transfer with a storage device, etc. when executing the special instruction, it generates an FPREQ signal indicating the type of the auxiliary operation. Also,
Generates the FPSYNC signal. The central processing unit checks the presence or absence of the FPREQ signal in response to the FPSYNC signal and outputs the FPREQ signal.
If there is a Q signal, the auxiliary operation instructed by the FPREQ signal is executed. When the special instruction processing unit completes processing of its special instruction, it generates the FPSYNC signal but does not generate the FPREQ signal. Therefore, in response to the FPSYNC signal, the central processing unit checks the presence or absence of the FPREQ signal and
Since there is no PREQ signal, program counter 51 proceeds to execute the next instruction. In this way, the central processing unit does not need to interact with the special instruction processing unit except for the following three operations. (1) Transferring special instructions to the special instruction processing device (
For example, steps 203, 204, 205) (2) calculating the addresses of the operands used to process the instruction (e.g., step 207), and (3) retrieving state from the special instruction processor (e.g., step 206). ) Therefore, from the time the FPATTN signal is generated until the special instruction processor generates the FPSYNC signal, the central processing unit performs interrupt processing and the special instruction processor in parallel with the operation of the special instruction processor. Other processing operations may be performed that may be parallel to the operation. Moreover, since the special instruction processing device of the present invention utilizes the bus interface portion of the central processing unit for data transfer to and from the storage device, the system as a whole according to the present invention bus interface circuits are reduced. Further, since the special instruction processing device of the present invention utilizes the circuit of the central processing unit as a circuit for performing specific operations such as address calculation, the present invention also includes this type of circuit as a whole system. reduced. Therefore, according to the present invention, it is possible to perform specific parallel processing between the central processing unit and the special instruction processing unit in an inexpensive system as a whole. In summary, floating point unit 13 is a processor for a special class of instructions. In this example, it happened to be a processor for floating point instructions. It is operable relatively independently of the central processing unit and controls interactions between itself and the central processing unit. That is, the central processing unit interacts with the floating point unit to the extent that it receives a combination of FPREQ and FPSYNC signals indicating that further interaction is required. It is therefore clear that it is only necessary to change the controls and some internal registers within the device 13 and to change the function that the device 13 performs. No changes are required to the central processing unit 10. In this way, it is therefore possible to change this class of instructions simply by removing some connections from the central processing unit and replacing the device 13. It will also be apparent that there are many other specific embodiments in which the general flowchart shown in FIG. 3 can be implemented. Additionally, the flowcharts and circuits depicted in the various diagrams may be modified. It is therefore the purpose of the appended claims to cover all such changes and modifications as fall within the true spirit and scope of the invention.

[Brief explanation of drawings]

FIG. 1 shows a data processing apparatus having a central processing unit and parallel units for executing separate classes of instructions. FIG. 2 is a detailed block diagram of the parallel device shown in FIG. 1 adapted to process floating point instructions. Figures 3A-G are flow diagrams illustrating the operation of the device along with the central processing unit. 4 is a schematic diagram of certain parts of the special control circuit for the apparatus of FIG. 2; FIG. 10...Central processing unit, 11...
Storage device, 12...Peripheral device, 13...
・Floating point unit, 14... Exponential calculation logic, 1
5... Fraction calculation logic, 16... Register device, 17, 18, 19, 20, 21゜22.23,
24... Bus line, 51... Program.
Counter, 52...Instruction decoder, 53...
...Control device, 55...Control circuit, 31...
...Floating point status register, 30...λ
register, 32... data storage multiplexer, 34... exponent arithmetic logic unit, 33...
...Exponent multiplexer, 43...Instruction register.

Claims (1)

[Scope of Claims] 1. A special instruction processing device connected to a central processing unit (10; Fig. 1) for processing data for special instructions in parallel with other operations of the central processing unit. , (a) Address path (17; Figure 1), data path (1
means for receiving the special command from the central processing unit; 2) for enabling said special instruction processing unit to initiate a first processing cycle for an instruction; and (c) for processing each instruction in a series of processing cycles, during each processing cycle. control means (55; second control means) which generates a control signal (FPREQ; FIG. 4) and a synchronization signal (FPSYNC; FIG. 4), and then blocks further processing until receiving another transfer signal; and (d) means for disabling control signals during the final processing cycle for each instruction (305, 304° 73; step 114 in FIG. 4; FIG. 3C). A special instruction processing device characterized by: 2. The special instruction processing device according to claim 1, wherein the special instruction processing device includes an instruction decoder, a control device, and a device (34, 42; FIG. 2) for processing special instructions; The control signal causes the special instruction processing unit and the central processing unit to interact with each other in response to a transfer signal from the central processing unit (70, 72).
, 73; steps 104-106 in FIG. 4; FIG. 3B), the controller includes devices (72, 73) responsive to the decoder to generate control and synchronization signals when further interaction is required. ; FIG. 4 step 108; FIG. 3B), and the control and synchronization signals are connected to the central processing unit. 3. The special instruction processing device according to claim 1, wherein the special instruction processing device includes a device (34, 42; FIG. 2) for processing data according to floating point arithmetic operations, The processing unit, in response to the beginning of a processing cycle in the special instruction processing unit, performs a process (steps following step 205) for going to other independent processing operations that are performed concurrently with operations in the special instruction processing unit. ; FIG. 3B).