JPS59165140A - Two-dimensional arithmetic circuit - Google Patents

Abstract

PURPOSE:To perform parallel arithmetic at a high speed on the basis of pipeline processing by providing a direct memory access mode wherein cyclic operation is performed while plural access operation timing points are regarded as one set. CONSTITUTION:An input buffer 41 is stored with data fetched from at least two memory areas. When data processing is performed, the data inputted to the circuit 41 synchronously with data fetched by direct memory access DMA is sent out to an arithmetic circuit 40 at the next timing. Further, the logical arithmetic part in the circuit 40 performs multinomial parallel progressive arithmetic among data set in plural registers, i.e. pipeline processing, and the result is stored in an output data buffer 42. This data is returned to the storage area of a general memory by using some of the access timing of an address generating circuit 43. Thus, DMA access control is performed to perform parallel arithmetic at a high speed.

Description

[Detailed Description of the Invention] (Field) The present invention relates to a two-dimensional arithmetic circuit, and particularly to a two-dimensional arithmetic circuit that can be connected to a general-purpose memory using a general-purpose bus interface in a normal data processing system, and that performs pipeline arithmetic processing internally. This paper relates to a possible two-dimensional arithmetic circuit.

(Prior art) In conventional data processing systems, normal data processing is performed in bit or word units using a general-purpose computer (hereinafter referred to as CPU).
However, for such general-purpose arithmetic processing, vector-to-vector arithmetic processing or matrix conversion is a computation process that is quite troublesome and requires processing steps and processing time. There are calculations between data matrices and data matrices to obtain various transformation matrices or inverse matrices, and general-purpose processing methods require two-dimensionally more calculation steps, and although it is possible in terms of memory capacity, Since it takes too much time, a large-sized CPU with high processing speed is required to perform such data processing.

On the other hand, there are also dedicated processors that are configured with dedicated hardware to specifically perform these processes, but the interface between these processors and the configuration memory is different from that of general-purpose ones, so special memory is also required. However, it is difficult to connect such a processor to the main memory of, for example, a minicomputer microcomputer.

(Purpose and Features) In view of the above, the object of the present invention is to have an interface that can be connected via a general-purpose memory and a general-purpose bus, and internally converts parallel operations into pipeline processing so that they can be executed at high speed. The feature of the present invention is to provide a dimensional arithmetic circuit as a means for realizing the above object, which has a high-speed arithmetic module controlled by a computer via a six bus, and a plurality of storage devices connected to the bus from the computer. When a command is issued to calculate and transfer data stored in an area.

It has a direct memory access mode that operates cyclically with multiple access operation timings as 1 cent, and selects one of the 1 cent timings to read data from one of the multiple areas of the storage device. A means for storing data in a buffer, a means for calculating the data taken in from multiple areas in this way, a means for temporarily buffering the result of the calculation, and a means for selecting one of the above timings to transfer the result of the calculation. It has one stage.

(Embodiment) Figures 1 to 10 are explanatory diagrams of one embodiment of the present invention, where Figure 1 shows the system configuration and Figure 2 shows the flow of data that is pipelined in a two-dimensional arithmetic circuit. Fig. 3 explains the meaning of two-dimensional array data, Fig. 4 explains the contents of two-dimensional operations, and Fig. 5 shows a more detailed explanation of the two-dimensional operation circuit shown in Fig. 1. detailed block diagram,
Figure 6 is a supplementary diagram to Figure 5, and is an explanatory diagram of a data access cycle that accesses general-purpose memory via a bus. Figure 7 is an example of the configuration of the address generation circuit in Figure 5. An example of the configuration of the input data buffer circuit, and FIG. 9 shows an example of the configuration of the output data buffer circuit of FIG.

FIG. 10 shows an example of the configuration of the arithmetic circuit shown in FIG. 5, respectively.

In Figure 9, 1 is a general-purpose interface pass line, 2 is a general-purpose processor, 3 is a general-purpose memory, 4 is a two-dimensional arithmetic circuit, and la, lb, and Ic are data buses and address buses, respectively, which define the buses in detail.

Control bus 40 to 44 are detailed definitions of the internal configuration of the arithmetic circuit 4, 40 is an arithmetic circuit that performs parallel operations on multi-element data, 41 is an input data buffer, 42 is an output data buffer, and 43 is an address generation circuit. , 44 is a bus control circuit.

The two-dimensional arithmetic circuit in FIG. 1 is connected to the processor 2 or the memory 3 via the bus 1 at the ink face of the general-purpose bus, and is configured to be mutually accessible.
Data of area A starting from number 0o and start address 2
Data in area B starting from number 000 is sequentially retrieved, calculations are performed on the data, and the calculation result is transferred back to memory in this case.
Suppose that a processing instruction to transfer is issued, the two-dimensional arithmetic circuit 4 receives from the processor 2 the size of each access area, each start address, the transfer destination, the size of the transfer area, the start address of the transfer destination, etc. Direct memory access that operates cyclically as a set of so-called multiple access operations, in which each data is fetched and transferred at each of a set of multiple timings, and each data is fetched and transferred cyclically and repeatedly. (DM below)
(commonly referred to as A).゛Based on Figures 5 and 6, the outline of the procedure will be explained.Based on the previous example, the input buffer 41 has at least two memories, as shown in 412 and 41b in Figure 8. Another group of data taken from the area according to the timing of another reading is stored and sequentially supplied to the arithmetic circuit 40, and the calculation results are stored in the output data buffer 42 or 42a, 42b, and transferred after waiting for the transfer timing. . The address generating circuit 43 performs all operations such as storing the start address of such an area, sequentially switching modes cyclically using DMA, and counting up the addresses for accessing the work data, and the bus control circuit 44 works in conjunction. to switch the bus transmission/reception mode.

To outline the flow of processing work of the data incorporated in this way, the data captured in the registers 41a, 41'b of the input data eight sofa 41 in synchronization with the data capture by DMA is transferred to the arithmetic circuit 40 at the secondary timing. One line buffers 401 to 404 and 405 to 40 form shift buffers in shift registers 412 to 40e and 40f to 40i, respectively, for setting a two-dimensional input data group to the logic operation unit 400 forming the internal configuration of the circuit 40.
8, and based on the set data, the logic operation unit 400 inputs the data through the shift registers 40a to 40a.
Data set in 40e and shift register 40f~
The result of multinomial parallel processing between data sent to 40i, so-called pipeline processing, is sent to 0UTDATA.
1. Or take out the output data via 0tJTDATA2 and register 4.2a of 8 sofa 42 or 42
At the same time, the stored data is returned to the storage area of the memory 3 via the data bus using one of the access timings of the address generation circuit 43 that performs the previous direct memory access. The above is an overview of the data flow, and below, to achieve this, data is fetched by specifying the address, sent to the buffer register group, and transferred to memory 3 by specifying the address, which are functionally performed simultaneously in parallel. We will provide more details on the timing and procedural control based on address specification.

As explained in FIG. 2, the two-dimensional arithmetic circuit takes in some two-dimensional array data from the memory 3 due to the cooperation between the address generation circuit 43 and the hash control circuit 44, and the data generated by the ω arithmetic processing between the data is The data in the two-dimensional array is transferred to the memory 3 again, and the two-dimensional array data referred to here is the array position in the form of two rows and two columns as shown on the input side of Figure 3 or Figure 4. It is a data matrix formed by loading data from the memory 3 into areas defined by addresses X and Y, respectively, and two-dimensional operation, at the very least, means processing for creating an output matrix by calculation between such matrices.

FIG. 6 shows the mode and control timing around the address generation circuit 43 and the bus control circuit 44. Data transfer (intake,
For example, the timing of the request (sending) is divided into four timings for MOD1 to MOD4, and according to the read/write mode signal, in the figure, MODEL and 2 are the read timings from the memory, and MODELs 3 and 4 are the timings for sending (writing) to external devices such as memory. is assigned to. Then, on the transfer control, this division is performed, and in this case, 4
It is configured so that each cycle operates with one internal instruction as one set, and when data is requested from the memory 3, read access is performed via the control bus in accordance with the bus timing, and the address of the requested data is accessed via the address bus. is specified, and the data that is read out and arrives via the data bus is immersed in the input data 8 sofa 41 for each incoming call.
The data is transferred one after another according to the internal timing to the arithmetic circuit 40.
The data in the conversion buffer 42 is stored in the memory 3 with the address to be stored during the previous write timing period. Forward. Write to memory 3.

The read area is managed by the processor 2, and the address generation circuit 43 naturally works under its control in accordance with processing instructions.

, etc. If the two-dimensional data matrix is taken from the memory 3, it is not necessary to use one row or one column of the data matrix.
There is no input data center.

The contents of the operations to be processed in the pipeline are not yet specified. The operation of the address generation circuit 43 will be explained based on FIG. 7. This circuit is a part that controls the timing and address for executing data DMA based on commands regarding the capture area and transfer area from the processor 2. There it is.

In this figure, 4 timing cycles equal 1 cent, and there are counters 41 to 43 to issue addresses in each timing cycle, and an FF 43 to specify at which timing in one set access is to be performed.
The number of access modes used in one cycle is specified by the processor 2 via the data bus by C, and the number of access modes used in one cycle is cyclically incremented by the clock CLK for sequentially advancing the cyclic modes. Sequential counters 431-43: cyclic counter 43e for instructing counter selection according to the timing of taking in address data; decoder 43d converts the value of the cyclic counter into four values here; Decoder 4 for the 1 to 4 address bus signals of 43f (game that creates the counter selection signal (■ enable signal))
3b, it consists of a multiplexer 432 etc. for putting the resulting issued address on the bus, and first there is an access processing command from the processor 2, and the number of timing modes to be used is 1. If the second data acquisition from A is data acquisition from area B, and the third is data transfer to area C, F F 4
3 Cent the three outputs of c, reset the counter 43e, and specify the timing from the address bus at the next clock timing.

The start address of the area is sent one after another from the data bus. Then, the first addresses sent in this way are respectively stored in the counter 431. 432. 433, the multiplexer 43a issues an access request address for accessing the memory by DMA to the memory one after another at a predetermined timing via the address bus, and the data bus is Each time data arrives from the memory to the input data buffer 41a or 41b, the counters 43+ and 43z are incremented by the address occupied by the received data.
Every time two transfer blocks of output data are transferred to the memory from the output data buffer 42 at a predetermined timing, here, at the third timing, the value of the counter 433 corresponding to the address that owns the transfer is changed. Pipeline data processing is a general-purpose data bus in which the data of the specified area bone is taken in sequentially in the order of the address of each area at a predetermined timing by counting up, sequentially processed, and sequentially written to the specified area. It is executed via. Although the cyclic mode has been described here with a maximum of 4 cycles, it can be expanded to 8 cycles, etc., if necessary, and in such a case, more than ternary input is required.

(Effects) As explained above, according to the present invention, by providing multiple modes of DMA access control that operate cyclically, pipe processing can be performed while interfacing between an arithmetic circuit that performs pipeline processing operations and a general-purpose bus. Since it can perform line processing, it is an extremely effective feature when there is a desire to speed up only special processing with a general-purpose processor (2), for example, when a small OCR device is desired to perform figure recognition, etc.

[Brief explanation of drawings]

1 to 10 are explanatory diagrams of one embodiment of the present invention, the first part is a system configuration, the second part is a diagram explaining the flow of data pipelined in a two-dimensional arithmetic circuit, and the first part is an explanatory diagram of an embodiment of the present invention. Figure 3 explains the meaning of two-dimensional array data.
Figure 4 explains the contents of the two-dimensional calculation, and Figure 5
The figure is a more detailed block diagram of the two-dimensional arithmetic circuit in Figure 1.
Figure 6 is a supplementary diagram to Figure 5, and is an explanatory diagram of a data access cycle that accesses general-purpose memory via a bus. Figure 7 is an example of the configuration of the address generation circuit in Figure 5. Configuration example of input data bath sofa circuit. 9 shows an example of the configuration of the output data bath sofa circuit of FIG. 5, and FIG. 10 shows an example of the configuration of the arithmetic circuit of FIG. 5. In the figure, 1 is a general-purpose interface path line, 2 is a general-purpose processor, 3 is a general-purpose memory, and 4 is a two-dimensional arithmetic circuit. Kaya, l Figure Kaya? Mouth (hJIlrd) 1m Bud 3 Figure 1-J -1-1- v Figure 4

Claims (1)

[Claims] It has a high-speed calculation module controlled by a computer via a bus, and when the computer issues a command to calculate and transfer data stored in multiple areas of a storage device connected to the bus, multiple It has a direct memory access mode that operates cyclically with one set of access operation timings, and selects one of the one set of timings to fetch data from one of the plurality of areas of the storage device and store it in the buffer. A method for storing data, a means for calculating the data taken in from a plurality of areas, a means for temporarily buffering the result of the calculation, and a means for selecting one of the timings and transferring the result of the calculation. Features a two-dimensional calculation circuit.