JPS5828338U - Direct memory access type analog input device - Google Patents
Direct memory access type analog input deviceInfo
- Publication number
- JPS5828338U JPS5828338U JP11939481U JP11939481U JPS5828338U JP S5828338 U JPS5828338 U JP S5828338U JP 11939481 U JP11939481 U JP 11939481U JP 11939481 U JP11939481 U JP 11939481U JP S5828338 U JPS5828338 U JP S5828338U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- digital data
- memory access
- reference value
- input device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は一実施例のブロック図、第２図、第３図、第４
図は一実施例の動作タイミングチャートである。
１・・・ＤＭＡ型アナログ入力装置、１０・・・ＡＤ変
換器、１１・・・基準値レジスタ、１２・・・比較回路
、１３・・・・・・セレクタ回路、１４・・・データレ
ベル設定回路、１５・・・検出回路、１６・・・転送制
御回路、１７・・・内部制御回路。Figure 1 is a block diagram of one embodiment, Figures 2, 3, and 4.
The figure is an operation timing chart of one embodiment. DESCRIPTION OF SYMBOLS 1... DMA type analog input device, 10... AD converter, 11... Reference value register, 12... Comparison circuit, 13... Selector circuit, 14... Data level setting Circuit, 15...Detection circuit, 16...Transfer control circuit, 17...Internal control circuit.
Claims (1)
するアナログ−ディジタル変換器と、あらかじめ設定さ
れる基準値Ｂを保持する記憶手段と、前記ディジタルデ
ータＡと前記基準値Ｂとの大小関係を比較し、Ａ＞Ｂで
あることを示す信号（ＧＡ倍信号、とＡ＜Ｂであること
を示す信号（ＮＧＡ信号）とを出力する比較回路と、前
記ＧＡ倍信号ＮＧＡ信号とのいずれか一方の信号により
状態設定されるデータレベル設定回路と、他の一方の信
号と前記データレベル設定回路からの信号とにより、前
記ディジタルデータＡが前記基準値Ｂより大から小に変
化するか、または、小から大に変化するタイミングを検
出する手段と、この検出手段からの信号により前記ディ
ジタルデータＡを主記憶装置へ転送制御する転送制御回
路とを具備したダイレクトメモリアクセス型アナログ入
力、装置。 −an analog-to-digital converter that converts sequentially input analog signals into digital data A, a storage means that holds a preset reference value B, and a comparison of the magnitude relationship between the digital data A and the reference value B; A comparison circuit that outputs a signal indicating that A>B (GA multiplied signal) and a signal indicating that A<B (NGA signal), and the GA multiplied signal NGA signal. Depending on the data level setting circuit whose state is set, the other signal, and the signal from the data level setting circuit, the digital data A changes from larger to smaller than the reference value B, or from smaller to larger. A direct memory access type analog input device, comprising means for detecting the timing at which the digital data A changes, and a transfer control circuit for controlling the transfer of the digital data A to a main storage device based on a signal from the detection means.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11939481U JPS5828338U (en) | 1981-08-13 | 1981-08-13 | Direct memory access type analog input device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11939481U JPS5828338U (en) | 1981-08-13 | 1981-08-13 | Direct memory access type analog input device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5828338U true JPS5828338U (en) | 1983-02-23 |
Family
ID=29913456
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11939481U Pending JPS5828338U (en) | 1981-08-13 | 1981-08-13 | Direct memory access type analog input device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5828338U (en) |
-
1981
- 1981-08-13 JP JP11939481U patent/JPS5828338U/en active Pending
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