JPS6016662B2 - Data signal interface circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention processes digitally coded input information according to a predetermined arithmetic processing procedure and controls an internal combustion engine based on the processing results. The present invention relates to a data signal interface circuit between an arithmetic processing section that performs digital arithmetic processing and an actuator control section of an engine that operates asynchronously.

Nowadays, as exhaust gas regulations become stricter, the number of electronic devices installed in vehicles increases day by day, and the control content becomes more complex, leading to expansion of circuit scale. Expansion of the circuit scale causes a rise in prices and a decrease in productivity. As a countermeasure to this problem, an internal combustion engine control device that is equipped with an arithmetic processing section that processes input information according to a predetermined arithmetic processing procedure can be considered, and by centrally controlling multiple functions in the arithmetic processing section, the circuit scale can be reduced. It is planned.

In order to control the engine based on the arithmetic processing results, it is required to convert the digital code arithmetic data into an actuator control signal such as a time width in synchronization with the movement of the engine. However, when the arithmetic processing section outputs the calculation data in synchronization with the movement of the engine, the operation of the arithmetic processing section is restricted by the movement of the engine, resulting in a decrease in processing efficiency and processing capacity. In view of the above points, the present invention has been made to solve these inconveniences and to eliminate such drawbacks.The purpose is to significantly improve the processing efficiency and processing capacity of the arithmetic processing unit with a simple configuration. In addition, the calculation processing time of the calculation processing section is shortened, and even if multiple functions are processed at once, real-time processing can be performed, and control that is perfectly suited to the internal combustion engine condition can be performed. , a data signal interface circuit that can transmit both digital code and analog voltage signals, increasing the degree of freedom in the circuit configuration of the actuator control section on the receiving side and simplifying the system configuration. It is about providing.

In order to achieve such an object, the present invention includes a first storage circuit that stores calculation data from an arithmetic processing section, and a storage circuit that operates asynchronously with the first storage circuit and re-stores the data in the first storage circuit. and a storage operation command generation circuit that generates a storage operation command for the second storage circuit when calculation data is requested, and the actuator has a time width or the like based on calculation data from the calculation processing section. an actuator control unit that generates a control signal in synchronization with the movement of the engine; a determination circuit that determines whether or not the storage operation command is present during storage operation of the first storage circuit; A storage operation delay circuit for delaying an operation command is provided.
An example will be explained.

FIG. 1 is a block diagram of the configuration of one embodiment. In FIG. 1, reference numeral 1 denotes an arithmetic processing unit that digitally processes input information from various sensors (not shown) according to a predetermined arithmetic processing procedure, and has a plurality of data output terminals la that output arithmetic data of digital codes. , a strobe terminal lb for notifying the output timing of calculation data to the outside. 2 is a first storage circuit such as a register that stores the calculation data from the calculation processing unit 1; 3 is a circuit that generates an actuator control signal such as a time width based on the calculation data from the calculation processing unit 1 in synchronization with the movement of the engine; In the actuator control section,
It includes a storage operation command generation circuit 3a that generates a storage operation command when the actuator control section 3 requests calculation data, and a second storage circuit 3b such as a register that stores the calculation data in the first storage circuit 2 again.

Reference numeral 4 denotes a determination circuit for determining whether or not a storage operation command has been generated from the storage operation command generation circuit 3b during the storage operation of the first storage circuit 2, and is constituted by a D-type flip-flop.

The data D terminal and set S terminal of the D-type flip-flop of this judgment circuit 4 are connected to the strobe terminal lb of the arithmetic processing section 1, and the timing T terminal is connected to the storage operation command generation circuit 3a. Reference numeral 5 denotes a memory operation delay circuit composed of a pulse delay circuit 5a and an AND gate 5b, which controls the memory operation of the second memory circuit 3b according to the output state of the determination circuit 4.

FIG. 2 is a timing chart for each part.

In FIG. 2, a is the strobe signal waveform generated from the strobe terminal Ib, b is the storage operation command waveform from the storage operation command generation circuit 3a, C is the output signal waveform of the judgment circuit 4, and d is the output signal waveform of the storage operation delay circuit 5. This is the output signal waveform. Next, the operation of the embodiment shown in FIG. 1 will be explained with reference to FIG. 2.

First, the arithmetic processing unit 1 digitally processes information from each type of sensor installed in the engine according to a predetermined arithmetic processing procedure, and immediately outputs the calculated data via the data output terminal la after the calculation is completed. Stroop terminal
As shown in FIG. 2a, an L-level strobe signal is output from terminal b. The arithmetic processing unit 1 repeatedly executes this operation,
Continuously outputs the latest data that matches the engine condition. 1st
The storage circuit 2 stores the calculation data on the data output terminal la when the strobe signal from the strobe terminal lb transitions from L to H level, and always stores the latest calculation data. On the other hand, each time the actuator control section 3, which operates in synchronization with the movement of the engine, requests calculation data, an H level storage operation command is generated from the storage operation command generation circuit 3a as shown in FIG. 2B.

By the way, since the arithmetic processing unit 1 and the actuator control unit 3 operate asynchronously, as shown in FIGS. There are two possible command generation timings.

The first mode is the case where the strobe signal from the strobe terminal lb and the storage operation command from the storage operation command generation circuit 3a do not overlap, as shown in operation mode 1 in FIG. This is a mode in which a memory operation command is generated when the system is stable.

In this mode, when a memory operation command is generated, the strobe signal applied to the set S terminal of the O-shaped flip-flop of the judgment circuit 4 is at H level, so the judgment circuit 4,
The D-type flip-flop remains set and maintains the H level as shown in FIG. 2C. In other words, judgment circuit 4
The D-type flip-flop is the first one when a memory operation command is generated.
This indicates that the data state in the memory circuit 2 is stable, and the memory operation command from the memory operation command generation circuit 3a has the waveform shown in FIG. 2d even after passing through the pulse delay circuit 5a and the AND gate 5b. 2 storage circuit 3b, and the L of the same signal is transmitted to the storage circuit 3b.
At the time of transition from to H level, the calculation data in the first storage circuit 2 is transferred to the second storage circuit 3b. In addition, the pulse delay circuit 5
In order to compensate for the delay in the operation of the D-type flip-flop in the judgment circuit 4 due to the storage operation command, the storage operation command is delayed by a very small amount of time, so both signals are They can be considered almost identical. In this way, operation mode 1
In this case, data is transferred immediately when a storage operation command is generated from the storage operation command generation circuit 3a. In the second mode, as shown in operation mode 2 in FIG. 2, a storage operation command is generated while a strobe signal is being generated, that is, while new calculation data is being stored in the first storage circuit 2.

In this mode, since the L-level strobe signal is being generated, the set state of the D-type flip-flop of the judgment circuit 4 is released, and the state of the data D terminal changes to the output Q at the transition timing from the L to H level of the storage operation command. Appears on the terminal.
That is, while the strobe signal is being generated, the data state in the first storage circuit 2 is interpreted as unstable, and as shown in FIG. It remains at L level until erasing, and sets a period during which transfer operations are prohibited by storage operation commands. Since the memory operation command from the memory operation command generation circuit 3a is corrected by the pulse delay circuit 5a for the operation delay of the D-type flip-flop in the judgment circuit 4 caused by the same signal, the memory operation command from the judgment circuit 4 is delayed as shown in FIG. 2d. The output of D-type flip-flop 4 is completely suppressed by AND gate 5b during the L level period. In this way, the storage operation command transmitted to the second storage circuit 3b is delayed until the data state in the first storage circuit 2 is completely stabilized, and accurate calculation results are transferred to the second storage circuit 3b. Ru. By the above-described operation, the calculation data of the digital code asynchronously outputted from the calculation processing section 1 is constantly and accurately transferred to the actuator control section 3 at any time when the operation data is requested by the actuator control section 3.

In the embodiment described above, the D-type flip-flop of the judgment circuit 4 operates using the strobe signal from the strobe terminal lb as the storage operation inhibit period of the second storage circuit 3b. Processing part 1
The scope of application of the present invention can be further expanded by generating the same signal from the strobe signal and applying it to the O-shaped flip-flop of the judgment circuit 4 instead of the strobe signal.

For example, it is also possible to convert digital code calculation data into an analog voltage and transmit it as an analog voltage.
A block diagram of the configuration of this embodiment is shown in FIG. This third
In the figure, the same numbers as in Figure 1 indicate corresponding parts,
6 is D- which converts the digital code to analog voltage.
It is an A converter, and the second storage circuit 3b is composed of a sample and hold circuit. Although the calculated data in the first storage circuit 2 is converted into an analog voltage by the DA converter 6, instantaneous conversion is impossible and requires an arbitrary conversion time. Furthermore, an arbitrary amount of time is required to charge the second memory circuit 3b with the analog voltage. Therefore, with a margin of the total time, an L-level control signal (
If the signal e) in FIG. 4 is generated from the signal terminal lc of the arithmetic processing unit 1 and this signal is connected to the set S terminal and the data D terminal of the D-type flip-flop of the judgment circuit 4, it is the same as the embodiment shown in FIG. The storage operation command from the storage operation command generation circuit 3a via the storage operation delay circuit 5 is controlled as shown in FIG. When the monostable multipipelator 3c is activated as shown in FIG. Since the analog voltage from the first memory circuit 2 is always stable, the second memory circuit 3b
The analog voltage corresponding to the calculated data within can be accurately transmitted. As is clear from the above description, according to the present invention, the arithmetic processing section converts the arithmetic data into an actuator control signal such as a time width without using a plurality of means. The processing efficiency and processing capacity of the arithmetic processing unit can be greatly increased by using a simple configuration that allows accurate data transfer between the two devices and reliably transmits data at the required time between devices that operate asynchronously. In addition, the calculation processing time of the calculation processing section is shortened, and even if multiple functions are processed at once, real-time processing can be performed, and control that is most suitable for the internal combustion engine condition can be performed. Furthermore, both digital code and analog voltage signals can be transmitted, and the degree of freedom in the circuit configuration of the actuator control section on the receiving side is increased, making it possible to simplify the system configuration. The above effect is extremely large.

[Brief explanation of the drawing]

FIG. 1 is a configuration block diagram showing one embodiment of this invention, FIG. 2 is a timing chart for each part of FIG. 1, FIG. 3 is a configuration block diagram showing another embodiment of this invention, and FIG. 4 3 is a timing chart of each part in FIG. 2...First storage circuit, 3a...Storage operation command generation circuit, 3b...Second storage circuit, 4...Judgment circuit,
5... Memory operation delay circuit. Note that the same reference numerals in the figures indicate the same or corresponding parts. Traditional 1 diagram Traditional 2 diagram Tsuna J diagram Scale 4 diagram

Claims (1)

[Claims] 1. In an internal combustion engine control device equipped with a calculation processing unit that digitally processes input information from various sensors,
a first storage circuit that stores calculation data from the calculation processing section; a second storage circuit that operates asynchronously with the first storage circuit and re-stores the data in the first storage circuit; 2. A storage operation command generation circuit that generates a storage operation command for the storage circuit; a determination circuit for determining the presence or absence of the storage operation command during the storage operation of the first storage circuit; and a storage operation delay circuit for delaying the storage operation command based on the output state of the determination circuit. A data signal interface circuit featuring: