JPS5828337U

JPS5828337U - address detection circuit

Info

Publication number: JPS5828337U
Application number: JP12203381U
Authority: JP
Inventors: 信行森脇
Original assignee: 東芝エンジニアリング株式会社
Priority date: 1981-08-18
Filing date: 1981-08-18
Publication date: 1983-02-23
Also published as: JPS6012188Y2

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図は従来装置の１例を構成を示すブロック図、第２
図は本考案の一実施例の構成を示すブロック図、第３図
は本考案の他の実施例の構成を示すブロック図である。Ａｌｏ−Ａｌ７・・・入力端子、ＳＯ１〜Ｓ０８・・・
出力端子、ＦＡ・・・全加算器、ＺＤ、　ＺＤ’・・・
オールゼロ検出回路、ＡＤ、ＡＤ′・・・デコーダ、Ａ
Ｓ・・・アドレススイッチ、２８．２９・・・４ビツト
全加算器、３０〜３５．３７〜３９・・・インバータ、
４０〜４３・・・ナントゲート、４４〜５１・・・切換
スイッチ。Figure 1 is a block diagram showing the configuration of an example of a conventional device;
The figure is a block diagram showing the structure of one embodiment of the present invention, and FIG. 3 is a block diagram showing the structure of another embodiment of the present invention. Alo-Al7...Input terminal, SO1-S08...
Output terminal, FA...Full adder, ZD, ZD'...
All zero detection circuit, AD, AD'... decoder, A
S...address switch, 28.29...4-bit full adder, 30-35.37-39...inverter,
40-43... Nantes gate, 44-51... changeover switch.

Claims

[Scope of utility model registration request]

Determine the target circuit specified by the address data in a system in which each module that is installed in parallel in the system has multiple target circuits, and the target circuits in each module are individually designated by address data. In the address detection circuit, an address setter generates data corresponding to a plurality of 1's in an arbitrary starting address by an external setting operation, and a carry signal is always given to a carry signal, and complement data given from the address setter is provided. A full adder that adds up and input address data, and an output of upper unnecessary digits excluding lower digits necessary for intra-module addressing of the output of this full adder are provided, and all of these upper unnecessary digit outputs are "0". An all-zero detection circuit that sometimes outputs a detection signal, and only when there is a detection output of this all-zero detection circuit, the lower digit output used for addressing within the module is decoded from the full adder output to each target within the module. A sadless detection circuit comprising a decoder that selectively outputs a signal based on the lower digit information at a plurality of output terminals corresponding to the circuit.