JPS5827341A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5827341A
JPS5827341A JP12653181A JP12653181A JPS5827341A JP S5827341 A JPS5827341 A JP S5827341A JP 12653181 A JP12653181 A JP 12653181A JP 12653181 A JP12653181 A JP 12653181A JP S5827341 A JPS5827341 A JP S5827341A
Authority
JP
Japan
Prior art keywords
film
region
area
mask
photoresist
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12653181A
Other languages
Japanese (ja)
Other versions
JPH038105B2 (en
Inventor
Tadashi Kirisako
桐迫 正
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP12653181A priority Critical patent/JPS5827341A/en
Publication of JPS5827341A publication Critical patent/JPS5827341A/en
Publication of JPH038105B2 publication Critical patent/JPH038105B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76221Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO with a plurality of successive local oxidation steps

Abstract

PURPOSE:To improve the characteristics of a semiconductor device by removing an Si3N4 film on an interelement isolating zone region with a thermal H3PO4 without roughing the surface of a lower Si substrate. CONSTITUTION:A dioxidized silicon film 22, an antioxidative film 23 and a dioxidized silicon film 24 of the prescribed pattern are respectively laminated on an interelement isolating zone forming region C and an element forming region A on a semiconductor substrate 21. Then, a photoresist film 25 is formed, a window is opened at the film 25 on the region C, and with the film as a mask the film 24 on the region C is removed. Then, nitrided silicon films 23 on the regions C and A as masks the first field oxidation 26 is performed. Then, a photoresist film 27 opened with a window only on the region C is formed, and with the film as a mask the film 23 on the region C is removed, and an isolating band forming impurity is introduced to the region C. Thereafter, the second field oxidized film 28 is formed.

Description

【発明の詳細な説明】 本発明は半導体装置、特にパイボーフ製半導体装置O製
造方法の改良に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to an improvement in a method for manufacturing a Paibov semiconductor device O.

従来よルパイポーフ型トランジスタのベース・コレクタ
接合容量を減少させ、トツンVスタのスイッチング特性
を向上させるためにベース領域Oa8を分厚い二酸化シ
リコン(S:LOj )で囲つ喪構造の半導体装置が提
供されている。
In order to reduce the base-collector junction capacitance of the Rupaipov transistor and improve the switching characteristics of the Totsun V-star, a semiconductor device having a mourning structure in which the base region Oa8 is surrounded by thick silicon dioxide (S:LOj) has been conventionally provided. There is.

第1図にこのような構造の半導体装置の断面図を示す・
図においてlはPWIO61基板、2はN型の塩込み層
、8はP型不純物を導入し九票子関分離帯層、4はN型
の81工ピタキシヤμ層、6拡フイーμド酸化膜、6は
Pgのベース領域、7はN!lのエミッタ領域を示す。
Figure 1 shows a cross-sectional view of a semiconductor device with such a structure.
In the figure, l is a PWIO61 substrate, 2 is an N-type salt layer, 8 is a nine-layer separator layer into which P-type impurities are introduced, 4 is an N-type 81-layer pitaxeum layer, 6 is an expanded feed μ-doped oxide film, 6 is the base area of Pg, 7 is N! The emitter region of l is shown.

従来このような半導体装置をI!#する揚台1g2図よ
シJI811ilまでに示すような工程がとられている
Conventionally, this kind of semiconductor device is I! The steps shown in Figure 1g2 and up to JI811il are taken.

すなわちまずj1g2図に示すように#J述した埋込み
層2を形成した81基板1上に気相成長法(CVD法)
tたは熱酸化法にょシ5iOslllllを1000A
C)厚さで形成し、次にCVD法にょ多窓化シリコン(
Si3N4)lll12を1sooAo厚サテ形成する
。その後フォトリソグラフィ法を用いて前記Sin、I
ll 11およびSi、N4膜12のうちで少くともS
i、N4膜12を所定のパターンに形成する。
That is, first, as shown in Figure j1g2, a vapor phase growth method (CVD method) is applied to the 81 substrate 1 on which the buried layer 2 described above is formed.
Or thermal oxidation method 5iOsllllll to 1000A
C) Thickness is formed, and then multi-windowed silicon is formed by CVD method (
Si3N4)llll12 is formed to a thickness of 1 sooAo. After that, using a photolithography method, the above-mentioned Sin, I
ll 11 and Si, at least S of the N4 film 12
i. The N4 film 12 is formed into a predetermined pattern.

七〇gIL第8図に示すようにSi、N4.$112を
マスクとして熱酸化法によルフィールド酸化11418
を約4oooAo厚さで形成する。
70gIL As shown in Figure 8, Si, N4. Lufield oxidation 11418 by thermal oxidation method using $112 as a mask
is formed to a thickness of approximately 4oooAo.

そのwk314図に示すように所定のパターンにフオ)
しs/;L)1114を被着し、該7オトレレスト膜を
マスクとして素子間分離帯形成予定領域上の5i1N4
77412 @プラズマエツチング法によル除去する。
The wk314 pattern as shown in the figure)
5i1N4 on the region where the isolation zone is to be formed using the 7 Otorerest film as a mask.
77412 @Remove by plasma etching method.

その後第5WAに示すように該フォトレジスト族14を
マスクとして硼*(B”)イオンをJ15 KeV5X
10”シCがの条件でイオン注入して素子間分離帯領域
を形成する。
Thereafter, as shown in the 5th WA, using the photoresist group 14 as a mask, borium * (B") ions are applied to J15 KeV5X.
Ion implantation is performed under the condition of 10''C to form an isolation band region between elements.

そOvk第6図に示すようにフォトレジスト11111
4を除去したのち、紫子間分離II領域C上にJI2の
フィールド酸化[15を700OAの厚さで分厚く形成
する@ このときはじめの第1のフィールド酸化膜18は第2の
フィールド酸化11115の形成のときに分厚くなシ約
52oofの厚さとなる。
Photoresist 11111 as shown in Figure 6
After removing 4, a field oxide film 15 of JI2 is formed thickly to a thickness of 700 OA on the violet isolation II region C. When formed, the thick shell is approximately 52oof thick.

その後基板を熱処理して、イオン注入された領域を活性
化し、素子間分離帯領域16を形成する。
Thereafter, the substrate is heat-treated to activate the ion-implanted regions and form isolation band regions 16 between elements.

次に第7図に示すように該基板を熱シん酸(Hgpo4
)によりて処理して、116図に示した素子形成領域上
(ベース領域上)の51sN4Ill 2 Aをい、そ
の後露出したベース領域上に51o1膜17を熱酸化に
よって約100OAの厚さに形成する。
Next, as shown in FIG. 7, the substrate was heated with hot phosphoric acid (Hgpo4
) to remove 51sN4Ill 2 A on the element formation region (on the base region) shown in Figure 116, and then form a 51o1 film 17 to a thickness of about 100OA on the exposed base region by thermal oxidation. .

1118を形成してから、該:y#)しN7.)311
18をマスクとして、醐素原子(B+)をイオン注入し
てから該しシス)1118を除去して熱処理して前述し
良路1図のペース領域6を形成する。その後見にシん(
P)tた砒素(A8)等OIJ型不純物原子をイオン注
入してlIr述したエミッタ領域7を形成してトランジ
スタを形成していた。
1118, then:y#) and N7. )311
Using 18 as a mask, phosphorus atoms (B+) are ion-implanted, and then cis) 1118 is removed and heat treated to form the pace region 6 shown in FIG. 1, described above. I'll see you later (
A transistor was formed by ion-implanting OIJ type impurity atoms such as arsenic (A8) to form the emitter region 7 described above.

しかしこのよりな方法であると第4図の工程で示したよ
うにフォトレジスト膜14を愈開きしてからプラズマエ
ツチング法で素子間分離帯領域上の519N4@ 12
を除去する際に下地のSiO,Jllllがエツチング
され、下部の81工ビタキシヤμ層4が露出することが
ある。とζろが該S1が一旦露出すると該S1のエツチ
ングされるjI度が5int膜やSilN4gに比べて
這いために急激にエツチングされ、Slの表面が荒れた
りあるいは溝を生じたシこのエツチングされた部分で段
差を生じる等欠点を生じる。
However, in this better method, the photoresist film 14 is opened as shown in the process of FIG.
When removing the layer 4, the underlying SiO and Jllll may be etched and the underlying 81-layer bitaxy μ layer 4 may be exposed. Once the S1 is exposed, the S1 is etched more rapidly than the 5-inch film or SilN4g, and the surface of the S1 becomes rough or grooves are formed. This causes defects such as unevenness in some parts.

また一方811N41112を熱a、po4のエツチン
グ液で除去するためには、他の領域の5ilN4膜12
Aを残すために何らかの保護膜が必要とな多工程が煩雑
となる欠点がある。
On the other hand, in order to remove 811N41112 with heat a and po4 etching solution, it is necessary to remove the 5ilN4 film 12 in other areas.
There is a drawback that some kind of protective film is required to leave A, and the multiple steps are complicated.

本発明は上述した欠点を除き、熱aapo4によシ票子
間分離帯領域上の5j−IN4 Ill 2を下部のS
1基板面を荒らすことなく除去し、特性の良好な半導体
装置を得ることを目的とするものである〇かかる目的を
達成するための半導体装置の製造方法は、半導体基板上
の素子間分離帯形成予定領域上、及び素子形成予定領域
上に所定パターンの二酸化シリコン膜、耐酸化性膜およ
び二酸化シリコン族を積層形成する工程、該基板上にフ
ォトレジスト展形成後、素子間分離帯形成予定領域上の
フォトレジスト族を鉱開きする工程、該値開きし九フオ
トレジヌト展をマスクとして素子量分j111形成予定
領域上の二酸化シリコン族を除去する工程、!ilI紀
素子閲分S帯形成予定領域上および素子形成予定領域上
の鼠化シリコン膜をマスクとしてfs1図目のフィール
ド酸化上行う工程、素子間分離帯形成予定領域のみ窓開
きしたフオ)vy7.)膜を形成する工程、該フォトレ
ジスト族をマスクとして素子聞分Jll帯形成yt!領
域上の鷹化Vリコン膜を除去する工程、該素子間分離帯
形成予定領域に分離帯形成用不純物を導入する工程、そ
の後第2のフィールド酸化を行い、形成した素子間分離
帯領域上に分厚い二酸化シリコン膜を形成する工程を含
むことを特徴とするものでおる。
The present invention eliminates the above-mentioned drawbacks, and provides thermal aapo4 to connect the 5j-IN4 Ill 2 on the inter-separation zone area to the lower S
The purpose is to obtain a semiconductor device with good characteristics by removing it without disturbing the surface of the substrate. A method for manufacturing a semiconductor device to achieve this purpose is to form an isolation zone between elements on a semiconductor substrate. A step of laminating a silicon dioxide film, an oxidation-resistant film, and a silicon dioxide group in a predetermined pattern on the planned area and the area where the element is to be formed, and after forming a photoresist on the substrate, on the area where the isolation zone between the elements is to be formed. A step of removing the silicon dioxide group on the region where the element amount j111 is to be formed using the nine photoresist groups as a mask. The step of performing field oxidation on the field oxidation shown in Fig. fs1 using the silicon nitride film on the S-band formation area of the ilI element as a mask and on the element formation area as a mask. ) A step of forming a film, using the photoresist group as a mask to form a Jll band between the elements yt! A step of removing the vulcanized V recon film on the area, a step of introducing an impurity for forming an isolation band into the area where the isolation band is to be formed, and then a second field oxidation is performed on the formed isolation band area. This method is characterized by including a step of forming a thick silicon dioxide film.

以下図面を用いて本発明の−*施偶につき詳細に説明す
る。
The features of the present invention will be explained in detail below with reference to the drawings.

第9図よシ第18図までが本発明の半導体装置の製造方
法の一実施例の工程を示す断面図である◎まずN9図に
示すように81基板(Vリコンエピタキシャμ層)21
の素子形成予定領域A上および素子間分離帯形成予定領
域C上に所定パターンのSing II 22をxoo
oL sl、N4II!sをt6ooJ、5101膜2
4をxooo、Mの厚さで三層構造に積層して形成する
。このようにSj−0gm122、Si、N41112
g、510zl1424を三層構造に所定のパターンで
形成するには該S1基板上にS10!展22.511N
411128.810g膜24tCVDlで連続して成
長後板基板上に7オトレジスト膜を脆布する。
Figures 9 through 18 are cross-sectional views showing the steps of an embodiment of the method for manufacturing a semiconductor device of the present invention. First, as shown in Figure N9, an 81 substrate (V recon epitaxial μ layer) 21
A predetermined pattern of Sing II 22 is placed on the element formation area A and the element isolation zone formation area C.
oL sl, N4II! s t6ooJ, 5101 membrane 2
4 is laminated into a three-layer structure with a thickness of xooo, M. In this way Sj-0gm122, Si, N41112
g, 510zl1424 in a predetermined pattern in a three-layer structure, S10! Exhibition 22.511N
411128. After successive growth of 810 g film with 24 t CVDl, 7 photoresist films are brittle on the plate substrate.

その後該フォトレジスト膜を所定パターンに7オトリソ
グラフイ法によって成形後、該バターニングされたフォ
トレジスト族をマスクとして下部のSLOg展、Si8
N4膜、SlogMf:プラズマエツチング法で所定の
パターンにエツチングする。
After that, the photoresist film is formed into a predetermined pattern by the 7 otolithography method, and the lower SLOg is exposed using the patterned photoresist as a mask.
N4 film, SlogMf: Etched into a predetermined pattern by plasma etching method.

その後JIIO図に示すように駅基板上にフオとレジス
ト膜を慾布後索子間分離帯形成予定領域C上を窓鈍きし
、弗化水素酸(HF)等を用いて素子間分離帯形成予定
領域CJ:の最上層の8102膜24をエツチングして
除去したのち、フォトレジ−スト1125をもレジスト
除去液で除去する。
After that, as shown in the JIIO diagram, after spreading a resist film on the station board, the area C where the inter-chord isolation zone is to be formed is dulled, and the inter-element isolation zone is formed using hydrofluoric acid (HF) or the like. After etching and removing the uppermost 8102 film 24 in the formation area CJ:, the photoresist 1125 is also removed using a resist removal solution.

その後1811図に示すように素子間分離帯形成予定領
域C上に形成された三層構造の810xlt22および
Si、N4M2Bと素子形成予定領域A上に形成されて
いる510gN22.81slL4m2B、8102膜
24をマスクとして第1層のフィールド酸化膜26を形
成する。
Thereafter, as shown in Fig. 1811, the three-layer structure of 810xlt22, Si, N4M2B formed on the area C where the isolation zone is to be formed, and the 510gN22.81slL4m2B and 8102 film 24 formed on the area A where the element formation is planned are masked. As a first layer, a field oxide film 26 is formed.

その後該フィールド酸化膜26と素子形成予定g4植A
上の510g展24をマスクとして熱EsPQ4を用い
て素子量分*帯形成予定領域C上のSis N4I14
2Bをエツチングしてから更にHB’等を用いてその下
の510g1l122をもエツチングして除去しS1基
板の表面を露出させる。
After that, the field oxide film 26 and device formation plan G4 Plant A
Sis N4I14 on the element amount*band formation area C using the heat EsPQ4 using the 510g layer 24 above as a mask.
After etching 2B, the underlying 510g11122 is also etched and removed using HB' to expose the surface of the S1 substrate.

このようにすればフィールド酸化1126および素子形
成予定領域上の5inz膜24がマスクとなってこの部
分は熱HaPO4に侵されずしたがって素子間分離帯形
成予定領域上のSi、N4膜28のみが所定の巾寸法で
エツチングされて除去できる。
In this way, the field oxidation 1126 and the 5inz film 24 on the area where the element is to be formed will act as a mask, and this part will not be attacked by the heat HaPO4, so only the Si and N4 films 28 on the area where the isolation zone will be formed will be in the designated area. It can be etched and removed with a width of .

その後HF等を用いて5iaN4膜下の8inz膜22
をもエツチングする。このようにすれば素子間分離帯形
成予定領域の811&板表面が表面を損傷されない状態
で算出できることになる。
After that, using HF etc., the 8inz film 22 under the 5iaN4 film is
Also etched. In this way, calculations can be made without damaging the surface of the 811 & plate surface in the region where the isolation band is to be formed.

その後第12図に示すごとくフォトリソグフフイ技術を
用いて素子間分離帯領域上のみ窓開きされたフォトレジ
スト1127を基板上に形成し、露出された素子間分離
帯形成予定領域に票(B+)イオンを矢印のように80
 KeV、5X10”67cm”のドーズ量でイオン注
入する。
Thereafter, as shown in FIG. 12, a photoresist 1127 is formed on the substrate using a photolithographic technique with a window opening only on the isolation zone area, and a mark (B+) is placed on the exposed area where the isolation zone is to be formed. 80 ions like the arrow
Ion implantation is carried out at a dose of KeV of 5×10"67 cm".

そのWk$18図に示すごとく第2のフィールド酸化y
428を約yooofの厚さでイオン注入された素子間
分離帯形成予定領域上および第1回目のフィールド酸化
された領域に形成する。
As shown in the Wk$18 figure, the second field oxidation
428 is formed to a thickness of about yooof on the ion-implanted region where the isolation band is to be formed and on the region subjected to the first field oxidation.

この時第1回目のフィールド酸化された領域上には第2
回目にフィールド酸化された寸法と合せて82GOAの
厚さのフィールド酸化膜が形成されたことになる〇 そOvk該基板基板処理してイオン注入された硼素イオ
ンを活性化して素子間分離帯領域29を形成する◎ その後素子形成予定領域上の5101M22.5j−s
N41128、Sing gもそれぞれHFおよび熱H
,PO4を用いエツチングして除去したのぢ、選択的に
硼素イオンをイオン注入して第1図6に示すように素子
形成領域にペース領域を形成する。
At this time, there is a second field oxidized area on the first field oxidized area.
This means that a field oxide film with a thickness of 82 GOA is formed, including the dimensions of the first field oxidation. ◎ Then, 5101M22.5j-s on the area where the element is to be formed.
N41128, Sing g also HF and heat H
, PO4 and then selectively implanting boron ions to form a space region in the element formation region as shown in FIG. 1.

以上述べたように本発明の方法によれば素子間分離帯領
域O81基板表面が異常にエツチングされることがない
ので、この部分に溝ができたシ段差を生じたシすること
がなくなシ高信頼度の半導体装置が高歩留で得られる利
点を生じる。
As described above, according to the method of the present invention, the substrate surface of the inter-element isolation zone O81 is not etched abnormally, so there is no need to form grooves or steps in this area. This brings about the advantage that a highly reliable semiconductor device can be obtained at a high yield.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はバイボーフ型半導体装置の断面図、第2図よシ
第8図までは従来の半導体装置の製造方法の工程を示す
断面図、第9図よシ第18図まで紘本発明の半導体装置
の擬造方法の一笑施例を示す工程の断面図である。 図において1はS1基板、2は堀込み層、Li2゜29
は索子間分離帯層、4,21はN型エピタキシャμ層、
5はフィールド酸化膜、6はベース領域。 7はエミッタ領域、11.17.22.24はS10g
膜、12.12A、2BはSj−sN4M、18.26
は第1のフィールド峡化膜、14.1&、25.27は
ニアt)L/Nスを展、15.28は第2のフィールド
峡化展、Aは素子形成予定領域、Cは素子間分離帯形成
予定領域、B+は硼素イオンを示す。 第1図 第2図 1り 第3図 第4図 第 5 凶 第6図 第7図
FIG. 1 is a sectional view of a Bybov type semiconductor device, FIGS. 2 to 8 are sectional views showing the steps of a conventional semiconductor device manufacturing method, and FIGS. FIG. 3 is a cross-sectional view of a process showing an example of a method for fabricating a device. In the figure, 1 is the S1 substrate, 2 is the digging layer, Li2゜29
4, 21 are N-type epitaxial μ layers,
5 is a field oxide film, and 6 is a base region. 7 is the emitter area, 11.17.22.24 is S10g
Membrane, 12.12A, 2B is Sj-sN4M, 18.26
is the first field isthmus film, 14.1&, 25.27 is the near t) L/N space, 15.28 is the second field isthmus film, A is the area where the element is to be formed, and C is the area between the elements. In the region where the separation zone is to be formed, B+ indicates boron ions. Figure 1 Figure 2 Figure 1 Li Figure 3 Figure 4 Figure 5 Figure 6 Figure 7

Claims (1)

【特許請求の範囲】[Claims] 半導体基板上の素子間分離帯形成予定領域上および素子
形成予定領域上に所定パターンの二酸化シリコン膜と耐
酸化性膜および二酸化シリコン族を積層形成する工程、
該基板上に7オトレジスト膜形成後、素子間分離帯形成
予定領域上のフォトレジスト族を窓開きする工程、該W
1開きしたフォトレジスト族をマスクとして素子間分離
帯形成予定領域上の二酸化シリコン族を除去する工程、
前記素子間分離帯形成予定領域上および素子形成予定領
域上の電化シリコン族をマスクとして11111目のフ
ィーμド酸化を行う工程、素子間分離帯形成予定領域の
み意Mきしたフォトレジスト膜を形成する工程、該フォ
トレジスト膜をマスクとして素子間分離帯形成予定領域
上の電化Fリコン膜を除去する工程、皺素子関分離帯形
成予定領域嬉分離帯形成用予義物を導入する工程、その
後ls2のフィーμド酸化を行い形成した菓子聞分JI
IIF領域上に分厚い二酸化シリコン族を形成する工程
を含むことを特徴とする半導体装置の製造方法0
a step of laminating a silicon dioxide film, an oxidation-resistant film, and a silicon dioxide group in a predetermined pattern on a region where an isolation band is to be formed and a region where an element is to be formed on a semiconductor substrate;
After forming the photoresist film on the substrate, opening the photoresist layer on the region where the isolation zone is to be formed;
1. Using the open photoresist group as a mask, removing the silicon dioxide group on the region where the isolation band is to be formed;
A step of performing 11111th feed μ oxidation using the electrified silicon group on the area where the isolation band is to be formed and the area where the element is to be formed as a mask, and forming a photoresist film only in the area where the isolation band is to be formed. a step of using the photoresist film as a mask to remove the electrified F silicon film on the region where the isolation zone between the elements is to be formed, a step of introducing a predetermined material for forming the separation zone into the region where the wrinkled element isolation zone is to be formed; Confectionery batch JI formed by ls2 feed μ oxidation
Manufacturing method 0 of a semiconductor device characterized by including a step of forming a thick silicon dioxide group on an IIF region
JP12653181A 1981-08-11 1981-08-11 Manufacture of semiconductor device Granted JPS5827341A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12653181A JPS5827341A (en) 1981-08-11 1981-08-11 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12653181A JPS5827341A (en) 1981-08-11 1981-08-11 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5827341A true JPS5827341A (en) 1983-02-18
JPH038105B2 JPH038105B2 (en) 1991-02-05

Family

ID=14937503

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12653181A Granted JPS5827341A (en) 1981-08-11 1981-08-11 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5827341A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5780352A (en) * 1995-10-23 1998-07-14 Motorola, Inc. Method of forming an isolation oxide for silicon-on-insulator technology

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51146186A (en) * 1975-06-11 1976-12-15 Hitachi Ltd Diode device fabrication method
JPS55157258A (en) * 1979-05-25 1980-12-06 Raytheon Co Semiconductor device and method of fabricating same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51146186A (en) * 1975-06-11 1976-12-15 Hitachi Ltd Diode device fabrication method
JPS55157258A (en) * 1979-05-25 1980-12-06 Raytheon Co Semiconductor device and method of fabricating same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5780352A (en) * 1995-10-23 1998-07-14 Motorola, Inc. Method of forming an isolation oxide for silicon-on-insulator technology

Also Published As

Publication number Publication date
JPH038105B2 (en) 1991-02-05

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