JPS5826266U - double scanning converter - Google Patents
double scanning converterInfo
- Publication number
- JPS5826266U JPS5826266U JP12020681U JP12020681U JPS5826266U JP S5826266 U JPS5826266 U JP S5826266U JP 12020681 U JP12020681 U JP 12020681U JP 12020681 U JP12020681 U JP 12020681U JP S5826266 U JPS5826266 U JP S5826266U
- Authority
- JP
- Japan
- Prior art keywords
- clock
- double scanning
- video signal
- scanning converter
- frequency
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Color Television Systems (AREA)
- Television Systems (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は通常走査によるテレビ画面と倍走査によるテレ
ビ画面とを示す図、第２図は倍走査受像機の回路系統図
、第３図は第２図の倍走査変換装置の従来より提案され
ている回路の一例を示す回路系統図、第４図は第３図の
各部の出力波形図、−第５図は本考案の実施例を示す回
路系統図、第６図は第５図の各部の出力波形図、第７図
は２画面倍走査による画面を示す図、第８図は２画面倍
走査を行う場合の実施例を示す回路系統図、第９図は第
８図の要部の出力波形図である。
なお図面に用いた符号において、７・・・倍走査変換装
置、ＤＬ−Ａ、 ＤＬ−Ｂ・・・ＩＨ遅延装置、３０・
・・クロック発振器、３１・・４分周器である。Fig. 1 is a diagram showing a normal scanning TV screen and a double scanning TV screen, Fig. 2 is a circuit diagram of a double scanning receiver, and Fig. 3 is a conventionally proposed double scanning conversion device of Fig. 2. Figure 4 is a circuit diagram showing an example of the circuit shown in Figure 3, - Figure 5 is a circuit diagram showing an embodiment of the present invention, Figure 6 is a diagram showing each part of Figure 5. Fig. 7 is a diagram showing a screen obtained by double-screen scanning, Fig. 8 is a circuit system diagram showing an embodiment in which double-screen scanning is performed, and Fig. 9 shows the main parts of Fig. 8. It is an output waveform diagram. In addition, in the codes used in the drawings, 7...double scanning conversion device, DL-A, DL-B...IH delay device, 30.
...Clock oscillator, 31...4 frequency divider.
Claims (1)
に加えるように成し、上記映像信号が加えられている遅
延装置を所定周波数の第１のクロックで駆動すると共に
上記映像信号が加えられていない遅延装置を上記第１の
クロック周波数の整数倍の周波数を有する第２のクロッ
クで駆動し、この第２のクロックで読み出された信号を
出力端子に加えるようにした倍走査変換装置。A video signal is alternately applied to the first and second IH delay devices for each IH, and the delay device to which the video signal is applied is driven by a first clock having a predetermined frequency, and the video signal is Double scanning conversion in which the delay device that is not added is driven by a second clock having a frequency that is an integral multiple of the first clock frequency, and the signal read out by this second clock is applied to the output terminal. Device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12020681U JPS5826266U (en) | 1981-08-13 | 1981-08-13 | double scanning converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12020681U JPS5826266U (en) | 1981-08-13 | 1981-08-13 | double scanning converter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5826266U true JPS5826266U (en) | 1983-02-19 |
Family
ID=29914232
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12020681U Pending JPS5826266U (en) | 1981-08-13 | 1981-08-13 | double scanning converter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5826266U (en) |
-
1981
- 1981-08-13 JP JP12020681U patent/JPS5826266U/en active Pending
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