JPS5826192B2 - Printed wiring board manufacturing method - Google Patents

Printed wiring board manufacturing method

Info

Publication number
JPS5826192B2
JPS5826192B2 JP55173563A JP17356380A JPS5826192B2 JP S5826192 B2 JPS5826192 B2 JP S5826192B2 JP 55173563 A JP55173563 A JP 55173563A JP 17356380 A JP17356380 A JP 17356380A JP S5826192 B2 JPS5826192 B2 JP S5826192B2
Authority
JP
Japan
Prior art keywords
insulating substrate
chemical plating
adhesive layer
printed wiring
chemical
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55173563A
Other languages
Japanese (ja)
Other versions
JPS5796591A (en
Inventor
成光 石井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP55173563A priority Critical patent/JPS5826192B2/en
Publication of JPS5796591A publication Critical patent/JPS5796591A/en
Publication of JPS5826192B2 publication Critical patent/JPS5826192B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)

Description

【発明の詳細な説明】 本発明は印刷配線板の製造方法に関し、詳しくはフルア
ディティブ法による印刷配線板の製造方法の改良に係る
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a printed wiring board, and more particularly to an improvement in the method for manufacturing a printed wiring board using a fully additive method.

フルアディティブ法による印刷配線板の製造方法は一般
に絶縁基板の表面にアクリルニトリルゴム、エポキシ樹
脂及びフェノール系樹脂を主成分とする化学メッキ用接
着剤層を被覆した後、該接着剤層の回路パターン形成予
定部以外をメツキレシストでマスキングし、ひきつづき
親水化処理、活性化処理を施し、更に化学メッキ処理を
施してメツキレシストから露出する接着剤層に化学メッ
キ膜を析出させ回路パターンを形成する方法が行なわれ
ている。
Generally, the fully additive method for manufacturing printed wiring boards involves coating the surface of an insulating substrate with a chemical plating adhesive layer containing acrylonitrile rubber, epoxy resin, and phenolic resin as main components, and then applying a circuit pattern to the adhesive layer. The method used is to mask the area other than the area to be formed with a mesh resist, then perform a hydrophilic treatment and an activation treatment, and further perform a chemical plating treatment to deposit a chemical plating film on the adhesive layer exposed from the mesh resist to form a circuit pattern. It is.

しかしながら、かかる方法ではメツキレシストをマスク
として選択的に化学メッキ膜を析出させるため、化学メ
ッキ処理工程中においてメツキレシストが化学メッキ浴
に悪影響を与えたり、メツキレシスト表面に化学メッキ
が異常析出して所定の回路パターン形成に支障をきたし
たりするなどの欠点があった。
However, in this method, a chemical plating film is selectively deposited using the metskily resist as a mask, so that the metskily resist may have an adverse effect on the chemical plating bath during the chemical plating process, or the chemical plating may be abnormally deposited on the surface of the metskily resist, causing damage to the predetermined circuit. This method has drawbacks such as interfering with pattern formation.

特に、メツキレシストを化学メッキ処理後に除去する場
合はそれほど回路パターン形成に支障とならないが、メ
ツキレシストを永久マスクとして使用する場合、回路パ
ターン間のショートを招く。
In particular, when the plating resist is removed after chemical plating, it does not interfere with circuit pattern formation so much, but when the plating resist is used as a permanent mask, short circuits occur between circuit patterns.

これに対し、本発明者は上記欠点を克服すべく鋭意研究
を重ねた結果、絶縁基板表面に化学メッキ用接着剤層を
被覆し、この基板の形成すべき回路パターン領域に凹部
を設け、親水化、活性化処理し、更に化学メッキ処理を
施した後、前記絶縁基板の表面を機械的に研摩して該基
板の凸部に析出した化学メッキ膜を除去することによっ
て、メツキレシストを伺んら用いることなく凹部に残存
した化学メッキ膜により回路パターンを形成でき、ひい
ては化学メッキ浴の汚染を防止できるとともに回路パタ
ーン間のショートのない高信頼性の印刷配線板を製造し
得る方法を見い出した。
In order to overcome this drawback, the inventors of the present invention have conducted extensive research to overcome the above-mentioned drawbacks, and as a result, they coated the surface of an insulating substrate with an adhesive layer for chemical plating, provided recesses in the area of the circuit pattern to be formed on this substrate, and created a hydrophilic substrate. After performing the chemical plating treatment and the chemical plating treatment, the surface of the insulating substrate is mechanically polished to remove the chemical plating film deposited on the convex portions of the substrate. We have discovered a method that allows circuit patterns to be formed using the chemical plating film that remains in the recesses without using it, thereby preventing contamination of the chemical plating bath, and producing a highly reliable printed wiring board without short circuits between the circuit patterns.

すなわち、本発明は絶縁基板の表面にゴム粒子が均一分
散した熱硬化性樹脂を主成分とした化学メッキ用接着剤
層を形成する工程と、この絶縁基板の形成すべき回路パ
ターン領域に所望深さの凹部を設ける工程と、前記絶縁
基板の接着剤層を親水化、活性化処理した後、化学メッ
キ処理を施す工程と、前記絶縁基板表面を機械的に研摩
して該基板の凸部に析出した化学メッキ膜を除去する工
程とを順次行なうことを特徴とするものである。
That is, the present invention includes a step of forming an adhesive layer for chemical plating mainly composed of a thermosetting resin in which rubber particles are uniformly dispersed on the surface of an insulating substrate, and a process of forming a desired depth in a circuit pattern area of the insulating substrate to be formed. a step of providing a concave portion of the insulating substrate, a step of performing a chemical plating treatment after hydrophilizing and activating the adhesive layer of the insulating substrate, and a step of mechanically polishing the surface of the insulating substrate to form a convex portion of the substrate. This method is characterized by sequentially performing the step of removing the deposited chemical plating film.

本発明に用いる絶縁基板としては、例えば紙−フェノー
ル樹脂積層体、紙−エポキシ樹脂積層板、ガラス繊維入
りフェノール樹脂積層板、ガラス繊維入りエポキシ樹脂
積層板、フェノール樹脂積層板、エポキシ樹脂積層板、
ポリエステル樹脂積層板等を挙げることができる。
Examples of insulating substrates used in the present invention include paper-phenolic resin laminates, paper-epoxy resin laminates, glass fiber-containing phenolic resin laminates, glass fiber-containing epoxy resin laminates, phenolic resin laminates, epoxy resin laminates,
Examples include polyester resin laminates.

本発明における化学メッキ用接着剤層は化学メッキ膜を
絶縁基板に対して強固に付着させる下地としての役目を
する。
The adhesive layer for chemical plating in the present invention serves as a base for firmly adhering a chemical plating film to an insulating substrate.

かかる接着剤の一構成成分であるゴム粒子としては、例
えば天然ゴム、或いはアクリロニトリルゴム、ブタジェ
ンゴム、アクリロニトリル−ブタジェンゴムなどの合成
ゴムから選ばれる1種又は2種以上の混合物等を挙げる
ことができる。
Examples of the rubber particles that are a component of such an adhesive include one or a mixture of two or more selected from natural rubber and synthetic rubbers such as acrylonitrile rubber, butadiene rubber, and acrylonitrile-butadiene rubber.

但し、このゴム粒子は親水化処理により接着剤層への粗
面化に寄与する動点から、接着剤層中に偏在せず、均一
に分散していることが必要である。
However, since the rubber particles contribute to roughening of the surface of the adhesive layer by the hydrophilic treatment, it is necessary that the rubber particles are not unevenly distributed in the adhesive layer and are uniformly dispersed.

また接着剤の他の構成成分である熱硬化性樹脂としては
、例えばノボラック型フェノール樹脂、レゾール型フェ
ノール樹脂、キシレン樹脂などのフェノール系樹脂、或
いはエピクロルヒドリンとビスフェノールとの重縮合体
、J]Wfiエポキシ樹脂、エポキシ化ポリブタジェン
樹脂などのエポキシ系樹脂から選ばれる1種又は2種以
上の混合物を挙げることができる。
Examples of thermosetting resins that are other constituents of the adhesive include phenolic resins such as novolak phenolic resins, resol phenolic resins, and xylene resins, or polycondensates of epichlorohydrin and bisphenol, and J]Wfi epoxy. Examples include one type or a mixture of two or more types selected from resins and epoxy resins such as epoxidized polybutadiene resins.

特に、熱硬化性樹脂としてフェノール系樹脂とエポキシ
系樹脂との混合物を用いることが望ましい。
In particular, it is desirable to use a mixture of a phenolic resin and an epoxy resin as the thermosetting resin.

前記接着剤中の各成分の配合割合はゴム粒子25〜60
重量饅、熱硬化性樹脂75重重量板下の範囲にすること
が望ましい。
The blending ratio of each component in the adhesive is 25 to 60 rubber particles.
It is desirable that the weight of the thermosetting resin be within the range of 75 weight plates.

なお、接着剤は上記二成分の他、必要に応じてコーテイ
ング性、密着性を向上するためのコロイド状シリカ等の
無機質微粉末、或いはゴム粒子の加硫剤である硫黄、促
進剤であるメルカプタン系化合物などの添加剤を併用し
てもよい。
In addition to the above two components, the adhesive may optionally contain inorganic fine powder such as colloidal silica to improve coating properties and adhesion, sulfur as a vulcanizing agent for rubber particles, and mercaptan as an accelerator. Additives such as system compounds may be used in combination.

本発明における絶縁基板への四部形成手段としとては、
例えば絶縁基板に化学メッキ用接着剤層を被覆する際に
、形成すべき回路パターンに所望深さの凹部形成する方
法、絶縁基板表面に化学メッキ用接着剤層を被覆した後
、形成すべき回路パターンと同形の凸状パターンを有す
る金型を用いてプレスして凹部を形成する方法等を挙げ
ることができる。
In the present invention, the means for forming four parts on the insulating substrate is as follows:
For example, when coating an insulating substrate with an adhesive layer for chemical plating, a method of forming a recess of a desired depth in a circuit pattern to be formed, and a circuit to be formed after coating an adhesive layer for chemical plating on the surface of an insulating substrate. Examples include a method of forming recesses by pressing using a mold having a convex pattern of the same shape as the pattern.

こうして形成された凹部には化学メッキ処理、研摩によ
り回路パターンが形成されることから、その深さは析出
する化学メッキ膜の膜厚と同等ないしそれより大きくな
るよう選定することが望ましい。
Since a circuit pattern is formed in the recess thus formed by chemical plating and polishing, it is desirable that the depth is selected to be equal to or larger than the thickness of the chemically plated film to be deposited.

本発明における化学メッキ手段としては、例えば化学銅
メッキ法、化学ニッケルメッキ法を挙げることかできる
Examples of the chemical plating means in the present invention include chemical copper plating and chemical nickel plating.

本発明における化学メッキ処理後の絶縁基板表面の研摩
手段としては、例えばパフ研摩法等を挙げることができ
る。
Examples of polishing means for polishing the surface of the insulating substrate after chemical plating in the present invention include a puff polishing method.

次に、本発明の実施例を第1図〜第5図を参照して説明
する。
Next, embodiments of the present invention will be described with reference to FIGS. 1 to 5.

〔[〕 まず、ポリエステルフィルム1a、1bの片
面に、アクリロニトリルゴム40重量部、レゾール型フ
ェノール樹脂20重量部、ビスフェノール型エポキシ樹
脂20重量部、シリカゲル10重量部及び硬化剤10重
量部をメチルエチルケトン−ブチルセロソルブ混合溶剤
で溶解した接着剤を夫々塗布し、乾操、硬化させて厚さ
約30#1の化学メッキ用接着剤層2a、2bを形成し
た。
[[] First, 40 parts by weight of acrylonitrile rubber, 20 parts by weight of resol-type phenol resin, 20 parts by weight of bisphenol-type epoxy resin, 10 parts by weight of silica gel, and 10 parts by weight of a curing agent were added to one side of polyester films 1a and 1b using methyl ethyl ketone-butyl cellosolve. Adhesives dissolved in a mixed solvent were applied, dried and cured to form chemical plating adhesive layers 2a and 2b having a thickness of about 30 #1.

つづいてこれらポリエステルフィルム1a、1bをその
接着剤層2a 、2bが対向するように配置し、これら
ポリエステルフィルム1a、Ib間に複数枚のプリプレ
グ3・・・を介在させた後、形成すべき回路パターンに
対応する箇所に凸状パターン4a・・・、4b・・−を
有する上下金型5a 、sbにより前記フィルムla。
Subsequently, these polyester films 1a and 1b are arranged so that their adhesive layers 2a and 2b face each other, and a plurality of prepregs 3... are interposed between these polyester films 1a and Ib, and then a circuit to be formed is formed. The film la is formed by upper and lower molds 5a and sb having convex patterns 4a, 4b, . . . at locations corresponding to the patterns.

1bとプリプレグ3・・・を熱圧着した(第1図図示)
1b and prepreg 3... were bonded by thermocompression (as shown in Figure 1)
.

こうして熱圧着し、ポリエステルフィルム1a、1bを
剥離することにより、第2図に示す如く絶縁基板6の両
面に接着剤層2a、2bを被覆すると共に、形成すべき
回路パターン領域に凹部7・・・を形成した。
By thermocompression bonding and peeling off the polyester films 1a and 1b, both surfaces of the insulating substrate 6 are coated with adhesive layers 2a and 2b as shown in FIG. 2, and recesses 7 are formed in the circuit pattern area to be formed.・was formed.

〔ii〕 次いで、前記絶縁基板6の凹部7・・・の
一部に上下に貫通するスルホール孔8・・・をドリルで
孔明けした(第3図図示)。
[ii] Next, through-hole holes 8 that vertically penetrate through a portion of the recesses 7 of the insulating substrate 6 were drilled (as shown in Figure 3).

つづいて、クロム酸500g/A及び硫酸250 g/
11の成分組成の混液(液温40℃)で7分間親水化処
理して接着剤層2a 、2bを粗面化し、更に米国シラ
プレー社の化学メッキプロセスに代表される活性化処理
を施した後、米国マグダミット社の化学銅9027浴中
で処理してスルホール孔8・・・を含む全面に化学銅メ
ッキ膜9を析出させた(第4図図示)。
Next, chromic acid 500g/A and sulfuric acid 250g/A
After roughening the adhesive layers 2a and 2b by making them hydrophilic for 7 minutes with a mixed solution having the composition of No. 11 (liquid temperature: 40°C), the adhesive layers 2a and 2b were further subjected to an activation treatment represented by the chemical plating process of Silaplay Co., Ltd. in the United States. , a chemical copper plating film 9 was deposited on the entire surface including the through-hole holes 8 (as shown in FIG. 4).

ひきつづき、絶縁基板6の両面をパフ研摩して該基板6
の凸部に析出した化学銅メッキ膜9部分を除去して凹部
に残存した化学銅メッキ膜からなる回路パターン10及
びこれと接続したスルホール11を備えた印刷配線板を
製造した(第5図図示)。
Continuing, both sides of the insulating substrate 6 are polished by puff polishing.
The chemical copper plating film 9 portions deposited on the convex portions were removed to produce a printed wiring board having a circuit pattern 10 made of the chemical copper plating film remaining in the recesses and through holes 11 connected to the circuit pattern 10 (as shown in Fig. 5). ).

しかして、本発明はメツキレシストを何んら用いること
なく、絶縁基板6の凹部7・・・に残存した化学銅メッ
キ膜により回路パターン10を形成できる。
Therefore, in the present invention, the circuit pattern 10 can be formed using the chemical copper plating film remaining in the recesses 7 of the insulating substrate 6 without using any metal resist.

したがって、メツキレジス+を用いたことに伴なう化学
銅メッキ浴の汚染を防止できると共に、メツキレシスト
に析出した化学銅メッキによる回路パターン間のショー
トを解消した高信頼性の印刷配線板を得ることができる
Therefore, it is possible to prevent contamination of the chemical copper plating bath due to the use of Metsuki Resist+, and to obtain a highly reliable printed wiring board that eliminates short circuits between circuit patterns caused by chemical copper plating deposited on the Metsuki Resist. can.

なお、本発明は上記実施例の如く化学銅メッキ処理後に
絶縁基板表面をパフ研摩して回路パターンを形成する方
法に限らず、活性化処理した後表面をパフ研摩して絶縁
基板の凸状の接着剤層に付着した触媒を除去し、ひきつ
づき化学銅メッキ処理を施して触媒が残存した接着剤層
の凹部に化学銅メッキ膜を選択的に析出させ回路パター
ンを形成してもよい。
Note that the present invention is not limited to the method of puff-polishing the surface of an insulating substrate after chemical copper plating to form a circuit pattern as in the above-described embodiment; The catalyst adhering to the adhesive layer may be removed, followed by chemical copper plating treatment to selectively deposit a chemical copper plating film in the recesses of the adhesive layer where the catalyst remains, thereby forming a circuit pattern.

以上詳述した如く、本発明によればメツキレシストを伺
んら用いることなく凹部に化学メッキ膜からなる回路パ
ターンを形成でき、もって化学メッキ浴の汚染を防止し
てメッキ浴の耐用寿命を向上できると共に回路パターン
間のショートのない高信頼性の印刷配線板を製造できる
等顕著な効果を有する。
As detailed above, according to the present invention, a circuit pattern made of a chemically plated film can be formed in the recessed portion without using a metal resist, thereby preventing contamination of the chemical plating bath and improving the service life of the plating bath. At the same time, it has remarkable effects such as being able to manufacture highly reliable printed wiring boards without short circuits between circuit patterns.

【図面の簡単な説明】[Brief explanation of drawings]

第1図〜第5図は本発明の実施例における印刷配線板の
製造工程を示す断面図である。 2a 、 2b・・・・・・化学メッキ用接着剤層、5
a t5b・・・・・・金型、6・・・・・・絶縁基
板、7・・・・・・凹部、8・・−・−・スルホール孔
、9・・・・・・化学銅メッキ膜、10・・・・・・回
路パターン、11・・・・・・スルホール。
1 to 5 are cross-sectional views showing the manufacturing process of a printed wiring board in an embodiment of the present invention. 2a, 2b...Adhesive layer for chemical plating, 5
a t5b...Mold, 6...Insulating substrate, 7...Concavity, 8...Through hole, 9...Chemical copper plating Membrane, 10...Circuit pattern, 11...Through hole.

Claims (1)

【特許請求の範囲】[Claims] 1 絶縁基板の表面にゴム粒子が均一分散した熱硬化性
樹脂を主成分とした化学メッキ用接着剤層を形成する工
程と、この絶縁基板の形成すべき回路パターン領域に所
望深さの凹部を設ける工程と、前記絶縁基板の接着剤層
を親水化、活性化処理した後、化学メッキ処理を施す工
程と、前記絶縁基板表面を機械的に研摩して該基板の凸
部に析出した化学メッキ膜を除去する工程とを順次行な
うことを特徴とする印刷配線板の製造方法。
1. A step of forming a chemical plating adhesive layer mainly composed of a thermosetting resin in which rubber particles are uniformly dispersed on the surface of an insulating substrate, and forming a recess of a desired depth in the circuit pattern area on which the insulating substrate is to be formed. a step of applying a chemical plating treatment after hydrophilizing and activating the adhesive layer of the insulating substrate; and a step of mechanically polishing the surface of the insulating substrate to deposit chemical plating on the convex portions of the substrate. 1. A method for manufacturing a printed wiring board, comprising sequentially performing a step of removing a film.
JP55173563A 1980-12-09 1980-12-09 Printed wiring board manufacturing method Expired JPS5826192B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55173563A JPS5826192B2 (en) 1980-12-09 1980-12-09 Printed wiring board manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55173563A JPS5826192B2 (en) 1980-12-09 1980-12-09 Printed wiring board manufacturing method

Publications (2)

Publication Number Publication Date
JPS5796591A JPS5796591A (en) 1982-06-15
JPS5826192B2 true JPS5826192B2 (en) 1983-06-01

Family

ID=15962866

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55173563A Expired JPS5826192B2 (en) 1980-12-09 1980-12-09 Printed wiring board manufacturing method

Country Status (1)

Country Link
JP (1) JPS5826192B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6044992A (en) * 1983-08-19 1985-03-11 三洋電機株式会社 Electromagnetic induction heater

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6044992A (en) * 1983-08-19 1985-03-11 三洋電機株式会社 Electromagnetic induction heater

Also Published As

Publication number Publication date
JPS5796591A (en) 1982-06-15

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