JPS5825780A - Multisystem color television receiver - Google Patents

Abstract

PURPOSE:To detect vertical synchronizing signal frequencies of different television systems stably and without adjustment, by providing a circuit which detect two kinds of vertical frequency, and a circuit which hold them. CONSTITUTION:An input vertical synchronizing signal is inputted to a vertical synchronizing pulse generating circuit 2 through a masking circuit 1 to output a vertical synchronizing pulse. This pulse resets a 9-bit binary counter 3, to which a horizontal synchronizing signal is inputted, to start counting the horizontal synchronizing signal. Three horizontal synchronizing signal detecting circuits 4, 5, and 6 which detect the number of horizontal synchronizing signals are provided in the output side of this counter; and when respective horizontal synchronizing pulses are detected by these circuits 4, 5, and 6, and these pulses are held by holding circuits 7, 8, and 9. Outputs of holding circuits 7, 8, and 9 are inputted to 50Hz and 60Hz vertical frequency detecting circuits 10 and 11 consisting of AND gates and are held in a holding circuit 12.

Description

[Detailed Description of the Invention] The present invention is applicable to S KCAM system, PAL system, N'rS system,
The present invention relates to a multi-system color television receiver that can receive color television broadcasts of four systems: C system and modified NTSC system.

As is well known, the multi-system color television receiver is the first
It has a circuit configuration as shown in the figure, and the horizontal/vertical oscillator and gate circuit corresponding to each system are switched by the output of the vertical frequency detection circuit X in the figure.

SUMMARY OF THE INVENTION An object of the present invention is to provide a multi-system color television receiver having a vertical frequency detection circuit capable of detecting the frequency of a vertical synchronization signal of a television signal stably and without adjustment.

Next, a vertical frequency detection circuit in a multi-system color television receiver according to the present invention will be explained based on the drawings.

FIG. 2 is a block diagram showing an embodiment of the vertical frequency detection circuit according to the present invention. The vertical synchronizing signal (2) input from the vertical synchronizing signal input terminal is input to the masking circuit 1. This is because the vertical synchronization signal is obtained by integrating the composite synchronization signal, so there is a so-called whisker on top of it, which may cause counters and flip-flops in the subsequent stages to malfunction. It is input to the synchronization pulse generation circuit ± and output as a vertical synchronization pulse. This vertical synchronization pulse is applied to the 9-bit binary counter 3.
Reset at vertical rate.

On the other hand, the horizontal synchronization signal or flyback pulse O is
The signal is input to the 9-bit binary counter 3, and this counter 3 starts counting horizontal synchronization signals.

For example, the output side of the counter 3 has 6
If it is 4μIIeC, the vertical frequency is 45Hz
Horizontal synchronizing signal detection circuits 4 and 5.6 are connected to detect the following signals: (347 horizontal synchronizing signals), 55 Hz (284 horizontal synchronizing signals), and 65 Hz (242 horizontal synchronizing signals). These horizontal synchronization signal detection circuits 4.
5 and 6 are constituted by AND gates 41, 51, and 61, respectively, as shown in FIG. Then, when the 9-bit binary counter 3 counts 242 horizontal synchronizing signals (11110010 in binary), the AND gate 4
The output of 1 becomes IHI for 1 horizontal period.

Furthermore, when counter 3 counts 284 horizontal synchronizing signals (100011100 in binary), AND gate 5
The output of 1 becomes 1H''.Similarly, the horizontal synchronization signal is 347
When only this number (101011011 in binary) is counted, the AND gate 61 becomes 1Hw. The above relationship is expressed as 50H
An example of z*60 Hz is shown in the timing chart shown in FIG. 4 at ■ and l.

These horizontal synchronization signal detection circuits 4.5.6 are holding circuits made up of a first group of flip-flops. , 8.9. The holding circuits 7, 8.9 are for holding the output detected during one vertical period, and are connected to the T7 lip-flops 71, 81, .
91 and ANDGATE 72.82.92 and R-8
73 degrees of flip-flops, 347 flip-flops, are counted, and when the horizontal synchronizing signal detection circuit 4 degrees 5.6 reaches 1*1, it is held. And R-S flip-flop 73.8
The Q output of 3.93 is the horizontal synchronization signal detection circuit 4, 5.6
If the output of
If 42, 284, and 347 are not counted, the Q output will be -Ll. These relationships can be expressed as follows: vertical frequency is 50
Hz.

An example of the case where the frequency is 50 Hz is shown in I and II of FIG.

The output of this holding circuit 7.8.9 is input to a vertical frequency detection circuit 10.11. And the vertical frequency is 50
In the case of Hz, the horizontal synchronizing signal is approximately 312 in one vertical period, and at this time, the Q output of the holding circuit 7 is -H-, the Q output of the holding circuit 8 is lHl, and the Q output of the holding circuit 9 is 1H1. , AND gates 10. connected as shown in FIG. Vertical frequency 50 Hz detection circuit 10 consisting of
The output of the AND gate 111, which is the vertical frequency 60 Hz detection circuit 11, becomes IL".

Therefore, the 50-60Hz holding circuit 12 holds 50Hz. This 50-60Hz holding circuit 12 is connected to a second R-8 flip-flop circuit 1 as shown in FIG.
It consists of 21.

On the other hand, when the vertical frequency is 60 Hz, the horizontal synchronization signal is te#'! in one vertical period. Since there are 1'262 lines, the Q output of holding circuit 7 is lHl, the Q output of 8 is 1H'', the Q output of 9 is IIHI, and the output of vertical frequency 50Hz detection circuit 10 is 1L1, vertical frequency 60Hz detection circuit 11.
The output is lHl, and the R-8 flip-flop 12. which constitutes the 50-60Hz holding circuit 12. is 60Hz
hold.

The second flip-flop 121 also has a function of maintaining the original state when the number of horizontal synchronizing signals exceeds 347 or falls below 242. As shown in the timing chart in Figure 4, 50Hz is currently being detected and the horizontal synchronization signal is 347.
Consider when it goes beyond a book (below 45Hz). At this time,
The outputs of 41, 51, and 61 in FIG.
101 and 111 are both lLI, and in this state, the Q output of the 50 to 60 Hz holding circuit 12 is not changed, so the previous state is held.

On the other hand, consider a case where 50 Hz is currently being detected and the horizontal synchronizing signal is less than 242 (65 Hz or more), as shown in the timing chart (2) in FIG. At this time, the third
The gravity forces of the AND gates 41.51 and 61 in the figure are both l L I, the state - is held by the holding circuits 7 and 8.9, and their Q outputs become ILI+. Therefore, the output of -AND gate 1011 is II
1 Both are @L l, and in this state 50-60Hz
The Q output of the holding circuit 12 is not changed.

Similarly, when the vertical frequency is 60 Hz, no change occurs in the output of the 50-60 Hz holding circuit 12 even when the number of horizontal synchronizing signals exceeds 347 or falls below 242.

As explained above, in the present invention, the outputs of the vertical frequency 50 Hz detection circuit and the vertical frequency 60 Hz detection circuit are input to the 20R-8 flip-prop circuit, so the number of horizontal synchronization signals is not specified. If the number exceeds or decreases, the original state is maintained and the frequency of the vertical synchronization signal can be detected stably and without adjustment.

Furthermore, as shown in FIG. 5, since the entire circuit can be constructed of IIL, reliability and productivity are improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of a multi-system color television receiver, FIG. 2 is a block diagram showing an embodiment of a vertical frequency detection circuit according to the present invention, and FIG. A specific circuit diagram, FIG. 4, is a timing chart for explaining the operation of the vertical frequency detection circuit of the present invention, and FIG. 5 is a circuit diagram in which the vertical frequency detection circuit of the present invention is configured with IIL. 1...Masking circuit, 2...
...Vertical synchronization pulse generation circuit, 3...
...Counter, 4.5,6...Horizontal synchronization signal detection circuit, 7.8.9...Holding circuit, 10.11... ... Vertical frequency detection circuit, 12 ・=-5060Hz holding circuit, 10.
, 11. j 41151, 61.72.82.92...
......And Gate, 121. ? 3.83.
93・・・・・・R-8 flip prop, 71
, 81.91...T flip-flop. Patent applicant Matsushita Electric Industrial Co., Ltd. 4 Figure 4 1.50Hz scream
Ichiho - Natsu, Ya & 50 Hz to adult No. 14 over 347 courses I2I11 force Q L Procedural amendment (method) Revenue stamp amount yen February 17, 1980 Commissioner of the Patent Office Shima 1) Haruki Tono ■・case Indication Relationship to patent application No. 56-124001 Applicant address 1006 Kadoma, Kadoma City, Osaka Prefecture Name! !
+: (582) Representative of Matsushita Electric Industrial Co., Ltd.
Toshi Yamashita Hikoton story 03 (43
1) 811 ] No. Z) 5. Date of procedural amendment order: January 5, 1980 (Shipping date: January 26, 1982) 6. Number of inventions increased by amendment 07. Subject of amendment Drawing 8, details of correction Figure 4 will be corrected in the attached document. That's all for Figure 4 ■ ■ 0--Ichirin--------
----Plate-12t, IO: i PA JP-A-58-25780 (7) ■ 12 Yo QL Procedural amendment (voluntary) February 17, 1981 Commissioner of the Japan Patent Office Shima 1) Haruki Tono 1, Indication of the incident Patent Application No. 124001/1982 2.
Name of the invention Yukaeka, -kaLz, :') =+
79 Image Machine 3, Relationship with the amended person case Applicant Address 1006 Oaza Kadoma, Kadoma City, Osaka Name (582) Representative of Matsushita Electric Industrial Co., Ltd.
Toshihiko Yamashita 4, agent 〒105

Claims (1)

[Claims] In a multi-scheme color television receiver that can automatically detect two or more broadcasting systems, switch the television set's circuitry, and automatically select each broadcasting system, different vertical synchronizing signal frequencies can be A counter that is reset at the same frequency as the horizontal synchronization signal or flyback pulse, and the output of the counter is converted to the frequency of the vertical synchronization signal, which is lower than the lower frequency of the vertical synchronization signals with different frequencies. a circuit for detecting the number of horizontal synchronization signals corresponding to a frequency f1, a frequency f2 between each of the vertical synchronization signals having different frequencies, and a frequency f3 higher than the higher frequency of the vertical synchronization signals having different frequencies; It is equipped with a 16th flip-flop group that holds detection results and a second flip-flop that holds logic levels corresponding to respective frequencies of vertical synchronization signals having different frequencies obtained by gating the output of the first flip-flop. The frequency of the vertical synchronizing signal is automatically detected, and the number of horizontal synchronizing signals or flyback pulses is 1. When the second flip-flop is lower than f1 or higher than f3, the second flip-flop is provided with a vertical frequency detection circuit that maintains a logic level state corresponding to a frequency of a previous vertical synchronization signal having a different frequency. A multi-format color television receiver with special features.