JPS5824192A - Electronic musical instrument - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic musical instrument in which the progress of automatic performance is automatically controlled in accordance with the operation timing of operators such as keys on a keyboard.

In general, automatic performance devices for electronic musical instruments include those that automatically play bass tones and chord tones, those that automatically play arpeggio tones, those that automatically play rhythm tones, or a combination of these as appropriate. In either case, if you start by setting a tempo, this initial tempo is maintained until the end and automatic performance is performed.

Electronic musical instruments equipped with such automatic performance devices
1. When performing a performance by pressing a key in accordance with an automatic performance from an automatic performance device, an undesirable situation may occur if the timing of the key depression deviates from the progress of the automatic performance. For example, if we consider a case where the key press timing is early compared to the progress of automatic performance, automatic performance will maintain a constant tempo regardless of the key press, so the next key press timing should have an appropriate note length interval. The progress from the automatic performance will remain as is, and if the next key press timing is set to match the automatic performance, the interval between key presses will become longer, making it impossible to obtain an appropriate note length. Conversely, if we consider a case where the key press timing is late relative to the automatic performance, if the next key press timing has an appropriate note length interval, the delay from the automatic performance will remain, and the next key press timing will be delayed. If you match it to automatic performance, the interval between key presses will become shorter, making it impossible to obtain the appropriate note length.

The present invention has been made in view of the above-mentioned points, and an object of the present invention is to provide an automatic performance device in which the progress and stop of automatic performance is automatically controlled in accordance with the operation timing of the operator.

According to the present invention, the automatic performance sound timing and the key press timing are compared, and in this comparison, if the key press timing is earlier than the automatic performance sound generation timing, the automatic performance is advanced rapidly or instantaneously; When the key press timing is later than the automatic performance sound generation timing, the progress of the automatic performance is temporarily stopped, and the progress of the performance by key depression and the automatic performance are made to match.

Hereinafter, one embodiment of the present invention will be described in detail with reference to the accompanying drawings.

Figure 1 shows a melody tone automatic performance function that reads recorded data on a magnetic tape 1a formed on a musical score 1 with a musical score data reading bag@2, and automatically plays melody tones based on this read data, as well as chord tones, bass tones, etc. This embodiment shows an example in which the present invention is applied to an electronic musical instrument equipped with an automatic accompaniment tone performance function for automatically playing accompaniment tones and an automatic rhythm tone performance function for automatically playing rhythm tones. However, in this embodiment, the automatic performance of the melody sound based on reading the score data is executed for melody performance practice, and is used to automatically play the melody sound at a low volume and to display the key to be pressed next. It will be done. That is, in this embodiment, the automatic performance of the melody tone is always performed and displayed one note earlier.

Musical score data reading device that reads recorded data on magnetic tape 1a formed on Raku11! The output of 2 is applied to the data memory 3 and the data format corresponding to the read data is selected. An example of this data format is shown in Table 1.

Table 1, that is, each data Dt (+=1...n) consists of pitch data TL1 and note length data TL2, where pitch data TL1 is, for example, a 4-pit note code NG indicating a note and a 3-pit note code indicating an octave. It is composed of a total of 7 bits of data including a bit octave code OC, and the code length data is composed of, for example, 8 bits of data. An example of note length data is shown in Table 2.

Table 2: Rests are represented by setting all bits of pitch data to 0, and n indicates the end of the data, and n indicates all bits of pitch data TL1 and note length data TL2. 1''.

Reading of each data D1 from the data memory 3 is performed by the address counter 4. This address counter 4
First, when turning on the power, the start/stop control circuit 5
It is reset by the output of the 7 lip 70 knob 51. That is, the initial clear signal IC generated when the power is turned on is applied to the set terminal S of the flip-flop 51 of the start-stop control circuit 5 via the OR circuit ORI, and thereby the flip 70 knob 51 is set and the address counter 4 is set. Clear initials.

Also, the flip-flop 5 of the start-stop control circuit 5
The output of 1 is the disable terminal DN of data memory 3.
S, making the data memory 3 inoperable.

Subsequently, when the start set switch 52 of the start/stop control circuit 5 is turned on, the output of the start set switch 52 is differentiated by the differentiating circuit 53 and then applied to the flip-flop 51 and the set terminal R, and the output of the start set switch 52 is applied to the flip-flop 51 and the set terminal R. −Reset. As a result, the reset of the address counter 4 is canceled and the data memory 3 becomes operational.

Further, the differential output (one pulse) of the differentiating circuit 53 is applied to the reset terminal R of the flip-flop 54 via the OR circuit OR2, resets the flip 70 knob 54, and is sent out as a start set signal SS. The output Q of the flip-flop 54 is used as play signals P and L as described later. In this case, the start set signal 5S (one pulse) remains raw, but the play signal PL remains "0". Further, the output of the differentiating circuit 53 is applied to the clock terminal GK of the counter 4 as an address clock signal ACK via the OR circuit OR3, and advances the address counter 4 by one switch. Pitch data TL1 regarding sound
and read out the note length data TL2. Pitch data TL1 and note length data TL2 read from data memory 3 are applied to latch circuit 6. The latch circuit 6 is
The strobe terminal S is the output of the OR circuit 3 mentioned above (
An address clock signal ACK) is applied via a delay circuit 7, and the output of this delay circuit 7 causes the first
Pitch data TL1 and note length data TL2 related to the note are latched. Of the data latched in the latch circuit 6, the pitch data TLI is added to the rest detection circuit 8, the key display control circuit 91 of the melody sound forming section 9, and the automatic performance melody sound forming circuit 92, and the note length data TL2 is latched. added to circuit 10. However, in the latch circuit 10, since the output of the OR circuit OR3 is applied to the strobe terminal S as is (without delay), the note length data TL2 regarding the first note is not latched. The rest detection circuit 8 is for detecting rests, and as mentioned above, rests are represented by setting all the pits of pitch data TL1 to °0'', so this can be used to detect rests. A rest detection signal RD is generated.

The key display control circuit 91 of the melody sound forming section 9 is for controlling the display of the key corresponding to the added pitch data TL1, and becomes operational when the key display select switch 93 is turned on. A key display signal for displaying the key corresponding to the pitch data TL1 is sent to the upper keyboard 94. Although details are not shown in the upper keyboard 94, indicator lamps are provided corresponding to eight keys, and the key display control circuit 91
The corresponding display lamp is turned on in response to the key display signal from the key display signal. Note that when the key display select switch 93 is off, the key display system W circuit 91 is inactive and no key display is performed on the upper keyboard 94.

Further, the automatic performance melody sound forming circuit 92 is for forming a melody sound corresponding to the added pitch data TL1. The automatic performance melody sound forming circuit 92 is activated and enabled by turning on the melody sound automatic performance selection switch 95, forms a musical sound signal corresponding to the melody sound indicated by the added pitch data, and sends this to the sound system 11. In addition, it is pronounced as a melody sound. Note that when the melody sound automatic performance selection switch 95 is off, the automatic performance melody sound forming circuit 92 is inactive, so that no melody sound is generated by automatic performance.

That is, first, under the condition that the key display select switch 93 is on, the key of the first note to be played (the key to be pressed first) is displayed by the display lamp disposed on that key.
Further, the first note of the performance (the note to be produced first) is produced under the condition that the melody tone automatic performance selection switch 95 is on.

Note that the sounds produced by the automatic melody sound forming circuit 92 are those that should be played, so normally the melody sound automatic performance select switch 95 should be turned off or the volume for adjusting the volume of the automatic melody sound ( (not shown) before use.

The following description will be made assuming that the melody tone automatic performance selection switch 95 is OFF.

In this state, when a key on the upper keyboard 94 whose display lamp is lit is pressed, the pressed key is detected by the key switch circuit 96, and the key switch circuit 96 sends a key code KC (bit of the bit) indicating the pressed key. (consisting of a note code NG and a 3-bit octave code OC) is output. This key code KC is applied to the melody sound forming circuit 97. The melody sound forming circuit 97 forms a musical sound signal corresponding to the melody sound indicated by this key code KO, adds this to the sound system 11, and causes it to be produced as a melody sound.

In addition, the key code K output from the key switch circuit 96
C is applied to the B input of comparator circuit 12.

The comparison circuit 12 has pitch data TL1 of the data latched in the latch 6 added to the input to the input, and pitch data TLI (indicating the note to be pressed) added to the input to the input B. When the added key codes KC (indicating the pressed sound) match (A-B), a match signal is output. This "coincidence multiplication signal" is added to the AND circuit 1. The AND circuit A1 uses a differentiator circuit 13 to differentiate the key-on signal KON (a signal that becomes 1" when the key is pressed and becomes 0" when the key is released) output from the other input key switch circuit W96. A pulse (key press coincidence signal) KEQ synchronized with the press of the key is output under the condition that a key whose display lamp is lit is pressed.This key press coincidence signal KEQ is a select signal. It is applied to the fast forward stop control circuit 15 via the switch 14, and also applied to the set terminal S of the 7-lip 70 knob 54 of the start-stop control circuit 5 and the AND circuit A2. If this is the case, the signal KEQ will be generated no matter what key is pressed on the keyboard.The following description will be made assuming that the select switch 14 is switched as shown.

The fast-forward stop control circuit 15 does not operate in response to the above-mentioned -seller key press coincidence signal KEQ. However, the flip-flop 54 of the start-stop control circuit 5 is reset, and the play signal PL output from the flip-flop 54 is added to the AND circuit A via the delay flip 70 tube 6F1 and the inverter INI.
2 is operable, so the key press coincidence signal @KEQ is sent to the OR circuit OR3 and OR circuit via this AND circuit A2.
Add to 4. Therefore, the address clock signal ACK is output from the output of the OR circuit OR3, and the address counter is advanced by one step. Further, the output of the OR circuit OR4 is used as the key-on timing signal KOT by the tempo control circuit 16.
added to.

This key timing signal KOT is used in the tempo control circuit 16 to control the generated tempo pulse TP, as will be described later.

In addition, the flip-flop 54 receives a key press coincidence signal K for the single-sale opening.
It is set by EQ, and the play signal PL rises to "1", so the signal applied to the AND circuit A2 via the delay flip 70 block DF1 and the inverter IN1 becomes "O" with a delay of one clock time from the rise of the play signal, and the AND circuit A2 becomes inactive and AND circuit A2
Passage of the key press coincidence signal KEQ thereafter is prohibited.

Also, since the output of the OR circuit OR3 is applied to the strobe terminal of the latch circuit 10, the latch circuit 10 has the latch 6.
The note length data TL2 related to the first note latched in is latched.

- The data memory 3 is advanced by one step in the address counter 4 in response to the key press coincidence signal KEQ from the sales outlet.
data D2 (pitch data TL1,
The code length data T2) is read out, and this data D2 is latched into the latch circuit 6 by a signal obtained by delaying the output of the OR circuit OR3 by the delay circuit 7. Of the data latched in the latch circuit 6, the pitch data TL1 is applied to a rest detection circuit and a melody sound formation circuit 9, and is used to detect rests and display indicator lamps placed on the key of the next note to be sounded. Control at points. These controls are similar to those described above.

Also, a play signal PL generated from the start/stop control circuit 5 is applied to the tempo control circuit 16. The tempo control circuit 16 forms a tempo pulse TP that determines the tempo of automatic performance in this embodiment, and the detailed configuration will be explained later, but in the initial state, the play signal PL is
A preset initial tempo pulse is output on the condition that . This tempo pulse TP is applied to the zero terminal CK of the rhythm counter 17 via an AND circuit A3 and an OR circuit OR5.

The rhythm counter 17 counts the tempo pulse king P and controls the progress of automatic accompaniment tone performance, which will be explained below. The rhythm counter 17 is configured to be initially set by the output of a flip-flop 19, which is set by a signal obtained by differentiating the play signal PL described above by a differentiating circuit 18. Also stop switch 2o
is for stopping the automatic performance of accompaniment tones, and by turning on the stop switch 20, the flip-flop 19 is reset and the rhythm counter 17 is made inactive.

The output of the rhythm counter 17 is applied to the rhythm pattern generation circuit 211 of the accompaniment sound forming section 21. The rhythm pattern generation circuit 211 stores a predetermined performance pattern using the output of the rhythm counter 17 as an address signal, and has an eid-only memory, and sequentially generates pattern pulses based on this performance pattern in response to the output of the rhythm counter 17. do. Pattern pulses generated by the rhythm pattern generation circuit 211 are applied to the accompaniment sound formation circuit 212 and the rhythm sound formation circuit 213.

The accompaniment sound forming circuit 212 detects the key being pressed on the lower keyboard 217 and outputs the key information indicating this key. It accepts the output of the key switch circuit 216 that outputs key information indicating the key, and corresponds to accompaniment sounds such as chord tones, bass tones, and albejo tones based on the key information and pattern pulses 2 sequentially output from the rhythm pattern generation circuit 211. form a musical tone signal.

Further, the rhythm sound forming circuit 213 opens and closes a plurality of rhythm sound sources based on the pattern pulses generated from the rhythm pattern generating circuit 211, and forms musical sound signals corresponding to the rhythm sounds.

Note that there are various well-known devices for forming accompaniment sounds such as chord tones, bass tones, arpeggio tones, etc. based on key information and pattern pulses from the lower keyboard and pedal keyboard, and devices for forming rhythm sounds based on pattern pulses. can be used, so a detailed description of the configuration will be omitted in this specification.

The musical tone signal representing the accompaniment tone thus formed by the accompaniment tone forming section 21 is applied to the sound system 11 and is emitted as a musical tone.

In this way, the indicator lamp disposed on the key corresponding to the second note in the upper keyboard 94 of the melody sound forming section 9 lights up, and the indicator lamp of the upper keyboard 94 lights up when automatic accompaniment tone play has started. When a lit key is pressed, a match signal is generated from the comparator circuit 12, the AND circuit A1 becomes operational, and a key press match signal KEQ is applied to the fast forward stop control circuit 15 via the select switch 14.

The fast forward stop control circuit 15 connects the latch circuit 10 to the latch circuit 10.
Based on the ticked note length data TL2, it is determined whether the key press timing on the upper keyboard 94 is early or late, and if it is early, a fast forward signal FF is output, and if it is late, a stop signal ST is output. This fast forward signal FF is applied to the AND circuit A4, and is inverted by the inverter IN2, and is then applied to the AND circuit A3.
added to.

As a result, the AND circuit A3 becomes inoperable, but the AND circuit A4 becomes operable, and the high-speed clock pulse φ is passed through the AND circuit A4 and the OR circuit OR5 to the tempo pulse T.
Output as P. Therefore, the automatic performance progresses rapidly, and the progress of the automatic performance is made to coincide with the key press timing. Further, the stop signal ST is inverted by an inverter IN3 and applied to AND circuits A4 and A3. As a result, the AND circuits A4 and A3 become inactive, so the tempo pulse output from the OR circuit OR5 is stopped, and the progress of the automatic performance is stopped. As will be clear from the explanation that will be given later, this stop continues until a key is pressed, so that the progress of the automatic performance and the timing of the key press can be made to coincide.

A detailed configuration example of the fast forward stop control circuit 15 is shown in FIG. In FIG. 2, the counter 151 has the output of the OR circuit OR3 (FIG. 1) applied to the reset terminal R, and the tempo pulse TP applied to the clock terminal CK. , the tempo pulse TP is reset in synchronization with the key press timing of the first note) and thereafter the tempo pulse TP is counted.

The comparison circuit 152 has 8 inputs as the output of the counter 151,
The output of the latch circuit 10 (FIG. 1) is added to the six inputs. In this case, the information latched in the latch circuit 10 is the note length data TL2 regarding the first note, as is clear from the above description. Comparison circuit 152 compares the count value of counter 151 with the note length data TL2 applied to the six inputs, and outputs a signal "°1" to line 153 if A>8, and outputs a signal to line 154 if A-B. Enter “1”.

The key press timing for the second note may be earlier, coincident, or later depending on the relationship with the note length DTL2.The operation in each case will be explained below.1) When the key press timing is early The key timing is latch times! If it is earlier than the note length data TL2 latched in 1o, the key press coincidence signal KEQ is generated before the counted value of the counter 151 reaches the note length data TL2. Therefore, at the timing when the key press coincidence signal KEQ is generated, the comparison circuit 152 is connected to line 1.
A signal "1" is generated at 53, and the key press coincidence signal KEQ,
The AND condition of the signal on line 153 and the signal obtained by inverting the rest detection signal RD from the rest detection circuit 8 (Fig. 1) by the inverter IN4 (in this case, the rest detection signal RD is set to °゛0!') is The output of the AND circuit A5 is "1", and the output of the AND circuit A5 is the flip-flop 155.
7 lip-flop 155 is set. The output Q of the flip-flop 155 is sent out as a fast-forward signal FF, and as described above, enables the AND circuit A4 (FIG. 1) to rapidly advance the automatic performance.

Further, the output of the flip 70 tube 155 is applied to the AND circuit 6 via the delay flip 70 tube DF2.

To the AND circuit, 〇 is the other input of the inverter IN4 mentioned above.
(a signal obtained by inverting the rest detection signal RD) and a note length match signal KEQ obtained by differentiating the signal on line 154 outputted from the comparator circuit 152 by a differentiating circuit 156 are added. Therefore, when A-B is established in the comparator circuit 152, the AND condition is established at the time when the code length signal matching signal LEQ is generated, and a - signal "1" (pulse signal) is outputted to the AND circuit. This signal is applied to the OR circuit 0R3 (FIG. 1) via the OR circuit OR6 and is applied to the clock terminal GK of the address counter 4 as the address clock signal ACK.
address counter 4 by one step. In this case, since the counter 151 is advanced by the high-speed clock φ, it instantaneously reaches the mark length data TL2, and the comparator circuit 152 establishes AB. 3. Therefore, the AND condition of the AND circuit 6 is satisfied at the same time as the key press coincidence signal KEQ, and the address counter 4 is output almost simultaneously with the key press coincidence signal.
is advanced one step. In addition, the reset terminal R of the flip 70 knob 155 that outputs the fast forward signal FF has the output of 6 to the AND circuit, the output of the OR circuit OR7 which takes the OR condition of the start set signal ss1 and the initial clear signal IC. In this case, the 7-rip 70-tube 155 is reset by the output of 0 to the AND circuit, and the fast-forward signal FF becomes "0".

In other words, if the key press timing is earlier than the note length data TL2 latched in the latch circuit 1o, the counter 1
The automatic performance is rapidly advanced until the count value of 51 matches the note length data TL2, and the automatic performance progress is made to coincide with the key press timing.

2) When the key press timing matches If the key press timing matches the note length data TL2 latched in the latch circuit 1o, the key press coincidence signal KEQ
At the same time, A-8 is established in the comparison circuit 152, and 1. A signal No. 1 411 j) is generated at the fly mower 54. This signal “1”
'' is differentiated by a differentiating circuit 156 and output as a code length match signal LEQ.
The signal is added to the AND circuit A7 as a signal. The AND circuit A7 has an inverter I that inverts the rest detection signal RD at its other input.
The output of N4 and the key press coincidence signal KEQ are added. Therefore, the AND condition of the AND circuit A7 is satisfied, and the signal j l (pulse signal) is applied to the OR circuit OR3 via the OR circuit OR6. As a result, the address clock signal ACK is generated at the input of the OR circuit OR3, and this address clock The address counter 4 is advanced by one step in response to the signal ACK.In other words, if the key press timing matches the note length data TL2 latched in the latch circuit 10, the address counter 4 is advanced by one step without applying any control to the tempo pulse TP. Advance counter 4 to the next step.

3) When the key press timing is late If the key press timing is late with respect to the note length data TL2 latched in the latch circuit 10, or if the correct key press is delayed due to a mistouch, a key press coincidence signal KEQ is generated. Before, the count value of the counter 151 is the note length data T.
L'2 is reached, A-B is established in the comparator circuit 152, and a code length match signal LEQ is generated from the differentiator circuit 156. This note length signal EQ is sent to the AND circuit 8. The output signal of the inverter TN4 and the signal obtained by inverting the output of the AND circuit A7 by the inverter IN5 are added to the other inputs, and in this case, the rest detection signal RD is “0”, and the output of AND circuit A7 is 0”, so the AND condition of 8 to the AND circuit is satisfied,
Outputs signal “1”. The 8 output to this AND circuit is applied to the set terminal S of the flip-flop 157 via an AND circuit A9 whose other input is the inverted output Q (in this case, "1") of the 7 flip-flop 155. As a result, the flip 70 knob 157 is set. The output Q of this flip 70 knob 157 is sent out as a stop signal ST, and as mentioned above, AND circuits A3 and A4 (first
(Fig.) is inactive, and the progress of automatic performance is temporarily stopped.

Further, the output Q of the flip 70 tube 157 is applied to the AND circuit A10 via the delay flip-flop DF3. The output of the inverter IN4 and the key depression coincidence signal KEQ are added to other inputs of the AND circuit A10. Therefore, the AND condition of the AND circuit A10 is satisfied at the timing of the key depression coincidence signal KEQ, and the signal °゛1°' (pulse signal) is applied to the OR circuit OR3 (Fig. 1) via the OR circuit OR6, and the address clock is applied to the AND circuit A10. By generating the signal ACK, the address counter 4 is advanced by one step.

Note that the output of the AND circuit A10, the output of the OR circuit OR8 which takes the OR condition of the start set signal SS and the initial clear signal IC are added to the reset terminal R of the flip-flop 157 that outputs the stop signal ST. The flip-flop 156 is reset by the output of the AND circuit A10, and the stop signal ST becomes "0".

In other words, if the key press timing is later than the note length data TL2 latched in the latch circuit 10, the automatic performance progresses by -5 from the time the key press timing matches the note length data TL2 until the key is pressed. The progress of the automatic performance is made to match the key press timing.

In the above operation description, it is assumed that the rest detection signal RD output from the rest detection circuit 8 is "O", but if the rest detection signal RD is "1", that is, the next note to be pressed is If it is a rest, the key is not pressed at the timing of the note length data TL2.

In this case, an AND circuit A11 that takes an AND condition between the rest detection signal RD and the note length match signal LEQ outputs the note length match signal LEQ.
At the timing when EQ occurs, that is, when the count value of the counter 151 matches the mark length data TL2 latched by the latch circuit 10 in the comparison in the comparator circuit 152, a signal "1" (pulse signal) is output and this is ORed. In addition to the OR circuit OR3 via the circuit OR6, an address clock signal ACK is generated to advance the address counter by one step.

In addition, the outputs of AND circuits A5, A7, A10, and A11 are subjected to OR conditions by OR circuit OR9, and OR circuit 0R4 (
1) to the tempo control circuit 16 as a key-on timing signal KOT.

Note that although the above explanation has been based on the relationship between the first sound and the second sound, the same control is performed for the third sound, fourth sound, etc.

When the automatic performance ends, the end data is transferred from data memory 3 (all bits “1” for both pitch data TL and note length data TL2).
When read, this data is detected by the end detection circuit 55 of the start/stop control circuit 5. The detection output of the end detection circuit 55 is applied to the set terminal S of the flip-flop 51 via the OR circuit OR1, and is also applied to the reset terminal R of the flip-flop 54 via the OR circuit OR2 to set the flip-flop 51.
Reset. As a result, the data memory 3 becomes inoperable.1. The address counter 4 is reset and the play signal becomes "0".

The above operation will be explained in accordance with the timing chart shown in FIG. 3 as follows. In this case, the automatic performance is executed according to the musical score shown in Figure 3 (a'), and the second note is pressed too early, and the fourth note (rests are also counted as one note) is pressed too early. The timing is delayed, and the fifth tone shows a case where the key press timings match.

First, when the start set switch 52 of the start/stop control circuit 5 is turned on, a start set signal ss is generated as shown in FIG. 3(b). As a result, the address clock signal ACK (!3 (f)) is generated, the address counter 4 advances by one step, and the data D1 (Figure 3 (g)) related to the first tone is read out from the data memory 3. This data D1 is latched by the latch circuit 6, and based on the pitch data TL1 of the latched data, the display lamp displays the key to be pressed next on the upper keyboard 94 of the melody sound forming section 9. ) shows data related to this display.

Next, when the key displayed by the display lamp on the upper keyboard 94 (the key specified by the pitch data TL1 of the data D1) is pressed, a pressed key coincidence signal KEQ (Fig. 3 (C)
) is generated, which causes the play signal PL (Fig. 3(d)
) rises, and at the same time, address clock signal ACK is generated. Then, the code length data TL2 of the data D1 is latched by the latch circuit 10 (FIG. 3(k)) by the address clock signal ACK.
The address counter 4 is advanced by one step by CK, and data D2 is read from the data memory 3. When the data D2 is read out from the data memory 3, the latched content of the latch circuit 6 changes to data D2, and the display by the display lamp on the upper keyboard 94 of the melody sound forming section 9 is specified by the pitch data TL1 of the data D2. It becomes the key.

In this state, if the key displayed by the display lamp is pressed on the upper keyboard 94 earlier than the note length specified by the note length data TL2 of the data D1, a pressed key coincidence signal KEQ is generated at this pressing timing, but the fast forward stop control is performed. circuit 15
The count value of the counter 151 (FIG. 2) is the latch circuit 10.
Since the note length data TL2 of the data D1 latched in is not reached, the AND circuit A5 (second
The AND circuit condition shown in the figure) is satisfied, and the flip-flop 15
5 is set, and a fast forward signal FF is generated (Fig. 3 (h)
)). As a result, the AND circuit A4 (FIG. 1) becomes operational, the counter 151 is rapidly counted up by the clock pulse φ, and the comparator circuit 152
is established, and a code length match signal LEQ is generated. When the code length match signal LEQ is generated, the AND condition of the AND circuit A6 (FIG. 3) is satisfied and the address clock signal ACK is generated. This address clock signal ACK changes the contents of the latch circuit 10 to the data latched in the latch circuit 6. D2 is rewritten to the note length data TL2, and data D3 is read from the data memory 3.Flip 70 knob 155 is reset by the output of 6 to the AND circuit, and the fast forward signal FF is stopped.In other words, the key press timing is If the timing is earlier than the timing specified by the note length data TL2, the tempo pulse TP is switched to a high-speed pulse φ, and the automatic performance is rapidly advanced to match the progress of the automatic performance with the key depression timing.

By reading data D3 from data memory 3, the latched contents of latch circuit 6 change from data D2 to D3. By the way, since the data D3 is data indicating a rest, it is detected by the rest detection circuit 8, and the rest detection circuit 8 outputs a rest detection signal RD as shown in FIG. 3(e). As a result, the counter 1 of the fast forward stop circuit 15
At the timing when the contents of 51 reach the mark length data TL2 of the data D2 latched in the latch circuit 10, the AND condition of the AND circuit A11 is satisfied and the address clock signal ACK is generated.

When address clock signal ACK occurs, latch circuit 1
The content of 0 is the data D3 latched in the latch circuit 6.
The data read out from the data memory 3 changes from data D3 to D4. The contents of the latch circuit 6 are then rewritten to the data D4, and on the upper keyboard 94 of the melody sound forming section 9, the key specified by the pitch data TLI of the data D4 is displayed by a display lamp.

Here, if the key press timing is later than the timing specified by the note length data of data D, a key press coincidence signal K
Comparison circuit 15 of fast forward stop control circuit 5 before EQ occurs
Since A-B is established at 2, the AND condition for 8 is established for the AND circuit at this timing, and the flip-flop 156
is set, and a stop signal JqST (FIG. 3 (1)) is generated. When the stop signal ST is generated, the automatic performance is stopped as described above. When the key press coincidence signal KEQ is generated in this state, fast forwarding is stopped 1lIIIl11 AND circuit A of circuit 5
7 is satisfied and the address clock signal ACK
occurs. Then, by this address clock signal ACK, the mark length data TL1 of the data D4 latched in the latch circuit 6 is transferred to the latch circuit 6, the address counter 4 is advanced by one step, and the data D5 is transferred from the data memory 3. Read out. Furthermore, the flip 70 tab 157 of the fast forward stop circuit 5 is reset by the output of the AND circuit A7, and the stop signal ST becomes 0. If the timing is later than that specified by the note length data TL2, the automatic performance is stopped until a key is pressed, and the progress of the automatic performance is made to match the key press timing.

By reading the data D5 from the data memory 3, the latch data of the latch circuit 6 is rewritten to this data D5, and the key specified by the pitch data TLI of the data D5 on the upper keyboard 94 of the melody sound forming section 9 is displayed on the display lamp. displayed by. When the key displayed by this display lamp is pressed in accordance with the timing specified by the note length data of data D4 latched in the latch circuit 10, the fast forward stop control circuit 15
The AND condition of AND circuit A10 is satisfied, and address clock signal AKC is generated. That is, when the key press timing matches the timing specified by the note length data TL2, the fast forward stop circuit 5 does not apply any control to the progress of the automatic performance.

Next, the tempo control circuit 16 will be explained.

The tempo control circuit 16 controls the tempo pulse TP in accordance with the key depression tempo. That is, as the key press tempo TP becomes faster, the cycle of the tempo pulse TP is shortened accordingly, and as the key press tempo TP becomes slower, the cycle of the key press tempo TP is lengthened accordingly. This control is performed using note length data TL2 of each note latched in the latch circuit 10.
This is performed in accordance with the key-on timing signal KOT output from the OR circuit OR4.

FIG. 4 shows a detailed configuration example of the tempo control circuit 16. When a start set signal SS is generated from the start/stop control circuit 5 (FIG. 1) and then a play signal PL is generated, first the initial tempo oscillator 160. The initial tempo pulse set in is output. An initial tempo pulse of a preset frequency output from the initial tempo oscillator 160 is applied to six inputs of the selector 161. Further, the start set signal SS output from the start set circuit 5 is applied to the reset terminal latch of the flip-flop 162, and the flip 70 knob 162 is reset. The output of the flip 70 tube 162 is inverted by the inverter IN6,
AND circuit AI that can be operated by play signal PL
2 to the six-input select terminal SA of the selector 161. Therefore, the selector 161 selects the play signal P.
When L becomes "1", the initial tempo pulse output from the initial tempo oscillator 160 is selected and output.

The initial tempo pulse is used in the initial state until it becomes possible to form a tempo pulse based on the key pressed tempo (in this case, until the fourth note is pressed), and when a predetermined condition is met, the tempo pulse changes to the pressed key tempo. Based on following tempo oscillator 1
63.

Note length data TL2 regarding the first note latched by the latch circuit 10 by the address clock signal ACK output from the OR circuit 0R3 (FIG. 1) based on the press of the first note.
is applied to variable frequency divider circuit 164. Variable frequency divider circuit 16
4 is a clock pulse φ corresponding to this mark length data TL2.
is frequency-divided to output a pulse signal having a period corresponding to the code length data TL2, that is, a pulse signal having a high frequency when the code length data TL2 is small and a pulse signal having a low frequency when the code length data TL2 is large. The output pulses of this variable frequency divider circuit 164 are counted by a counter 165. The reason why the variable frequency divider circuit 164 forms a pulse signal with a period corresponding to the note length data TL2 as described above is to make the count value of the counter 165 that counts this pulse signal a value that does not depend on the note length data. It is. That is, the counter 165 sends the key-on timing signal KOT to its reset terminal r as a delay flip 70 tube DF.
A signal delayed in step 4 is added, and its count value is reset every time the key-on timing signal KOT occurs, but the count value of the counter 165 at the time of reset is based on the fact that the key depression tempo is constant. If the value is constant regardless of the note length, then the value is constant regardless of the note length.

The value corresponding to the key depression tempo counted by the counter 165 is sequentially transferred to the latch circuits L1, L2, and L3 by the key-on timing signal KOT.

In addition, the key-on timing signal KOT is the AND circuit A13.
is applied to the clock terminal OK of the counter 166 through the counter 166 and counted sequentially. This counter 166 is composed of a 3-pit shift register and outputs a carry signal when the count value is 4. Further, this carry signal is sent to the AND circuit A via the delay flip-flop DF5 and the inverter IN7.
13, and added to the subsequent AND circuit A13,
The subsequent operation of AND circuit A13 is prohibited.

The operations of the latch circuits L1, L2, L3 and the counter 166 will be explained below with reference to the timing chart shown in FIG.

In the case shown in Fig. 3, the key-on timing signal KOT is
As shown in the figure (Il), it is generated in synchronization with the key press timing. However, the key is not pressed for rests, but
It should be noted that the key-on timing signal KOT is generated at the start timing of the ninth rest. That is, rests are evaluated in the same way as keys to be pressed, and a key-on timing signal KOT is generated. First, while the note length data TL2 regarding the first note is latched in the latch circuit 10, the counter 165 counts pulse signals having a period corresponding to the note length data TL2. Then, this count value C1 is transferred to the latch circuit L1 by the key-on timing signal KOT which is applied to the second tone ((1) in FIG. 3). Similarly, the counter 165 counts pulse signals of a period corresponding to the note length data TL2 related to the second note in the latch circuit 10. Then, this count value C2 is transferred to the latch circuit L1 by the key-on timing signal KOT regarding the third tone, and
Similarly, the contents C1 of latch circuit L1 are transferred to latch circuit L2 (FIG. 3(n)). Similarly, when the key-on timing signal KOT regarding the fourth tone is generated, the content of the latch circuit L1 becomes the count value C1 (FIG. 3 (0)), the content of the latch circuit L2 becomes the count value C2, and the content of the latch circuit L3 becomes the count value C1.
The content of is the count value C3.

Further, the count value of the counter 166 is counted up in response to the key-on timing signal KOT, and when the count value reaches 4, the count is stopped.

The outputs of the latch circuits L1, L2, and L3, in which the values related to the key press tempo are latched as described above, are sent to the averaging circuit 167.
The average is taken at , and added to the latch circuit L4. Also, the output of the averaging circuit 167 is 2x circuit 1688, 1/2 circuit 1
The comparator circuit 16 is doubled and halved by 68b, respectively.
9 C input and C input. Comparison circuit 169
The output of the counter 165 is added to six inputs, and outputs a signal ``1'' when the value added to these six inputs is between the value added to the C input and the value applied to 0 people and force. .This signal "1" is applied to the AND circuit A14.The AND circuit A14 has the aforementioned counter 16 as another input.
6 and a key-on timing signal KOT. Therefore, the AND circuit A14 is the counter 16
The count value of 5 is the double value of the output of the averaging circuit 167 and 1
The key-on timing signal KO is activated on condition that the value is between /2 times the value and the count value of the counter 166 reaches 4.
The AND condition is satisfied at the timing when T is added, and a signal "1" is output. The output of this AND circuit A14 is applied to the strobe terminal set of latch circuit 4, and is also applied to the set terminal S of 7 lip flop O-tubes 162. That is, the latch circuit L4 has 1) latch circuits L1, L2, and L3 filled with data.

2) The count value of the counter 165 does not deviate significantly from the output value of the averaging circuit 166.

Under the condition, the output of the averaging circuit 167 is latched at the timing of the key-on timing signal KOT. Latch circuit L4
The value latched in is applied to the follow-up tempo oscillator 163. The follow-up tempo oscillator 163 is composed of a variable frequency dividing circuit, and generates a clock pulse φ according to the output of the latch circuit L4.
By dividing the frequency of the tempo, a follow-up tempo pulse that changes in accordance with the key depression tempo is generated. This follow-up tempo pulse is applied to eight inputs of selector 161.

Furthermore, by applying the output of the AND circuit A14 to the set terminal S, the flip 70 block 162 is set, and the output Q of the flip 70 block 162 is applied to the 8-input select terminal SB of the selector 161. Thereby, the selector 161 selects the follow-up tempo pulse to be added to the B input and outputs it as the subsequent tempo pulse TP.

The reason why the latch circuit L4 is designed not to latch the output of the averaging circuit 167 when the count value of the counter 165 deviates greatly from the output value of the averaging circuit 166 is because the tempo deviation of only one note is large. This is to prevent the frequency of the tempo pulse from changing even if it occurs.

FIG. 5 shows another example of the configuration of the tempo control circuit 16. In the configuration example shown in Figure 4, the evaluation was made the same for any key press timing regardless of the note length, but in this configuration example, the degree of influence on the follow-up tempo pulse is evaluated in accordance with the note length. I'm trying to change it. In other words, when evaluating key tempo by converting it into a value that does not depend on note length, if you treat short note lengths of 1 and long note lengths the same, the effect on the tracking tempo pulse will be less for short note lengths. Therefore, the structure is such that a long note length has less influence on the follow-up tempo pulse than a short note length. In the explanation of FIG. 5, parts that perform the same functions as the circuit shown in FIG. 4 are given the same reference numerals to simplify the explanation. In this configuration example as well, the selector 161 first selects the output of the initial tempo oscillator 160 that is added to the input and outputs it until a predetermined condition is satisfied. In other words, if the output of the OR circuit 0R10 is "1", which takes the OR condition of the outputs of the NOR circuits NR1 to NRn when each bit output of each stage of the shift register 24, which will be described later, is added (each stage of the shift register 24 This signal is applied to the input select terminal SA of the selector 161, and the selector 161 selects the initial tempo pulse output from the initial tempo oscillator 160. and output this.

On the other hand, the note length data TL2 latched by the latch circuit 10
is added to the variable frequency divider circuit 164, and the variable frequency divider circuit 16
4, a pulse signal having a period corresponding to the code length data TL2 is generated. This pulse signal is counted by a counter 165 that is reset every time the key-on timing signal KOT is counted, and the latch circuit 2
It is latched to 5. The value latched in this latch circuit 25 is added to the shift register 24.

The shift register 24 consists of n stage bits, and takes in the values latched by the latch circuit 25 as many times as the number of stages corresponding to the code length.

- The shift register 24 has a clock pulse φ applied to its shift terminal via an AND circuit A15 which is enabled to operate according to the output of the flip 70 knob 26 set by the key-on timing signal KOT and the playback signal PL. 7 by key-on timing signal KOT
When the lip 70 tab 26 is set, the values latched in the latch circuit 25 are sequentially taken in. Also, latch circuit 1
The note length data TL2 latched at 0 is latched in the latch circuit 27 by the key-on timing signal KOT, and the counter 28 to which the key-on timing signal KOT is applied to the reset terminal R counts clock pulses φ in synchronization with the key-on timing signal KOT. The output of the latch circuit 27 and the output of the counter 28 are compared in a comparison circuit 29.

When the count value of the counter 28 reaches the note length data TL2 latched by the latch circuit 27 and a coincidence output is generated from the comparison circuit 29, this coincidence output is applied to the reset terminal R of the flip-flop 26, and the flip-flop 70 knob 26 is output. Reset. As a result, the AND circuit A15 becomes inactive and the shift operation of the shift register 24 is stopped. That is, the number of stages to which the data latched in the latch circuit 25 is shifted in the shift register 24 for one key-on timing signal @KOT increases as the note length data TL2 is large, and decreases as the note length data TL2 is small.
The number corresponds to L2. For example, if the note length data TL2 corresponds to a quarter note, and the shift register 24 takes in data for 2 stages, then if the note length data TL2 corresponds to a stupid note, then the data for 2 stages is taken into the shift register 24. Data is captured. The contents of each stage of this shift register 24 are averaged by an averaging circuit 167 and applied to a follow-up tempo oscillator 163.

Assuming that each stage of the shift register 24 is filled with data, when the data related to the first note reaches the final stage of the shift register 24, the output of the OR circuit 0R10 becomes °“OII, and the output of this OR circuit 10 is sent to the selector via the inverter IN8. 161 to the B input select terminal SB.This causes the selector to select the follow-up tempo pulse to the pressed key tempo output from the follow-up tempo oscillator 163,
This will be output later.

FIG. 6 shows yet another configuration example of the tempo control circuit 16, in which the tempo pulse is corrected based on the deviation between the note length data TL2 and the note length formed by the tempo pulse i. There is. In this configuration example, the electric current 'Ff
A tempo pulse is generated by an I-controlled oscillator (VCO) 30. VC030 is manual tempo setting terminal A
and a correction terminal B, and an initial tempo is set to the manual tempo setting terminal A by a manual tempo setting device (variable resistor) 31. The tempo pulse output from vCO 30 is applied to the clock input of canter 32. The counter 32 has a key-on timing signal KOT applied to its reset terminal R, is reset every key-on timing signal KOP, and is reset by a tempo pulse T.
Count P. The tempo pulse TP count value of this counter 32 corresponds to the note length formed by the tempo pulse TP. The count value of the counter 32 is calculated by a subtracter 338
Added to human power.

The subtracter 33 has the note length data TL2 latched in the latch circuit 10 added thereto, and subtracts the count value of the counter 32 from this note length data TL2. This subtracted value I A-B + and a signal indicating its mark length are applied to the latch circuit 34 .

Further, the subtracted value I A-B + outputted from the subtracter 33 is added to the allowable value detection circuit 35 . The permissible value detection circuit 35 compares the preset permissible value and the subtracted value +A-BI, and if the subtracted value is within the permissible value range, applies a signal "1" to the AND circuit A16.

The AND circuit A16 has the key-on timing signal KOT added to its other input, and on the condition that the subtracted value in the subtracter 33 is within the range of allowable values, it outputs a signal "1" in synchronization with the key-on timing signal KOT. This signal is applied to the strobe terminal S of the latch circuit 34. That is, the latch circuit 34 outputs the key-on timing signal K on the condition that the output of the subtracter 33 is within the tolerance range.
The output of the subtracter 33 is latched at the OT timing.

The reason why the tolerance value detection □ circuit is provided here is to prevent the tempo pulse from following large changes in the key depression tempo.

The output of the latch circuit 34 is converted into an analog signal by a digital-to-analog converter 36 and applied to a correction terminal B of the VCO 30. □Although the latch circuit has one stage in the configuration example shown in FIG. 6, it may be multi-stage as in the configuration example shown in FIG. 4, and an averaging circuit for taking the average value may be provided.

FIG. 7 shows another embodiment of the invention. In this embodiment, if the key press timing is later than the note length data, or if they match, the operation is the same as in the embodiment shown in Figure 1, but if it is earlier, the delay in automatic performance is recorded in the rhythm counter. Configured for direct presetting.

In the description of FIG. 7, the same parts as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

When a start set switch (not shown) is pressed in the start/stop control circuit 5, the data memory 3 becomes operational and the reset of the address counter 4 is released. In addition, a start set signal SS is generated from the start/stop IIJ111 circuits, and this signal SS is applied to the address counter 4's output terminal CK as an address clock signal ACK via an OR circuit 0R11 to advance the address counter 4 by one step. . As a result, data D1 related to the first tone is read from the data memory 3, and the delay circuit 7 inputs the address clock signal AC to the address clock signal AC.
The delayed signal is latched into the latch circuit 6.

The signal latched by the latch circuit 6 is applied to a rest detection circuit 8, where rest detection is performed and a melody sound generation section 9
is added to display the key of the first note.

When the key of the first note is pressed in this state, a matching output is generated from the comparator circuit 12, and the AND circuit A1 becomes operable.
A press/key coincidence signal KEQ is outputted via the select switch 14. This key press coincidence signal KEQ is first applied to the start/stop control circuit 5 to output a signal indicating that the key of the first tone is pressed, and this signal is sent to the OR circuits OR12 and OR11.
is applied to the clock input of the address counter 4 as the address clock signal ACK. Also, OR circuit 0R
The output of 11 is applied to the strobe terminal S of the latch circuit 10, and latches the note length data TL2 of the data related to the first note latched by the latch circuit 6. Further, the output of the OR circuit 0R11 is applied to the reset terminal R1 of the power 1 counter 151, the preset terminal PE of the down counter 37, and the preset terminal PE of the rhythm counter 3B. As a result, the counter 151 is reset, and the down counter 37 is preset with the note length data TL2 latched by the latch circuit 10. Note that at this time, the rhythm counter 38 is preset to an initial value.

In this state, when the next key press timing is reached, a counter that forms a tempo pulse TP outputted from the tempo control circuit 16 via the AND circuit A17 will be activated. In the comparator circuit 152 that compares the count value of 151 and the output of the latch circuit 10, A>8 holds true, and the AND condition of the AND circuit A18 holds true. The output of any AND circuit A18 is sent out as an address clock signal ACK via OR circuits 0R13, 0R12, OR, 11.

By the way, down counter 37#- and rhythm counter 3
8 is the tempo pulse TP outputted from the AND circuit A17.
is added, and counts down and counts up in response to this tempo pulse TP. Therefore, in this case, the count value of the down counter at the time when the output is generated from the OR circuit 0R11 is n>o. The count value n of this down counter 37 is an adder! At step s39), it is added to the count WIN of the one-woman counter 38, and the added value N10 is preset to the direct-nosm counter 38 at the output timing of the OR circuit 0R11. That is, by presetting the additional value N10 in the rhythm counter 38, the delay value n of the rhythm counter 38 with respect to the key press timing is eliminated. Further, the counter 151 is reset by the output of the OR circuit 11, the note length data TL2 regarding the next note is latched in the latch circuit 10, and the down counter 3
7 is the note length data TL2 latched by the latch circuit 10.
is preset.

Next, the key press timing is delayed by 1 with respect to the note length data TL2 latched in the latch circuit 10, and the key press coincidence signal K
A-8 is established in the comparator circuit 152 before EQ is generated, and a code length match signal LEQ is generated from the differentiator circuit 156fiS. As a result, the AND condition of the AND circuit A19 is satisfied, and the flip 70 and the flip 157 are set. The output Q of this flip-flop 157 is applied to the AND circuit A17 via the inverter IN3, rendering the AND circuit A17 inoperative. That is, the tempo pulse TP is stopped, and the progress of the automatic performance is stopped. Also flip flop 15
The output Q of No. 7 is applied to the AND circuit A20 via the delay flip-flop DF3. This AND circuit A20
The signal becomes “1” at the timing when the key press coincidence signal KEQ occurs.
is output, and the address clock signal ACK is generated from the OR circuit 0R11. At this time, the count value n of the down counter 37 is no. Therefore, the output of the adder 39 remains the count value N of the rhythm counter 38, and this value N is preset in the rhythm counter 38 by the output of the OR circuit 0RII. Further, the output of the AND circuit A20 presets the flip-flop 157. As a result, the AND circuit A17 becomes operable and the stoppage of automatic performance is canceled.

When the key press timing matches the note length data TL2 latched in the latch circuit 10, the AND condition of the AND circuit A21 is satisfied and the address clock signal ACK is generated from the OR circuit 0R11. At this time, the count value n of the down counter 39- is neo, and the OR circuit 0R11
The value N preset in the rhythm counter 38 by the output of the rhythm counter 38 remains unchanged. In other words, no control can be applied to the progress of automatic performance.

Further, when a rest is detected by the rest detection circuit 8, the comparison circuit 1
A-8 is established in step 52, and the AND condition of the AND circuit A22 is established at the timing when the code length match signal LEQ is generated, causing the OR circuit 0R11 to generate the address clock signal ACK.

Further, in this embodiment, the key-on timing signal KOT used in the tempo control circuit 16 is obtained from the output of the OR circuit 0R12.

As explained above, according to the present invention, the progress of the automatic performance is automatically controlled in accordance with the operation timing of the controller, so the progress of the automatic performance always matches the manual performance by pressing the keys, which is preferable. You can get a performance.

Note that when a plurality of notes of the same scale are consecutive, note length data and pitch data may be formed by treating these notes as one note. With this configuration, stability in tempo can be obtained, especially when notes with short note lengths are consecutive.

Alternatively, data may be created by extracting only important notes from the melody sounds. In this case, data can be simplified.

Also, the fast-forward clock that occurs when the key press timing is early may be made to follow the tempo, be made to speed up exponentially when the note length matches, or be made to slow down exponentially for a restart. . This makes it easier to follow the performance.

Also, when controlling the frequency of the tempo pulse using past n tempo data, each of the n pieces of data may be weighted. For example, if close data is given a large weight, natural tempo control can be achieved. It becomes possible.

Furthermore, it goes without saying that the musical score data that forms the basis of automatic performance can be similarly realized with data related to the petal keyboard or the lower keyboard.

In addition, in this embodiment, the automatic performance melody sound forming circuit always monitors and sounds the melody sound to be played one note earlier, making it easier for the performer to play the melody, but the obbligato data is not stored. An obbligato generation circuit may be provided to automatically play the obbligato to assist the performer's performance.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG.
The figure is a circuit diagram showing a detailed configuration example of the fast forward stop control circuit shown in Fig. 1, Fig. 3 is a timing chart explaining the operation of the device shown in Fig. 1, and Figs. 7 is a block diagram showing a detailed configuration example of the tempo control circuit shown in FIG.
The figure is a block diagram showing another embodiment of the invention. 1... Musical score, 2... Musical score data reading device, 3...
Data memory, 4...Address counter, 5...Start/stop control circuit, 6.1o...Latch circuit,
7... Delay circuit, 8... Body step detection circuit, 9... Melody sound forming section, 11... Sound system, 12.
... Comparison circuit, 13 ... Differentiation circuit, 14 ... Select switch, 15 ... Fast forward stop control, 16 ... Tempo control circuit, 17.38 ... Rhythm counter, 21
... Accompaniment sound forming section, 37 ... Down counter, 39
...adder.

Claims (11)

[Claims] (1) A storage means for storing performance timing information, an operator, a reading means for reading out the performance timing information from the storage means in performance order based on the operation of the operator, and performance timings read from the storage means. a detection means for detecting whether the operation timing of the operator is slow or early based on the instruction timing indicated by the information; an automatic performance means; and a stop of the automatic performance by the automatic performance means in response to a detection output of the detection means. An electronic musical instrument comprising an automatic performance progress control means for controlling the progress. (2) The storage means stores the note length information of the musical tone to be played.
The electronic musical instrument according to claim 1, wherein the electronic musical instrument is stored as performance timing information. (3) The electronic musical instrument according to claim (1), wherein the operator is any key on a keyboard. (4) The electronic musical instrument according to claim 1, wherein the reading means reads out the performance timing information based on a key-on signal generated in response to an operation of the operator. (5) The detection means includes a counter that counts predetermined clock pulses from the time when the performance timing information is read by the readout means until the time when the next operator is operated, and compares the counted value of the counter with the performance timing information. An electronic musical instrument according to claim (1), further comprising a comparison circuit. (6) The predetermined clock pulse is a tempo pulse that controls the tempo of automatic performance of the performance means, and the tempo pulse is controlled based on the operation timing of the operator. electronic musical instrument. (7) When the automatic performance progress control means detects based on the output of the detection means that the operation timing of the operator is earlier than the timing indicated by the performance timing information, the automatic performance progress control means automatically controls the automatic performance progress control means. Claim No. 1 includes an automatic performance fast-forwarding means for fast-forwarding the progress of the performance.
Electronic musical instruments listed in ). (8) The automatic performance means controls the progress of the automatic performance in accordance with the count value of a tempo counter that counts tempo pulses, and the automatic performance fast-forward means converts the tempo pulses at a frequency higher than that of the tempo pulses. The electronic musical instrument according to claim 7, wherein the electronic musical instrument switches to a high pulse. (9) The automatic performance means controls the progress of automatic performance in accordance with the count value of a tempo counter that counts tempo pulses, and the automatic performance fast-forward means presets a fast-forward target value in the tempo counter. An electronic musical instrument according to claim (7). (10) When the automatic performance progress control means detects based on the output of the detection means that the addition operator has not yet been operated even at the timing specified by the performance timing information, the automatic performance progress control means automatically controls the automatic performance progress control means. The electronic musical instrument according to claim 1, further comprising an automatic performance stop means for stopping the progress of the performance. (11) The automatic performance means controls the progress of automatic performance in accordance with the count value of a tempo counter that counts tempo pulses, and the automatic performance stop means stops supplying tempo pulses to the previous tempo counter. The electronic musical instrument according to claim (10), which is prohibited.