JPS648832B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an automatic performance device that can automatically change and control the tempo depending on the performance location.

Conventionally, when an automatic performance device sets a tempo before starting a performance, the automatic performance is executed according to the set tempo. That is, the tempo of automatic performance is constant from the start to the end of the performance, and the tempo set before the start of the performance is maintained.

By the way, in general performances, it is preferable that the tempo of automatic performance be kept constant.
When practicing for beginners, it is preferable to change the tempo at difficult parts to enable key presses to follow automatic performance.

In addition, not only for beginners' practice, there are parts of a song where the tempo should be made faster or slower depending on the song's idea, and automatic tempo control of such automatic performance has been desired.

The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to provide an automatic performance device that can automatically change and control the tempo as desired depending on the performance location.

This invention is applied to an automatic performance device that records musical note data on musical notes, etc., sequentially reads out this musical note data, and performs automatic performance according to the read musical note data. According to this method, tempo change information is recorded in a part of the musical note data, and the tempo is automatically changed according to this tempo change information.

Hereinafter, one embodiment of the present invention will be described in detail with reference to the accompanying drawings.

In FIG. 1, musical note data is recorded on a musical note 1 by a magnetic tape 1a, and this musical note data is read by a musical score data reading device 2 and added to a data memory 3. The data memory 3 stores data formats corresponding to musical score data, one example of which is shown in FIG.

In Figure 2, the data format consists of tempo specification data, pitch note length data, tempo change data, tempo return data, and end data.The tempo specification data is for setting the initial tempo and is the first data in the data format. It is stored at one address and consists of a flag bit "1" indicating that it is not pitch note length data, a two-bit identification code "00" that identifies it as tempo data, and tempo data TD that specifies the initial tempo. Ru.
The pitch note length data indicates the pitch and note length of the note to be produced, and is composed of a flag bit "0", a key code KC consisting of an octave code OC and a note code NC, and note length data TL. The tempo change data specifies the location where the tempo is to be changed to a slow tempo, and is composed of a flag bit "1" and an identification code "01". This tempo change data does not include tempo data specifying the tempo, and all other bits are "0". The tempo return data specifies the point where the tempo is to be returned from the slow tempo to the initial tempo, and is composed of a flag bit "1" and an identification code "10".
This tempo return data also does not include tempo data specifying the tempo, and all other bits are "0".
The end data is composed of a flag bit "1" and data in which all other bits are "1".

In other words, in the data format, pitch note length data is distinguished from other data by whether the flag bit is "0" or "1", and tempo specification data, tempo change data, and tempo return data are distinguished by the upper level data. They are distinguished by identification codes "00,""01," and "10," which are the contents of the second and third bits.

Data memory 3 is addressed by address counter 4 . This data memory 3 and address counter 4 are connected to its day enable terminal DIS.
and a signal output from the output terminal Q of the flip-flop 5 is applied to the reset terminal R.
Flip-flop 5 receives an initial clear signal applied to set terminal S via OR circuit OR1.
It is set by an IC (a signal that becomes "1" only for a predetermined time when the power is turned on). Therefore, data memory 3 is first rendered inactive and address counter 4 is reset.

In this state, when the start set switch 6 is turned on, the output of the start set switch 6 is differentiated by the differentiating circuit 7, and the start set signal is
It is output as SS and is applied to the reset terminal R of flip-flop 5. In response, the flip-flop 5 is reset, the data memory 3 becomes operational, and the reset of the address counter 4 is released.

In addition, the differential pulse output from the differentiating circuit 7 is sent to the address clock signal ACK via the OR circuit OR2.
CK is added to the clock input CK of the address counter 4, and the address counter 4 is advanced by one step. Address counter 4 first specifies an address in data memory 3 where tempo designation data is stored, and reads this tempo designation data from data memory 3. This tempo designation data is applied to the tempo control circuit 8. The above tempo designation data is also applied to the latch circuit 8, but since the flag bit of the tempo designation data is "1" at this time, the AND circuit A1 to which the signal obtained by inverting the contents of this flag bit by the inverter IN1 is added becomes inoperable. A signal obtained by delaying the output of the AND circuit A1 by the delay circuit 10 (strobe terminal S of the latch circuit 9)
Since the signal applied to the latch circuit 9 is “0”, the latch circuit 9
The tempo specification data is not latched.

The tempo control circuit 8 is composed of the circuit shown in FIG. Of the tempo designation data read from the data memory 3, the tempo data TD is added to the tempo data latch circuit 801. Also, the flag bit and identification code of the tempo designation data are added to the tempo designation data detection circuit 802,
If the content is "100", the tempo designation data detection circuit 802 outputs a signal "1". The output of this tempo designation data detection circuit 802 is applied to the strobe terminal of the tempo data latch circuit 801. As a result, the tempo data latch circuit 80
Tempo data TD of the tempo data designation data is latched at 1. This latched value is converted into an analog signal (voltage signal) by a digital-to-analog converter 803 and applied to the A input of a selector 805 via a manual automatic select switch 804. Here, since the signal applied to the A input select terminal SA is "1", the selector 805 selects the signal applied to the A input and sends it to the voltage controlled oscillator (VCO) via the switch 806.
807 control input C. This allows the VCO
The oscillation frequency of 807 is determined by the tempo data latch circuit 8.
It is controlled in accordance with the tempo data TD latched to 01. The signal oscillated from the VCO 807 is output as a tempo pulse TP. This tempo pulse TP determines the tempo in this embodiment, as will be described later.

Note that the manual automatic select switch 804 is for selecting the tempo set by the manual setting device 808, and when the manual automatic select switch 804 is switched to the opposite side as shown in the figure, the A input of the selector 805 is set. is added with the output of the manual setter 808, and the VCO 807 outputs a tempo pulse TP corresponding to the tempo set by the manual setter 808.

Further, the switch 806 is used to select an effect for smoothing the change in tempo when changing the tempo, as will be described later.

The output of the tempo designation data detection circuit 802 of the tempo control circuit 8 is also connected to the OR circuit OR2 (the first
Figure). The OR circuit OR2 thereby generates the address clock signal ACK, adds this address clock signal ACK to the clock input of the address counter 4, advances the address counter 4 by one step, and transfers the next data from the data memory 3, that is, the first Read out pitch note length data related to notes. Further, the address clock signal output from the OR circuit OR2 is simultaneously applied to the AND circuit A1. At this time, since the signal obtained by inverting the contents of the flag bit applied to the other input of the AND circuit A1 by the inverter IN1 is "1", the AND circuit A1 becomes operational and the signal "1" is sent to the latch circuit via the delay circuit 10. 9 strobe terminal S.
Therefore, the pitch note length data regarding the first note, which has been output from the data memory 3, is latched into the latch circuit 9.

Among the pitch note length data latched in the latch circuit 9, the key code KC indicating the pitch is stored in the display control circuit 1.
1 and the automatic performance melody sound forming circuit 12, note length data TL indicating the note length is added to the latch circuit 2.
Added to 2. However, since the output of the AND circuit A1 is applied as is (without delay) to the strobe terminal S of the latch circuit 22, the note length data TL regarding the first note latched in the latch circuit 9 is stored in the latch circuit 22 at this timing.
is not latched.

The display control circuit 11 to which the latched key code KC is added to the latch circuit 9 displays the key to be pressed (the key corresponding to the first note) on the upper keyboard 13 based on this key code.
A display lamp (not shown) is provided corresponding to each key, and the key to be pressed is indicated by lighting one of the display lamps in accordance with the output of the display control circuit 11. .

Further, the automatic performance melody sound forming circuit 12 forms a musical sound signal corresponding to the sound to be pressed (first sound) in response to the applied key code KC. The musical tone signal formed by the automatic performance melody tone forming circuit 12 is applied to the sound system 14, and is produced as a pilot tone indicating the tone to be pressed. Since this pilot sound merely indicates the sound to be pressed, it is controlled to a sufficiently low volume so as not to interfere with the melody sound based on key presses, which will be explained next.

When you press the key indicated by the indicator lamp on the upper keyboard 13 (or the key of the pilot tone being sounded from the sound system 14), the pressed key is detected by the key switch circuit 15, and the pressed key is detected by the key switch circuit 15. A key code KC ^* and a key-on signal KON (a signal that remains "1" while the key is pressed) are output. The key code KC ^* and the key-on signal KON are applied to the melody tone forming circuit 16, and a musical tone signal representing the melody tone corresponding to the pressed key is formed. The musical tone signal formed by the melody tone forming circuit 16 is applied to the sound system 14, and is produced as a melody tone.

In addition, the key code KC latched in the latch circuit 9 and the key code KC ^* corresponding to the pressed key output from the key switch circuit 15 are compared in the comparator circuit 17, and the signal obtained by inverting the matched output by the inverter IN2 is sent to the AND circuit. Added to A2. AND circuit A2 inputs the above-mentioned key-on signal to other inputs.
A signal obtained by differentiating KON with a differentiation circuit 18 is added, and if the key pressed on the upper keyboard 13 is a mistouch (different from the key indicated by the indicator lamp), the AND condition is satisfied, and the signal "1" is applied. ” is output. The output of this AND circuit A2 is applied as a trigger pulse to the one-shot circuit 19, where it is converted into a signal with a predetermined pulse width, and the light emitting diode 20
to drive. That is, if a key pressed on the upper keyboard 13 is a wrong key, the light emitting diode 20 lights up to notify the player of this.

The output of a differentiating circuit 18 for differentiating the key-on signal KON outputted from the key switch circuit 15 is applied to the set terminal of the flip-flop 21 to set the flip-flop 21 and also applied to the AND circuit A3.

The AND circuit A3 has, to its other input, a signal delayed by the delay flip-flop DF2 and inverted by the inverter IN3, which is the output of the flip-flop 21. By the way, the flip-flop 21 has its reset terminal R connected to the initial clear signal IC,
The output of the end detection circuit 37, which will be described later, and the output of the differentiating circuit 7 mentioned above are added via the OR circuit OR4, and before being set by the output of the differentiating circuit 18, the output of the differentiating circuit 7 is set. It has been reset. Therefore, the AND condition of the AND circuit A3 is satisfied only with respect to the output of the first differentiation circuit 18, and the AND circuit A3 outputs a signal "1". This signal is passed through the OR circuit OR2 to the address clock signal.
Output as ACK. This address clock signal ACK is applied to the strobe of the latch circuit 22 via the AND circuit A1 (in this case, the content of the flag bit output from the data memory 3 is "0", and the AND circuit A1 is enabled to operate). The note length data TL related to the first note, which is applied to the terminal and latched in the latch circuit 9, is transferred to the latch circuit 2.
Latch to 2.

Further, the address clock signal ACK output from the OR circuit OR2 is applied to the clock input of the address counter 4. This allows data memory 3
Pitch note length data regarding the second note is read from. This pitch note length data is latched in a latch circuit 9 by a signal obtained by delaying the address clock signal ACK in a delay circuit 10. (the key corresponding to the second note) is the upper keyboard 13
A musical tone signal that is displayed by a display lamp and indicates the next tone (second tone) to be generated is formed by the automatic performance melody tone forming circuit 12, and this tone is generated from the sound system 14 as a pilot tone. The above operation is similar to the case described above.

By setting the flip-flop 21, a signal generated from its output terminal Q is outputted as a play signal PL. The automatic performance of this embodiment is started by this play signal PL. Play signal PL
is differentiated by the differentiating circuit 23, and the flip-flop 2
4 and sets the flip-flop 24. This flip-flop 24
The output Q is the enable terminal of the rhythm counter 25.
It is added to EN to enable the rhythm counter 25.

The rhythm counter 25 receives its clock input CK.
The tempo pulse TP outputted from the tempo control circuit 8 described above is added to the tempo pulse TP, which is driven by the tempo pulse TP, and its output is applied to the rhythm pattern generation circuit 26. The rhythm pattern generation circuit 26 generates a rhythm pattern for controlling automatic rhythm performance, a chord sound generation timing signal for controlling automatic chord performance, a bass pattern for controlling automatic bass performance, and a base pattern for controlling automatic arpeggio performance. It is composed of a read-only memory (ROM) that stores arpeggio patterns and the like, and sequentially generates pattern pulses based on these patterns in accordance with the output of the rhythm counter 25.
Note that since such a rhythm pattern generation circuit is well known, detailed explanation will be omitted in this specification.

Pattern pulses based on the rhythm pattern generated by the rhythm pattern generation circuit 26 are applied to the rhythm sound formation circuit 27. Rhythm sound formation circuit 2
7 is equipped with a sound source that corresponds to various rhythm sounds,
Based on pattern pulses sequentially applied from the rhythm pattern generation circuit 26, the opening/closing control of the sound source signals output from these sound sources is performed to form musical sound signals representing rhythm sounds.

Further, pattern pulses based on other patterns generated from the rhythm pattern generation circuit 26 are applied to the accompaniment sound formation circuit 28.

The accompaniment sound forming circuit 28 receives the output of the key switch circuit 30 that detects keys pressed on the lower keyboard 29 and the output of the key switch circuit 32 that detects keys pressed on the pedal keyboard 31, and receives outputs from the rhythm pattern generation circuit 26. Based on the various pattern pulses generated, musical tone signals representing accompaniment tones such as chord tones, bass tones, arpeggio tones, etc. are formed. Note that various well-known circuits can be used as the rhythm sound forming circuit 27 and the accompaniment sound forming circuit 28.

A musical tone signal indicating the rhythm tone formed by the rhythm tone forming circuit 27 and a musical tone signal indicating the chord tone, bass tone, arpeggio tone, etc. formed by the accompaniment tone forming circuit 28 are added to the sound system 14, and the musical tone signal indicating the rhythm tone formed by the accompaniment tone forming circuit 28 is added to the sound system 14, and the automatic accompaniment performance tone is generated. pronounced as Furthermore, switch 3
6 is turned on, the flip-flop 24 is reset, the rhythm counter 25 becomes inactive, and the automatic accompaniment performance is stopped.

Further, the tempo pulse generated from the tempo control circuit 8 is applied to the clock input CK of the counter 33. The counter 33 has its reset terminal connected to the output of the AND circuit A1, and is first reset at the output of the AND circuit A1, that is, at the timing of pressing the first note, and sequentially counts tempo pulses TP. This count value is added to the B input of the comparison circuit 34.

The comparison circuit 34 has the output of the latch 22 (note length data TL regarding the first note) added to the A input, and compares the value added to the A input with the count value of the counter 33 added to the B input. . In this comparison, the count value of the counter 33 reaches the note length data latched in the latch circuit 22,
When A=B holds true, the comparator circuit 34 generates a match output. This coincidence output is differentiated by a differentiating circuit 35, and the output of the flip-flop 21 (play signal
PL) is applied to the OR circuit OR2 via the AND circuit A4, which is operable by the clock signal PL, to generate the address clock signal ACK. This address clock signal ACK is applied to the strobe terminal S of the latch circuit 22 via the AND circuit A1, and latches the note length data TL related to the second note latched in the latch circuit 9 to the latch circuit 22. It is added to the clock input of the address counter 4, advances the address counter 4 by one step, and the same operation is repeated thereafter.

That is, when the key related to the first note is pressed on the upper keyboard 13, the flip-flop 21 is set;
A play signal PL is generated, thereby starting automatic performance of the accompaniment sound. Further, when the key associated with the first note is pressed, the address counter 4 is advanced, and the pitch note length data regarding the second note is read out from the data memory 3. Then, when the count value of the counter 33 for counting tempo pulses TP reaches the value latched in the note length data TL latch circuit 22 related to the second note, the address counter 4 is advanced and the note length data related to the third note is read from the data memory 3. The high note length data is read out, and thereafter, each time the count value of the counter 33 reaches the note length data TL latched in the latch circuit 22, the address counter 4 is incremented to proceed with automatic performance.

By the way, as mentioned above, in the data format stored in the data memory 3, tempo change data is stored at the start point of a difficult part etc. where the tempo is to be changed (slowed down), and tempo change data is stored at the end point (return to the original tempo). The tempo return data is stored at the return point).

If the tempo change data is now read out from the data memory 3, this tempo change data is applied to the tempo control circuit 8. At this time, since the content of the flag bit of the tempo change data is "1", the AND circuit A1 becomes inactive,
The tempo change data is not latched in the latch circuit 9.

The tempo change data added to the tempo control circuit 8 is sent to the tempo change detection circuit 81 of the tempo control circuit 8.
0 (FIG. 3). That is, if the content of the upper three bits of the added data is "101", the tempo change detection circuit 810 detects this as tempo change data and outputs a signal "1" to the output terminal T1. This signal is applied to the set terminal S of flip-flop 811 to set flip-flop 811. flip flop 81
The set output Q of 1 is applied to the B input select terminal SB of the selector 805 via the switch 812.

Incidentally, a signal obtained by lowering the level of the output of the digital-to-analog converter 803 by a predetermined value using a variable resistor 813 is applied to the B input of the selector 805. Therefore, in this case, selector 8
At step 05, the level-down signal is selected and applied to the control input C of the VCO 807 via the switch 806. As a result, the frequency of the tempo TP oscillated from the VCO 807 becomes lower, and the tempo becomes slower. At this time, if the switch 806 is set to the opposite side as shown in the figure, the level-down signal is applied to the control input C of the VCO 807 via the integrating circuit 809, and the tempo changes smoothly according to the integral characteristic of the integrating circuit 809. do.

In addition, the output terminal T1 of the tempo change detection circuit 810
The signals output from are OR circuits OR5, OR3,
The OR circuit OR2 (FIG. 1) is added to the clock input of the address counter 4 as the address clock signal ACK through the delay flip-flop DF1, thereby advancing the address counter 4 by one step. Subsequent pitch note length data is read from , and the automatic performance continues. However, since the frequency of the tempo pulse TP is lowered by the level down caused by the variable resistor 813 mentioned above, the tempo of the automatic performance becomes slower.

In this state, when tempo return data is read from the data memory, this tempo return data is applied to the tempo control circuit 8. In this case as well, since the content of the flag bit of the tempo return data is "1", the AND circuit A1 is inactive and the latch circuit 9 does not latch this tempo return data.

The tempo return data added to the tempo control circuit 8 is sent to the tempo change detection circuit 81 of the tempo control circuit 8.
Detected by 0. That is, if the content of the upper three bits of the added data is "110", the tempo change detection circuit 810 detects this as tempo return data and outputs a signal "1" to the output terminal T2. This signal is applied to the reset terminal R of the flip-flop 811 via an OR circuit OR6 which takes an OR condition with the start set signal SS, and resets the flip-flop 811. As a result, the output Q of the flip-flop 811 becomes "0" and the signal applied to the A input select terminal SA of the selector 805 becomes "1", so the selector 805 selects the output of the digital-to-analog converter 803 that is applied to the A input. This is then applied to control input C of VCO 807 via switch 806. Therefore, the tempo pulse output from VCO807
TP returns to its original frequency. In this case as well, if the switch 806 is switched to the opposite side from that shown in the figure, it will return smoothly according to the integration characteristics of the integration circuit 809.

Also, the output terminal T2 of the tempo change detection circuit 810
The signals output from are OR circuits OR5, OR3,
It is applied to the OR circuit OR2 (FIG. 1) via the delay flip-flop DF1, and is applied to the clock input of the address counter 4 as the address clock signal ACK, thereby advancing the address counter 4 by one step. As a result, the following pitch note length data is read out from the data memory 3, and automatic performance is performed according to the restored tempo.

It should be noted that if the switch 812 of the tempo control circuit 8 is off, the selector 805 cannot be switched in accordance with the operation of the flip-flop 811, so the above effect is not provided.

When the end data is read out from the data memory 3 due to the end of the automatic performance, this end data is detected by the end detection circuit 37. The output of this end detection circuit 37 is OR circuit OR1, OR4.
are applied to the set terminal of flip-flop 5 and the reset terminal of flip-flop 21, respectively. When flip-flop 5 is set, data memory 3 becomes inactive, address counter 4 is reset, and when flip-flop 21 is reset, play signal PL becomes "0".

FIG. 4 shows another example of the configuration of the tempo control circuit 8 shown in FIG. 1. In this case, in the data format stored in the data memory 3, the data regarding the tempo consists only of tempo designation data. To explain this with respect to the case shown in FIG. 2, tempo change data and tempo return data both use tempo designation data. In other words, the upper three bits of the tempo change data and tempo return data are both “100”,
Its contents are not all "0", but tempo data TD corresponding to the tempo to be changed and tempo data TD corresponding to the tempo to be restored.

That is, in the circuit shown in FIG. 4, a tempo is formed corresponding to each tempo designation data, and the tempo is controlled to change.

The upper three bits of the data read from the data memory 3 (FIG. 1) are applied to a tempo designation data detection circuit 813, and the other bits are applied to a tempo data latch circuit 814. The tempo designation data detection circuit 813 detects the contents of the upper 3 bits, and if this is "100", it is regarded as tempo designation data and outputs a signal "1". The output of this tempo designation data detection circuit 813 is applied to a strobe terminal of a tempo data latch circuit 814. As a result, the tempo data TD of the tempo designation data is latched in the tempo data latch circuit. This tempo data TD is converted into an analog signal (voltage signal) by a digital-to-analog converter 815, resistance-mixed with a voltage set by a variable resistor 816 for manual correction, and then sent to a voltage-controlled oscillator via an integrating circuit 817. (VCO)81
8 control inputs. Therefore, VCO8
The oscillation frequency of 18 is determined by the tempo data latch circuit 81.
It is determined according to the tempo data TD latched at 4 and the output of the variable resistor 816 for manual correction. The output of this VCO818 is tempo pulse TP
is output as In addition, the output of the tempo designation data detection circuit 813 is a Tayray flip-flop DF.
3 to the OR circuit OR2 (FIG. 1), and is used to advance the address counter 4 by one step.

That is, in the circuit shown in FIG. 4, the latch contents of the tempo data latch circuit 814 are rewritten every time new tempo designation data is added, and the tempo pulse output from the VCO 818 is thereby rewritten.
The frequency of TP is changed and controlled.

In this case, the contents of the data format only need to include tempo specification data, pitch note length data, and end data, so data identification control can be performed even if only flag bits are provided without using the upper three bits as in the above embodiment. It is possible.

As explained above, according to the present invention, the tempo can be automatically changed and controlled depending on the performance location, so for example, during practice, it is possible to easily follow the tempo and perform, and the tempo A favorable performance effect can also be obtained by changing the .

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a diagram showing an example of a data format used in the same embodiment, and FIG. 3 is a block diagram showing an example of a tempo control circuit in the same embodiment. , FIG. 4 is a block diagram showing another embodiment of the same tempo control circuit. DESCRIPTION OF SYMBOLS 1...Score, 1a...Magnetic tape, 2...Score data reading device, 3...Data memory, 4...Address counter, 8...Tempo control circuit, 11...
... Display control circuit, 12 ... Automatic performance melody sound formation circuit, 13 ... Upper keyboard, 14 ... Sound system, 16 ... Melody sound formation circuit, 25 ... Rhythm counter, 26 ... Rhythm pattern generation circuit, 27 ... Rhythm sound formation circuit, 28 ... Accompaniment sound formation circuit, 29 ... Lower keyboard, 31 ... Pedal keyboard, 33 ... Counter, 34 ... Comparison circuit, 80
1,814...tempo data latch circuit, 80
2,813...Tempo specification data detection circuit, 80
5...Selector, 809, 817...Integrator circuit,
807, 818...voltage controlled oscillator, 810...
...Tempo change detection circuit.

Claims (1)

[Scope of Claims] 1. In an automatic performance device that sequentially reads out musical tone data stored in accordance with the order of performance progress and performs an automatic performance according to the read data, the musical tone data is stored in correspondence with the musical tone data. An automatic performance device equipped with a tempo control circuit that automatically changes and controls the tempo according to tempo change information provided. 2. The tempo change information includes changed tempo start information and tempo return information, and the tempo control circuit changes the tempo using the changed tempo start information and controls the tempo to return to the original tempo using the tempo return information. An automatic performance device according to claim 1. 3. The automatic performance device according to claim 2, wherein the tempo change and return are performed smoothly according to integral characteristics. 4. The automatic performance apparatus according to claim 1, wherein the tempo change information includes changed tempo information, and the tempo control circuit controls the tempo to be changed to a tempo specified by the changed tempo information.