JPS5823437U - logic circuit - Google Patents
logic circuitInfo
- Publication number
- JPS5823437U JPS5823437U JP8612482U JP8612482U JPS5823437U JP S5823437 U JPS5823437 U JP S5823437U JP 8612482 U JP8612482 U JP 8612482U JP 8612482 U JP8612482 U JP 8612482U JP S5823437 U JPS5823437 U JP S5823437U
- Authority
- JP
- Japan
- Prior art keywords
- fet
- logic circuit
- parallel
- bias source
- input signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Logic Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来の論理回路を示す回路図、第２図−は本考
案に係る一実施例の論理回路を示す回路図、第３図は本
考案に係る他の実施例の論理回路を示す回路図、第４図
は本考案の論理回路を適用した出力ドライバー回路を示
す回路図、第５図、第６図は本考案に対するさらに他の
実施例を示す図である。
２１・・・・・・論理部、”ＳＳ、 ■Ｉ］）・・・・
・・バイアス源、Ｑ２ｂ Ｑ２２・・・・・・エンハン
スメント型ＦＥＴ（Ｅ−ＦＥＴ）、Ｑ、、３＋ Ｑ２４
・・・・・・デプリーション型ｒ”ＥＴ（Ｄ−ＦＥＴ）
、Ａ、 Ｂ・・・・・・入力信号、八、■・・・・・・
入力信号Ａ、 Ｂの補数信号。FIG. 1 is a circuit diagram showing a conventional logic circuit, FIG. 2 is a circuit diagram showing a logic circuit of an embodiment of the present invention, and FIG. 3 is a circuit diagram of another embodiment of the logic circuit of the present invention. FIG. 4 is a circuit diagram showing an output driver circuit to which the logic circuit of the present invention is applied, and FIGS. 5 and 6 are diagrams showing still other embodiments of the present invention. 21...Logic section, "SS, ■I])...
...Bias source, Q2b Q22...Enhancement type FET (E-FET), Q, 3+ Q24
・・・・・・Depletion type r”ET (D-FET)
, A, B... Input signal, 8, ■...
Complement signal of input signals A and B.
Claims (1)
ＥＴを直列接続し、他方のバイアス源と上記出力端との
間に上記第１のＦＥＴと同数でかつ同チャンネル型の第
２のＦＥＴを並列接続し、且つ上記第１のＦＥＴ及び上
記第２０ＦＥＴのいずれか一方を、入力信号をゲート入
力とするエンノ・ンスメント型ＦＥＴで構成し、他方を
Ｌ記入力信号の補数信号をゲート入力とするデプレッシ
ョン型ＦＥＴで構成してなり、Ｌ記補数信号の状態に応
答して上記デプレッション型ＦＥＴのインピーダンス状
態を変化せしめてなることを特徴とする論理回路。A plurality of first F is connected between one bias source and the output end.
ETs are connected in series, and second FETs having the same number and the same channel type as the first FET are connected in parallel between the other bias source and the output terminal, and the first FET and the 20th FET are connected in parallel. One of them is configured with an enhancement type FET that uses the input signal as a gate input, and the other is configured with a depletion type FET that uses the complement signal of the L input signal as the gate input. A logic circuit characterized in that the impedance state of the depletion type FET is changed in response to a state.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8612482U JPS5823437U (en) | 1982-06-11 | 1982-06-11 | logic circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8612482U JPS5823437U (en) | 1982-06-11 | 1982-06-11 | logic circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5823437U true JPS5823437U (en) | 1983-02-14 |
Family
ID=29881359
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8612482U Pending JPS5823437U (en) | 1982-06-11 | 1982-06-11 | logic circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5823437U (en) |
-
1982
- 1982-06-11 JP JP8612482U patent/JPS5823437U/en active Pending
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