JPS5822974A - Large scale integration testing device - Google Patents

Abstract

PURPOSE:To prevent an overcurrent from flowing into and out of an output line of a testing device, by selectively inserting a current limiting circuit. CONSTITUTION:In accordance with an input request synchronizing with a clock to an LSI device 1 to be measured, a tester outputting circuit outputs a data input signal B onto a bus line 4. In this case, when a time shift is generated between an input/output state of an input/output terminal D of the device 1, and an input and an output are overlapped, a relay is driven and a contact 5 is opened. As a result, a resistance RM is placed between a tester and the device 1, a current limiting circuit is selected, and it is prevented that an overcurrent flows into the device 1. In the same way, it is also prevented that the overcurrent flows out to the tester, and a function test is executed with safety and reliability.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an L8I test device that performs a functional test on an L8I (large scale integrated circuit).

Figure 1 shows a general LSI test device. LSI 1, such as a microprocessor, has input terminals for clock, reset, etc., and a write straw! In addition to output terminals such as , read stroke, and address latch enable, it has a common terminal that shares input/output with address or data out and instruction or data in. The input/output terminal of the former is connected to the funx tester 2 via the control twin 3, and the common terminal of the latter is connected to the funxy tester 2 via the pass line 4. and,
Transferring LSI 1, which is the device under test, to tester 2.

When performing a digital test, the address or data output mode (low impedance) and data input mode (high impedance) are clearly defined for each test cycle in the pass line 4, as shown in FIG. While in this data input mode, a predetermined data signal is output from the tester 2 through the tester output line including the pass line 4.
A functional test based on this data is performed at SI7 and ζ. Next, when the data output mode is entered, the test result data of this LSI 1 is output to the tester 2 side through the pass line 4, and the tester 2 compares this result data with preset data to determine whether its function is normal. A good/bad judgment is made as to whether the product is good or bad.

FIG. 3 shows details of the output circuit on the tester 2 side, and FIG. 4 is a time chart for explaining the circuit operation of FIG. 3. A more detailed explanation will be given with reference to these. Positive power supply■
A resistor R and N-type transistors Q1 to Q are connected between and the negative power supply e.
s, a P-type transistor Q4, and a resistor R are connected in sequence, and the data input signal B is supplied to the pace of the transistor Ql*Q4 through the resistor R, respectively, and the data input signal B is supplied to the pace of the transistor Qs e Qs through the resistor R, respectively. A tester input/output control signal A is supplied. Furthermore, the positive and negative power supplies (2) and (e) are each connected to the tester output terminal C via a high resistance RH, and
The interconnection point of the transistors Q*Qs is connected to the tester output terminal C.

In the above circuit, as shown in FIG. 4, the address signal synchronized by the black input is outputted to the input/output terminal of the device under test LSI 1 through the path line 4. Thereafter, the device under test 1 requests the tester 2 for the data input signal B, so the tester 2 sends the tester output C shown in the figure to the device 1. Here, when the device under test l is in the output mode, the input/output control signal A in the tester 2 is not a negative voltage, and the transistor Qz*Qs is in the off state, so its output terminal C
becomes a high impedance state. Furthermore, when device 1 is in the input mode, the input/output control signal A is at a positive voltage and the transistors Qs*Qm are off, so if the data input signal B is at a positive voltage, the transistor Q1 is turned on and passes. A positive voltage is applied on line 4. Conversely, if the data input signal B is a negative voltage, the transistor Q4 is turned on and a negative voltage is applied to the pass line 4.

Here, if there is a time difference between the input/output status of the input/output terminal of the device under test 1 and the input/output control signal of the tester 2, as shown in FIG. The output signal from the device 1 and the output signal from the device 1 overlap each other 9, creating an input/output overlap location. For example, when the output signal from the input/output terminal of device 1 is 4V and the output signal from tester 2 is Ov, the output current from the terminal passes through path line 4 to the tester at this overlapped point. An excessive current flows into output terminal C of No. 2.

Conversely, when the output signal of tester 2 is 4■ and the output signal from device 1 is Ov, the output current from tester 2 flows into the input/output terminal of device 1 as an excessive current through pass line/4. . This does not have a harmful effect on the device under test 1, but also causes the inconvenience that a reliable function test cannot be performed.

Therefore, if an attempt is made to improve this effect by increasing the output impedance of the tester 2, a delay will occur in the tester output waveform when performing a high-speed test, resulting in inconvenience in the functional test.

The present invention has been made in view of the above circumstances, and
The test equipment output line connected to the input/output common terminal of the SI device has a configuration in which a current limiting circuit can be selectively inserted to prevent excessive current from flowing in and out, and the current limiting circuit is configured to be able to be inserted selectively into the test equipment output line connected to the input/output common terminal of the SI device. An object of the present invention is to provide an LSI test device that can perform safe and reliable function tests by preventing excessive current from flowing into and out of devices.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. FIG. 5 shows an LSI testing apparatus of the present invention, and the same symbols are used to describe the same parts as the circuits described above. In the output circuit of tester 2, the positive and negative power supplies ■, ef! lKa low resistance RL% N-type transistors Q1 to QS, P-type transistor Q4 and low resistance RL are connected in sequence, and the pace of transistor Q1eQa is connected to a pace resistor Rb.
A data input signal B is supplied through the transistor Q.
An input/output control signal is supplied to each pace of t*Qs through a pace resistor Rb. Further, the positive and negative power supplies (2) and (theta) are connected to the output terminal C of the tester 2 via high resistances R, respectively. Furthermore, in the present invention, the output terminal C of the tester 2 and the transistor Q are connected in series with the tester output line.

A normally closed contact 5 of the relay and a current limiting circuit, for example, a medium resistance RM of about Ω are inserted in parallel between the mutual contacts of Qs.

According to the above circuit, as shown in FIG. 6, the address signal synchronized by the clock input is outputted to the input/output common terminal of the device under test 1 through the path line 4. Thereafter, the device under test 1 requests the tester 2 for the data input signal B, so the tester 2 sends the tester output C to the device 1 as shown in the figure.

Here, when the device under test 1 is in the output mode, the input/output control signal A in the tester 2 is a negative voltage, and the transistor Q is connected.

Since Qs is in an off state, its output terminal C is in a high impedance state. Furthermore, when the device 1 is in the input mode, the input/output control signal Ad is not at a positive voltage and the transistor QleQ3 is turned on, so if the data input signal B is at a positive voltage, the transistor Q1 is turned on and the pass line 4 is turned on. A positive voltage is applied to the top. On the contrary,
If the data input signal B is a negative voltage, the transistor Q4 is turned on and a negative voltage is applied to the pass line 4.

Here, if there is a time difference between the input/output status of the input/output terminal of the device under test 1 and the input/output control signal A of the tester 2, that is, the output signal from the device 1 and the output signal from the tester 2 If a time lag occurs between the output signal of When set, K operates to prevent excessive current from flowing into or out of device I. In other words,
This circuit can prevent excessive current from flowing in and out of device 1 without being affected by the time lag of input/output control signals, and prevents destruction of device 1 or tester 2 due to excessive current, thereby increasing safety and reliability. It is possible to carry out certain func- tion tests. Note that other switch elements may be used in place of the relay contact 5.

As explained above, according to the present invention, it is possible to selectively insert a current limiting circuit to prevent the inflow and outflow of excessive current into the test equipment output line connected to the input/output common terminal of the LSI device under test. By using this configuration, it is not affected by the time lag of input/output control signals.
LS that prevents excessive current from flowing into and out of the device and allows safe and reliable functy testing.
I test equipment can be provided.

[Brief explanation of drawings]

Figure 1 is a configuration diagram of a test equipment for measuring general L8I devices, Figure 2 is a time chart for explaining the operation of the equipment shown in Figure 1, Figure 3 is a conventional example of the test equipment shown in Figure 1. FIG. 4 is a time chart for explaining the operation of FIG. 3, and FIG. 5 is an LS according to an embodiment of the present invention.
FIG. 6 is a circuit diagram showing the I test device, and is a time chart for explaining the operation of the device shown in FIG. 1-・LSI device under test, 1-・Tester, 3...
Control line, 4...Pass line, 5...Relay, Q1
~Q4...Transistor, RH...High resistance, RL・
...Low resistance, RM...Medium resistance, Rb...Base resistance, A...I/O control signal, B...Data input signal, C...Tester output, D...Device input/output Common terminal, ■, e...Power supply.

Claims (2)

[Claims] (1) An L8I test device characterized in that it is configured such that a current limiting circuit is selectively inserted into a test device output line connected to an input/output common terminal of the L8I to be measured. (2) The current limiting circuit has a period in which the test signal is supplied from the test equipment output line side to the input/output terminal of L8I, and
2. The LSI testing device according to claim 1, wherein the JI is inserted into the output line during a period that overlaps with a period in which an output signal is output to an input/output terminal.