JPS63103988A - Testing device for semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To enable a test with the level sensitive scan design of a semiconductor circuit by arranging an exclusive NOR gate in front of a latch circuit in shift register constitution. CONSTITUTION:An AND gate 13 is arranged in front of a latch 12 in a test unit 11 and the clock of the latch 12 is controlled through the control line of the gate 13. Even when data is sent to the latch 12, the gate 13 does not turn on, so no data is inputted. When the output of the test unit 11 is observed, the inversion of an expected output is inputted previously to the latch circuit 6 of the shift register constitution. Then a circuit 15 is arranged in front of the clock of the circuit 6, and while the output of the test unit 11 is supplied to one input of the circuit 15, the output of the circuit 6 is supplied to the other input; when the output of the test unit 11 reaches the expected value, the value of the circuit 6 is rewritten into the expected output value and observed. Therefore, even if a fault occurs in the test unit 11 and the expected output is not outputted, the value of the circuit 6 is not rewritten, so the fault can be detected.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit testing device for easily testing semiconductor integrated circuits.

[Conventional technology]

Conventionally, level sensitive tape scan design (hereinafter abbreviated as LSSD) for synchronous circuits has been constructed using two design methods. One of them, level sensitive, normalizes variations in AC characteristics, and consists of a latch circuit using a multiphase clock. Also, another one
In the two scan designs, the latch is configured with a serial shift register so that an arbitrary value can be set from an external terminal to a memory element within the LSI (in this case, it is considered to be a memory element), or the result can be observed. Consists of design methods.

FIG. 2 is a block diagram showing a conventional semiconductor integrated circuit testing device. In the figure, 1 is a primary input, 2 is a shift-in terminal, 3 is a clock A, 4 is a clock B, 5 is a system clock, and 6 is a shift-in terminal. is a latch circuit having a shift register configuration (hereinafter abbreviated as SRL), 7 is a shift mode, 8 is a test unit, 9 is a test pattern generator, and 10 is a comparator, and the circuit to be tested uses the launch. It can be used as a test unit and divided into sequential circuits.

Next, the operation will be explained.

First, an initial value is set for primary input 1. And 5
The mode of RL6 is switched by shift mode 7, and then a test pattern is set from shift-in terminal 2. Among them, the shift clocks are inputted in the order of clock A4 and clock B5, and values are set in 5RL6. Then, switch the operating mode of 5RL6 from shift mode to normal mode, input system clock 5, and
Import data into L6. Switch the mode of 5RL6 from normal mode to shift mode again, and clock B5,
Input the shift clock of clock A4 in order, 5RL6
Get the value of. By comparing the data thus obtained with the expected output value, it is determined whether the test unit 8 is out of order.

[Problem that the invention seeks to solve]

Conventional semiconductor integrated circuit test equipment is configured as described above, so when testing a semiconductor integrated circuit with an LSSD, data is sent to the test unit 8 while a value is set in 5RL6, and the test unit Since there is a risk that the internal state of the latch in test unit 8 may change, synchronous circuits prevent this by controlling the clock of the latch in test unit 8, but the same cannot be done with asynchronous circuits. Moreover, there were problems such as the timing not being able to be obtained when outputting from the test unit 8 to 5RL6.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a semiconductor integrated circuit testing device capable of testing a semiconductor integrated circuit using an LSSD.

[Means for solving problems]

A semiconductor integrated circuit testing device according to the present invention includes an AND gate provided at the front stage of a test unit and a clock stage of a latch circuit having a shift register configuration, in order to test an asynchronous circuit by scan design, and the test unit It consists of a two-input exclusive gate that observes the output from the gate.

[Effect]

The semiconductor integrated circuit testing device according to the present invention prevents the data in the memory element from being changed inadvertently by disposing an AND gate in the front stage of the test unit, and also prevents the data in the memory element from being changed inadvertently. An exclusive NOR gate is placed before a latch circuit having a register configuration so that observation can be performed when data from the test unit is output.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.
Components in the figure that are the same as those in FIG. 2 are given the same reference numerals, and their explanations will be omitted. In the figure, 11 is a test unit which is a circuit to test, 12 is a latch, and 13 is an input AND gate. has been done. 15 is a 2-input exclusive NOR circuit (hereinafter abbreviated as XNOR gate) arranged at the clock input terminal of 5RL6 on the output side. It is configured such that the output from 5RL6 is input.

Next, the operation will be explained.

With conventional test equipment, when testing an asynchronous circuit with LSSD, there was a possibility that the latch data in the test unit would be rewritten while the latch data was storing the signal in 5RL6. In the device, test unit 11
An AND gate 13 is arranged before the latch 12 in the middle, and the wiring that controls the AND gate 13 connects the latch 12.
Since the AND gate 13 is not turned on even when data is sent to the latch 12, data does not inadvertently flow in.

Also, when observing the output from test unit 11, 5
Input the inversion of the expected output into RL6 in advance, and then
An XNOR gate 15 is arranged before the clock of the test unit 11, and one input of the XNOR gate 15 receives the output from the test unit 11, and the other input receives the output from the 5RL6. When the output from 5RL6 reaches the expected value, observation can be made by rewriting the value of 5RL6 to the expected output value. Therefore, even if a failure occurs in the test unit 11 and the expected output is not output, 5RL6
Since the value of is not rewritten, it is possible to detect a failure.

〔Effect of the invention〕

As described above, according to the present invention, in order to test an asynchronous circuit using a scan design, a semiconductor integrated circuit testing device has an AND gate provided in the front stage of a test unit, and a clock gate in a latch circuit having a shift register configuration. Since it is configured with a 2-input exclusive NOR gate that observes the output from the test unit, it is possible to test asynchronous semiconductor integrated circuits with LSSD, making testing easier and improving product reliability. The benefits include improved performance, lower test costs, and a shorter development period.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a semiconductor integrated circuit testing device according to an embodiment of the present invention, and FIG. 2 is a professional diagram showing an example of a conventional semiconductor integrated circuit testing device. 6 is a latch circuit (SRL), 11 is a test unit, 12
is a latch, 13 is an AND gate, and 15 is a 2-input exclusive gate. Note that the same reference numerals in the figures indicate the same or corresponding parts. Fig. 1 2 = Shift-in block 6: 5RL 11 nearest single to 12: U, + 13: 2 input AND gate 14: AND control slave 15: 2 input XNOR '7'-to Fig. 2

Claims (1)

[Claims] In a semiconductor integrated circuit testing device that applies an input signal to a test unit and compares the correctness of the response output with an expected value, the test is performed before the test unit in order to test an asynchronous circuit using scan design. 2, which is equipped with a two-input AND gate that prevents the value of the memory element in the unit from changing inadvertently, and which observes the output from the test unit before the clock of a latch circuit having a shift register configuration.
A semiconductor integrated circuit testing device characterized by being equipped with an input exclusive NOR gate.