JPS58225641A - キヤステイングモ−ルド製造法 - Google Patents
キヤステイングモ−ルド製造法Info
- Publication number
- JPS58225641A JPS58225641A JP57107804A JP10780482A JPS58225641A JP S58225641 A JPS58225641 A JP S58225641A JP 57107804 A JP57107804 A JP 57107804A JP 10780482 A JP10780482 A JP 10780482A JP S58225641 A JPS58225641 A JP S58225641A
- Authority
- JP
- Japan
- Prior art keywords
- casting
- lead frame
- case
- casting mold
- protrusion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/01—Manufacture or treatment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57107804A JPS58225641A (ja) | 1982-06-23 | 1982-06-23 | キヤステイングモ−ルド製造法 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57107804A JPS58225641A (ja) | 1982-06-23 | 1982-06-23 | キヤステイングモ−ルド製造法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58225641A true JPS58225641A (ja) | 1983-12-27 |
| JPS6322611B2 JPS6322611B2 (https=) | 1988-05-12 |
Family
ID=14468451
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57107804A Granted JPS58225641A (ja) | 1982-06-23 | 1982-06-23 | キヤステイングモ−ルド製造法 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58225641A (https=) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01107152U (https=) * | 1988-01-12 | 1989-07-19 |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5270766A (en) * | 1975-12-10 | 1977-06-13 | Toshiba Corp | Semiconductor device |
-
1982
- 1982-06-23 JP JP57107804A patent/JPS58225641A/ja active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5270766A (en) * | 1975-12-10 | 1977-06-13 | Toshiba Corp | Semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01107152U (https=) * | 1988-01-12 | 1989-07-19 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6322611B2 (https=) | 1988-05-12 |
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