JPS58222621A - Counter - Google Patents

Abstract

PURPOSE:To attain measurement with good accuracy even for a short measuring period, by changing the polarity of a clock inputted to a counter depending on the polarity of a reference clock at the start of count. CONSTITUTION:A count starting signal is inputted to a terminal 7 to reset T FFs 14, 15 constituting the counter, and inputted to a T input of a D FF9 to latch the state of a reference clock input terminal 8 in this state. As a result, either of NAND gates 11, 12 is activated. For example, when the state of the terminal 8 is ''H'', the NAND gate 11 is activated. Thus, the reference clock is inverted finally via an inverter 10, the NAND gate 11 and an NAND gate 13 from the input terminal 8 and inputted to the counter. Inversely, when the input terminal 8 is ''L'' at the start of count, the clock is inputted finally to the counter with the original polarity via the NAND gates 12 and 13. Thus, the error of measuring period is suppressed within a half period of the reference clock.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a counter, and more particularly to a counter suitable for accurately counting four waveforms input within a short cycle period.

In conventional counters, especially when the measurement period is short, a large error occurs in the measurement time depending on the phase relationship between the measurement start and the reference clock. The configuration of a conventional counter is shown in FIG. Further, FIG. 2 shows a time chart when the measurement start timing and the phase relationship between the four reference points are different. 1st
In the figure, 1 and 2 are T-flips that operate based on the timing of the clock.
This is a flop (hereinafter abbreviated as IFF). Also, in Figure 2, 5
1f1 reference clock, Q output waveform of 4 TFF1, 5
The Q output waveform of fdrFF2, 6 is the reset pulse of TFF1, 2.

Let's explain the operation. In the initial state (to), TFFl2
It is fixed at %Ll by the reset pulse (waveform 6). Therefore, even if the reference standard 4-3 is input, TFFl, 2
status remains unchanged. Next, reset pulse <rs, form 6
) (#x). The counter starts working. T
FFl inverts its output at the rising edge of the reference clock 3, and the Q output changes to %ill (tl). Next, when the reference clock 5 rises, the Q output of TFF1 changes to %(, I, that is, Q changes to %fil.

(t3) Then, TFF2 is inverted to -Bl.

Furthermore, at t4, reset input is input to TFF1 and 2) %
Fall to LI. Thereafter, similar operations are performed from t7 to t8. ,
Here, the measurement period is from the falling edge of waveform 6 to the rising edge of the TFF2Q output. Then, the measurement period is approximately one cycle (1K) of the reference clock 5 in state A of FIG. 2, which is the minimum value of the measurement period. In state B, the reference clock 3'v) is about 2 cycles (T), which is the maximum accuracy of the measurement period.The error is about 1 cycle, which is caused by the problem.In order to solve this problem, the reference clock 5'v) Increasing the frequency can also be considered, but this often has the disadvantage of increasing the price.

An object of the present invention is to provide and provide a counter that can measure accurately even during a short measurement period.

In order to achieve the above object, the present invention changes the polarity of the clock input to the counter depending on the polarity of the reference clock at the start of counting.

An embodiment of the present invention will be explained below with reference to FIGS. 5 and 4. FIG. 3 is a specific circuit diagram, and FIG. 4 is an explanatory diagram of the operation when the phase relationship between the measurement start timing and the reference clock is different. In FIG. 5, 7 is a Vi reset input terminal, 8 is a reference clock input terminal, 9 is a D flip-flop (hereinafter abbreviated as DFF), and 10 is an inverter. 11,1
2°13 is a Nant gate, and 14.15 is a TFF.

In Figure 4, 16 is the reference clock, 17 is the TFF 14.1
5 is the reset pulse and the trigger pulse of DFF 9, and 18 is the Q output of DFF q. 19ijTFF
14 clock inputs, 20 TF7”14 Q outputs, 2
1 is the Q output of TF7''15.

Let's explain the operation. This counter shows the fall of waveform 17! Measurement starts at 0 (tl). At the same time, this pulse (waveform 17) operates DFF 9, and the information on D input (
Waveform 16) That is, at this time (tl), %B is outputted to the Q output, and waveform 18 is obtained. The Q output of DFF 9 is %LI・
It is. Therefore, the Nant gate 11 side connected to Q is active, and the reference clock 19 is connected from the input terminal 8 to the inverter 10,
Nando Game) 11.15 via TFFl4 T
transmitted to the input. Therefore, the input to 'I'FF1a becomes waveform 22. The waveform 22 of TFF14,15 is subjected to the above-mentioned frequency division to obtain waveform 20.21. Here, the measurement period is waveform 1
The rising of the Q output of TFFl5 from the falling of 7 is #
) f and (41 to 2g), then 1 of the reference clock 16
．． This is the maximum value for 5 cycles. State A has been explained above. Next, waveform 17 %fil (i3) TFF
14 and 15 are reset and their Q outputs become %L# (waveforms 20 and 21). Furthermore, the waveform changes to 17Ll (t4), so the counter starts counting.

At this time, the waveform 17 DFF 9''k is operated as described above, and the information on the D input <e, form 16), that is, %Ll, is output to Q. Therefore, the reference clock 16 is transmitted from the terminal 11 via the synand gate 12.15. The T input waveform of TFlla becomes waveform 19. This is frequency-divided by TFFl7.18 to obtain waveforms 20 and 21. At this time, the measurement period is from t4 to ts, and is approximately one cycle of the reference clock 16. This is the minimum value of the measurement period. State B has been described above.

As explained above, according to this embodiment, the measurement period error can be suppressed to within a half period of the reference clock 16, and the same effect as when the reference clock frequency is doubled isometrically can be obtained. In the above embodiments, the configuration of the counter has been explained by exemplifying the counter shown in FIG. 1, but it goes without saying that the present invention can be applied to counters with other configurations.

Next, an application/column in which the present invention is applied to noiseless slow reproduction using intermittent capstan driving in a magnetic recording/reproducing device will be explained. FIG. 5 shows a block diagram of an application example, and FIG. 6 shows an explanatory diagram of its operation. In Fig. 5, 22 is a capstan motor, and 23 is a frequency generator (Frequency generator).
Generator) Coil (abbreviated as FG coil)
, 24 is an FG amplifier. 25 is a frequency-voltage converter, 26 is a DC multiplier, 27-digit quasi-magnetic pressure source, 28 is a motor drive amplifier, 29 is an intermittent drive signal generator, and 50 is an acceleration device using the counter of the present invention. A pulse generator, 51 is a diode, 52 is a resistor, and 0.55 is a switch. Next, the sixth
In the figure, 34 is the output waveform of the intermittent drive signal generator, 35 is the speed waveform of the acceleration pulse generator and the 36-digit capstan, and 57 is the input waveform of the motor drive amplifier 28. At the beginning 22~
The speed control system constituted by 28 will be explained. A signal generated in the FG coil 25 (hereinafter referred to as FG) has a frequency proportional to the capstan speed, and is transmitted to the FG amplifier 2.
After being amplified in step 4, it is applied to the frequency-voltage converter 25. The output of this frequency-to-voltage converter 25 is proportional to the capstan speed.

This output voltage is converted into a DC multiplier 26 having a reference voltage source 27.
to be applied. The output voltage obtained here is inversely proportional to the capstan speed. Furthermore, this output voltage is applied to the motor drive amplifier 2B. The motor drive amplifier 028 causes a current proportional to its input voltage to flow through the motor. Therefore, the entire system described above operates so that the output voltage of the one-frequency voltage converter 25 matches the voltage of the reference voltage source 27, thereby forming a speed control system.

Next, intermittent drive will be explained. At to-t and t in FIG. 6, the output of the intermittent drive generator 29 is -LI (waveform 54), so the switch 56 is turned on. Motor-driven amplifier 28
The input is %L#, and the capstan motor 22 is in a stopped state with no current flowing through it.

At tl, the waveform 57 changes to 'El, and the switch 33 turns OFF.
F and the motor starts rotating due to the action of the speed control system.

Here, in order to avoid noise on the playback screen during the period when the capstan 22 shifts from stop to standard speed,
Is there a need to quickly shift to standard speed? Therefore, the motor start-up period (t1 to t).

Only, the acceleration pulse (waveform 5
5) Apply a pressure of sBz@. This acceleration pulse (waveform 35) is generated by an acceleration pulse generator 5D. This acceleration pulse generator has a built-in counter according to the present invention, and counts FG after the rise of the waveform 34 to generate an appropriate pulse. This acceleration pulse waveform 35) is applied to the motor drive amplifier 28 via the diode 31. Therefore, the input waveform of the motor-driven amplifier 28 becomes a waveform 57. Thereafter, after a speed control period (tl-ts), the motor decelerates (from t8 to to).Actually, during deceleration, the direction of the motor drive current is reversed and torque is generated in the opposite direction to the motor.This is used as a brake and the motor suddenly stops. However, since it is not directly related to the present invention, detailed explanation will be omitted.

As explained above, by employing the present invention as a means for determining the width of the acceleration pulse (waveform 39), an appropriate acceleration period can be provided. This causes the acceleration period to be too long and the vehicle to accelerate too much.
On the other hand, the situation where the start-up time of the capstan motor 25 is too long due to being too short is eliminated.

According to the present invention, even a short measurement period can be counted with high accuracy. Therefore, there is no need to intentionally increase the reference clock frequency in order to improve measurement accuracy, and the economical effect is great.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a conventional counter, FIG. 2 is an explanatory diagram of the operation of the counter, FIG. 5 is a specific circuit diagram of the present invention, FIG. 4 is an explanatory diagram of the specific circuit operation, and FIG. FIG. 6 is a block diagram showing an embodiment of the present invention, and is an explanatory diagram of the operation of the embodiment. 9...D flip flop. 10... Inver ° Evening. 11.12.15... Nantes Gate. 14.15...T clip flock. 55... Acceleration pulse. E 1 Figure 20 Status A 3 Figure 4 Figure ni tail A 滄旭B O S Figure '1-6 Figure 1 illustrator book 1) Restaurant procedure amendment (voluntary) Indication of the incident Patent Application No. 10s575 of 1988 Title of the invention Counter - Person making the amendment 2 'Ic5I'4k Formula 67 + Manufactured by Hitachi Representative Name 3 11] Win
Shigeyo Osamu Target of human correction 1. Full text of the specification of the present application 2, content of amendments to the same above and attached drawings 1 The entire text of the specification of the present application is amended as shown in the attached sheet. Full Text Corrected Description 1, Title of the Invention Counter 2, Claim 1 A counter characterized by having means for switching a trigger edge between positive and negative depending on the polarity of a black signal at the time of starting counting. 2. The switching means comprises a D clip-flop whose D input is connected to the clock signal and whose T input is connected to the measurement start signal, and the D clip-flop, the D-flip-flop, the G-flo, and the P-Q outputs, and an inverted signal of the clock signal. A first Nant's gate to which the D-flip and P-flop Q outputs are connected, a second Nant's gate to which the clock signal is connected;
and a third Nantes gate connected to the output of the second Nantes gate? Counters listed in range 1. 6 DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a counter, and particularly to a counter suitable for accurately counting input clock waveforms within a short cycle period. In conventional counters, especially when the measurement period is short, a large error occurs in the measurement time depending on the phase relationship between the hand side start and the reference clock. The configuration of a conventional counter is shown in FIG. Further, FIG. 2 shows a time chart when the phase relationship between the measurement start timing and the reference clock is different. In FIG. 1, numerals 1 and 2 are T flip-flops (hereinafter abbreviated as TFF) that operate at the rising edge of the clock. Also, in Figure 2, 3 is the reference clock, 4 is the Q output waveform of 'l'FF1,
5 is the Q output waveform of TFF 2, 6 is a measurement start signal, and is a reset pulse of TFF1, 2. Let's explain the operation. In the initial state (to), TFFl,
A reset pulse (waveform 6) is input to 2. Therefore, even if the reference clock 3 is input, the states of TFF1 and TFF2 do not change, and the output is fixed at "L". Next, the reset pulse (waveform 6) is released (tl). The counter starts working. TFFl inverts its output at the rising edge of the reference clock, Ri3, and the Q output changes to H" (tl). At the rising edge of the next reference clock, Ri3, the q output of TFFl changes to "H".
L", that is, Q changes to "B". (t5) Mo and 1'FF
2 is inverted to "H'f" (waveform 5). Next, at t4, reset input is applied to TFFl and 2, TFFl
, 2's Q outputs fall to "L". Thereafter, similar operations are performed from t5 to t6. Here, the measurement period is from the falling edge of waveform 6 to the rising edge of TFF2Q output. Then, in state A of Fig. 2, the measurement period is approximately 1 cycle of reference black and 3 (T, which is the minimum value of the measurement period. Also, in state B, 4 cycles of reference 4 and 2 cycles of ifi of 3) ( T2), this is the maximum value of the measurement period.The error was approximately one cycle, which was a problem.In order to solve this problem, the standard clock
It is also possible to raise the frequency of An object of the present invention is to provide a counter that can measure accurately even during a short measurement period. In order to achieve the above object, the present invention changes the polarity of the clock input to the counter depending on the polarity of the reference clock at the time of starting counting. An embodiment of the present invention will be described below with reference to FIGS. 3 and 4. FIG. 6 is a specific circuit diagram, and FIG. 4 is an explanatory diagram of the operation when the phase relationship between the measurement start timing and the reference clock is different. In Fig. 3, 7 is the input terminal for the measurement start signal;
8 is a reference clock input terminal, 9 is a D flip-flop (hereinafter abbreviated as DFF), and 10 is an inverter. 11.12.13 is Nantes Gate, 14 and 15 are TFF
It is. In FIG. 4, 16 is a reference clock, 17 is a measurement start signal, and reset pulses for TFFl4 and 15, and 18 is a D
This is the Q output of FF9. 19 is the clock input of TFF14, 20 is the Q output of FF7''14, 21 is TFF1
This is the Q output of 5. Let's explain the operation. This counter starts measuring at the falling edge (tl) of waveform 17. At the same time, this pulse (waveform 17) operates DFF9, and the information on the D input (waveform 16)
) That is, at this time (tl) outputs "H" to the Q output, and the waveform 1
Get 8. The Q output of DFF 9 is "L". Therefore, the Nantes gate 11 side connected to Q of DFF 9 is alive,
The reference clock 16 is input from the input terminal 8 via the inverter 10 and the NAND game) 11.13 to the T of TFF 14.
transmitted to the input. Therefore, the input to TFF 14 becomes waveform 19. TFF 14.15 divides this waveform 22 as described above to obtain waveform 20.21. Here, if the measurement period is from the falling edge of the waveform 17 to the rising edge of the Q output of rpp i s (1+ to t2), then 1.5 of the reference clock 16
This is the maximum value for the period. State A has been explained above. Next, waveform 17 becomes 1H'' (ts) TFF
14 and 15 are reset and their Q outputs become "L" (waveforms 20 and 21). Next, waveform 17 changes to "L" (t4), so the counter starts counting. At this time, the waveforms change as described above. 17 operates the DFF9, and the information of the D input (waveform 16), that is, “
L" is output to Q. Therefore, the reference clock 16 is output from terminal 8 via NAND game) 12.13 to TFF.
The T input waveform of 14 becomes waveform 19. This is frequency-divided by TEs 101 and 18 to obtain waveforms 20 and 21. At this time, the measurement period is from t4 to t5, and the reference clock 16
This is approximately one period of the period. This is the minimum value of the measurement period. State B has been described above. From the above explanation, according to this embodiment, the measurement period error can be suppressed to within a half period of the reference clock 160, and the same effect as when the reference clock frequency is doubled under the same constraints can be obtained. In addition, in the above embodiment, the configuration of the counter was explained by exemplifying the counter shown in FIG.
It goes without saying that the present invention can be applied to counters with other configurations. Next, an application example in which the present invention is applied to noiseless slow reproduction using intermittent capstan driving in a magnetic recording/reproducing device will be described. FIG. 5 shows a block diagram of an application example, and FIG. 6 shows an explanatory diagram of its operation. In Fig. 5, 22 is a capstan motor, and 23 is a frequency generator.
erator ) coil (abbreviated as FG coil), 24
is the FG amplifier. 25 is a frequency-voltage converter, 26 is a DC amplifier, 27 is a reference voltage source, 28 is a motor drive amplifier, 29 is an intermittent drive signal generator, and 30 is an acceleration pulse generator using the counter of the present invention. , 61 is a diode, 62 is a resistor, and 33 is a switch. Next, in FIG. 6, 34 is the intermittent drive signal generator 2.
9 is the output waveform, 35 is the output waveform of the acceleration pulse generator, and 6 is the output waveform of the acceleration pulse generator.
6 is the speed waveform of the capstan, and 67 is the input waveform of the motor drive amplifier 28. First, the speed control system composed of 22 to 281C will be explained. The signal generated by the FG coil 23K (hereinafter referred to as FG) has a frequency proportional to the capstan speed, and after amplifying it with the FG amplifier 24,
applied to the frequency-voltage converter 25. The output of this frequency-to-voltage converter 25 is proportional to the capstan speed. This output voltage is converted into a DC amplifier 26 having a reference voltage source 27.
to be applied. The output voltage obtained here is inversely proportional to the capstan speed. Furthermore, this output voltage is applied to the motor drive amplifier 28. Motor drive amplifier 28 causes a current to flow through the motor that is proportional to its input voltage. Therefore, the entire system described above operates so that the output voltage of the frequency-voltage converter 25 matches the voltage of the reference voltage source 27, forming a speed control system. Next, intermittent drive will be explained. From tO to t1 in FIG. 6, the output of the intermittent drive generator 29 is "L" (waveform 34), so the switch 33 is on. Motor drive amplifier 2
The input of No. 8 is "L", and no current flows to the capstan motor 22, so it is in a stopped state. At tl, the waveform 37 changes to "H-" and the switch 33 turns OFF.
The motor starts rotating due to the action of the F-speed control system. Here, in order to avoid generating noise on the playback screen during the period when the capstan 22 shifts from stop to standard speed, it is necessary to quickly shift to standard speed. Therefore, only during the motor start-up period (t1 to t2), an "R° voltage" which is an acceleration pulse (waveform 35) is applied to the motor drive amplifier 28. This acceleration pulse (waveform 35) is generated by the acceleration pulse generator 30. The acceleration pulse generator has a built-in counter according to the present invention, and counts FG after the rise of waveform 54 to generate an appropriate pulse.This acceleration pulse (waveform 35) is applied to motor drive amplifier 28 via diode 31. Therefore, the input waveform of the motor drive amplifier 28 becomes like the waveform 37. After that, the speed control period (t2 to ts) is followed by deceleration (ts to t4).In fact, during deceleration, the direction of the motor drive current is changed. It reverses and generates torque in the opposite direction to the motor.This acts as a brake and stops the motor abruptly.
Since it is not directly related to the present invention, detailed explanation will be omitted. From the above explanation, by employing the present invention as a means for determining the width of the acceleration pulse (waveform 69), an appropriate acceleration period can be provided. This may cause the acceleration period to be too long and accelerate too much,
On the other hand, the start-up time of the capstan motor 25 will not be too long due to being too short. According to the present invention, even a short measurement period can be counted with high accuracy. Therefore, there is no need to intentionally increase the reference clock frequency in order to improve measurement accuracy, and the economical effect is great. 4. Brief description of the drawings Fig. 1 is a circuit diagram of a conventional counter, Fig. 2 is an explanatory diagram of the operation of the counter, Fig. 6 is a specific circuit diagram of the present invention, and Fig. 4 is a diagram of the specific circuit operation. FIG. 5 is a block diagram showing an embodiment of the present invention, and FIG. 6 is an explanatory diagram of the operation of the embodiment. 9・・・・・・・・・・・・・・・・・・・・・D flip-flop 10・・・・・・・・・・・・・・・・・・
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Claims (1)

[Claims] 1. Depending on the polarity of the clock signal at the start of counting,
A counter characterized by having means for switching a trigger edge between positive and negative. The switching means comprises a D7 lip-flop whose D input is connected to the clock signal and whose T input is connected to the measurement start signal, and the D-flip 70-tub Q output and an inverted signal of the above-mentioned up-tub signal. a first Nant's gate to which the D flip-flop Q output and the clock signal are connected;
2. The counter according to claim 1, further comprising a fifth Nantes gate to which the output of the second Nantes gate is connected.