JPS58222557A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To obtain an integrated circuit device having a protection function larger than the conventional one and an input protection circuit which does not give any adverse effect on an input characteristic of the circuit by using an inversion layer as a protection resistance, providing an electrode on an insulating film and connecting an electrode to an input terminal through the MOS structure. CONSTITUTION:When a positive surge is applied to the input terminal 1, a parasitic capacitance is charged through an inverting layer 17 which forms a protection resistance. When a voltage of base terminal 3 exceeds the junction dielectric strength of a diode formed by the p type solicon substrate 10 and n<+> type buried region 11b, a diode breaks down and a current bypasses to a terminal 5 form the input terminal, preventing a potential of base terminal 3 to increase. In case a negative suge is applied to the input terminal 1, a diode becomes conductive and a current is bypassed to the input terminal 1 from the terminal 5 through a protection resistance 2 formed by the inversion layer 17. By since a negative high voltage is also being applied to the electrode 16, the inversion layer 17 becomes narrow and a resistance value of protection resistanle becomes large, while considerably consuming surge energy. Thereby, a remarkably efficient function as the protection circuit can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device having an input protection circuit.

2. Description of the Related Art Conventionally, semiconductor integrated circuit devices have been provided with a protection circuit in an input circuit in order to protect the circuit, particularly the input transistor, from damage caused by surges, static electricity, and the like. An example of a circuit diagram of a generally widely used input protection circuit is shown in FIG. In the figure, (1) is the input terminal, (2) is the input transistor, (3) is its base terminal, and (4) is the input terminal (1
) and the pace terminal (3), a protective resistor inserted between (
5) is the emitter terminal of the input transistor, (6) is the input protection diode connected in anti-parallel polarity between the base terminal (3) and the emitter terminal (5), and (7) is the input transistor's emitter terminal (1). This is the power connection point to the collector. Connection to the next stage is made from the emitter terminal (5).

Next, the operation of this input protection circuit will be explained.

When a positive surge is applied to the input terminal (1), the protective resistor (4)
A parasitic capacitance (not shown) is charged through. When the potential of the base terminal (3) of the transistor (1) exceeds the junction breakdown voltage of the protection diode (6), the junction diode (6)
breaks down and bypasses the current from the input terminal (1) to the emitter terminal (5), preventing the potential of the base terminal (3) from rising above that level. In addition, when a negative surge is applied to the input terminal (1), the protective diode (6) conducts and the current is passed from the emitter terminal (5) to the input terminal (1) through the protective resistor (4), and then to the base. Terminal (3
) is prevented from becoming less than the forward voltage drop of the protection diode (6), thereby protecting the input transistor (2) from destruction.

In the input protection circuit described above, it is desirable that the resistance value of the protection resistor (4) be as large as possible from the viewpoint of slowing down the potential rise of the base terminal (3) when a surge voltage is applied and consuming surge energy. However, if the resistance value of the protective resistor (4) is increased, the input signal waveform will also be blunted, significantly slowing down the circuit operation, and the signal level will also drop, causing problems in connection with other circuits. There were drawbacks.

This invention was made in view of these points, and uses an inversion layer induced under an insulating film formed on the main surface of a semiconductor substrate as a protective resistor, and an electrode is provided on the insulating film to provide an MO.
By connecting the electrode to the input terminal in the 8 structure, when a negative surge is applied to the input terminal, the above-mentioned inversion layer is canceled out, and the resistance value of the protective resistor is increased to the same constraint. It is an object of the present invention to provide a semiconductor integrated circuit device having an input protection circuit that has a large protection function and does not adversely affect the input characteristics of the circuit.

An embodiment of the present invention will be described below with reference to the drawings. Second
The figure is a sectional view showing the structure of an embodiment of the present invention. In the figure, parts equivalent to those in FIG. 1 are designated by the same reference numerals. αO is p
shaped silicon substrate, (ll&), (111:+).

(1lc) is n+ built in the same silicon substrate α1.
type buried region, (12a) is an n-type epitaxial growth layer region which becomes the collector of transistor (2), (12b),
(12a) are respectively n+ type embedded regions (llb),
n-type epitaxial growth layer region formed on (llc), (to) p-type space diffusion region of transistor (2), α4 is n+-type emitter diffusion region of transistor (2), (15a), (15b) , (15c).

(15d) is an oxide film for isolation between elements, α is an electrode formed on the isolation oxide film (15c) between the n-type epitaxial growth layer region (12b) and (12c), and Qη is the isolation oxide film (15c) is an inversion layer forming a protective resistance, and is controlled by the electrode αIK. Electrode Q →
is connected to the input terminal (1), and constitutes the gate electrode of the n-type epitaxial growth layer region (12b), (MOS transistor 12 (12) and the n+ type buried region as the source/drain region) transistor. , isolation oxide film (15
The reason why an inversion layer is not induced at the interface between a), (15b) and the p-type substrate QO& is that p-type impurities are usually doped in order to completely isolate the elements S7\. In addition, the n-type epitaxial growth layer region (1
2a), (12b), (12c), by setting the p-type silicon substrate αO to the lowest potential, the n-type epitaxial growth layer regions (12a), (12b), (1
It is well known that 2c) can be separated.

Note that the n-type epitaxial growth layer region (12c) is connected to the input terminal (1) via its n+ type portion, and the n-type epitaxial growth layer region (12b) is connected to the p-type of the transistor (2) via its n+ type portion. Pace diffusion area (13
The emitter terminal (5) drawn out from the n+ type emitter diffusion region Q41 of the transistor (2) is connected to the p-type silicon substrate 00.

Next, the operation of this embodiment will be explained. Input terminal (
When a positive surge is applied to 1), a parasitic capacitance (not shown) is charged through the inversion layer Q'I) that constitutes a protective resistor.

The potential of the base terminal (3) is the same as that of the p-type silicon substrate αO and n
When the junction breakdown voltage of the diode formed with the + type buried region (11b) is exceeded, the diode breaks down and bypasses the current from the input terminal (1) to the terminal (5), reducing the potential of the pace terminal (3). prevents it from increasing further.

Furthermore, when a negative surge is applied to the input terminal (1), the diode conducts and the current is passed from the terminal (5) through the protective resistor (2) formed by the inversion layer (17) to the input terminal ( 1), but at this time, a negative high voltage is also applied to the electrode θQ, so the inversion layer α becomes narrower, and as a result, the resistance value of the protective resistor increases, which can consume a considerable amount of surge energy. Therefore, the function as a protection circuit becomes extremely large. A desired protection resistance value can be obtained by appropriately changing the length and width of the inversion layer Qη region. Note that since the oxide film (15o) directly under the electrode OQ is relatively thick, the inversion layer a' does not change in the normal operating voltage range. That is, the resistance value of the protective resistor increases only when a negative surge is applied to the input terminal (1), and does not adversely affect the input characteristics of a normal circuit.

FIG. 3 is a sectional view showing the structure of another embodiment of the present invention.
Components equivalent to those in the embodiment of FIG. 2 are designated by the same reference numerals. In the embodiment shown in FIG. 2, all the protective resistors are composed of an inversion layer αη, but in the embodiment shown in FIG.
A barrel of n-type diffusion region a is formed in a part directly below Q8), and the protection resistor is constituted by this n-type diffusion region Q8) and the inversion layer Oη.

With such a structure, even if the inversion layer θη is pinched off by the negative surge voltage applied to the electrode a, and as a result the n+ type buried regions (llb) and (llc) are connected by bunch-through, Since there is a resistance of the n-type diffusion region θ, the function as a protective resistor is not lost.

Furthermore, the p-type silicon substrate αO and the n+ type buried region (11
Since a diode is formed by b) and the n-type diffusion region θ mark, the junction area of the diode can be increased compared to the case shown in FIG.

Note that the n-type diffusion region (to) is not necessarily the n+-type buried region K1.
It is not necessary to provide it so as to be connected to 1b), but if it is provided between the n+ type buried regions (11b) and (11c), the same effect as in the above embodiment can be achieved.

As described above, according to the present invention, the protective resistor connected to the input transistor pace is formed by an inversion layer induced under an insulating film formed on the main surface of a semiconductor substrate, and an inversion layer is formed on the insulating film. Since the electrode is electrically connected to the input terminal, when a negative surge is applied to the input terminal, the inversion layer becomes narrower and the resistance value of the protective resistor increases due to constraints such as restrictions. This has the effect that a semiconductor integrated circuit device can be obtained that has an input protection circuit that has a greater protection function than the conventional one and does not have any adverse effect on the input characteristics of a normal circuit.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an example of an input protection circuit of a conventional semiconductor integrated circuit device, FIG. 2 is a cross-sectional view showing the structure of an embodiment of the present invention, and FIG. 3 is a circuit diagram of another embodiment of the invention. FIG. 3 is a cross-sectional view showing the structure. In the figure, (1) is a signal input terminal, (2) is an input transistor, (3) is its base terminal, α1 is a silicon substrate (semiconductor base), (llb), (llc) and n+
n-type (or p-type) region], (15c) is an isolation oxide film (insulating film), 0Q is an electrode, 0η is an inversion layer, αQ
is an n-type (or p-type) impurity diffusion region. Note that the same reference numerals in the figures indicate the same or corresponding parts. Agent Makoto Kuzuno (1 other person) Procedural amendment (voluntary) Commissioner of the Japan Patent Office], Display of iJ$ patent application 1986-1064
1!2 No. 2, Name of invention Semiconductor integrated circuit device 3
Relation with -
12-3 Name (601) - E-Ryo Electric Co., Ltd. Representative Hitoshi Katayama 4, Agent Address Marunouchi, Chiyo IJJ-ku, Tokyo - Lower Eye 2-3-5 Claim for patent of specification subject to amendment Column 6 for the scope and brief explanation of the front page
, Contents of the amendment + 1) The scope of claims in the specification is corrected as shown in the attached sheet. Claims (1) An npn type input transistor formed on a p type semiconductor substrate and an electrode formed on an insulating film formed on the main surface of the semiconductor substrate and connected to a signal input terminal. an inversion 1-formation region that induces an inversion layer corresponding to an applied voltage on the semiconductor substrate immediately below the insulating film, one end of the inversion layer is connected to the signal input terminal, and the other end of the inversion layer is connected to the signal input terminal; 1. A semiconductor integrated circuit device comprising: an input protection circuit connected to the base of the input transistor and using the resistance of the inversion layer as an input protection resistance. (2) An insulating film is formed on the semiconductor substrate at a portion sandwiched between two n-shaded regions formed on the main surface of the semiconductor substrate, and connects the inversion layer to the signal input terminal and the base of the transistor, respectively. 2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is formed through two n-shaded regions. (3) A semiconductor integrated circuit device according to claim m1 or claim 2, wherein the inversion layer forming region has an n2 impurity diffusion region interposed in a part thereof. (4) The semiconductor integrated circuit device according to any one of claims 1 to 8, wherein an oxide film for isolation between elements is used as the insulating film.

Claims (4)

[Claims] (1) n formed on a p-type (or n-type) semiconductor substrate
A pn type (or pnp type) input transistor and an inversion layer formed on the insulating film formed on the main surface of the semiconductor substrate and corresponding to the voltage applied to the electrode connected to the signal input terminal are formed on the insulating film. one end of the inversion layer is connected to the signal input terminal, the other end of the inversion layer is connected to the base of the input transistor, and one end of the inversion layer is connected to the base of the input transistor. A semiconductor integrated circuit device comprising an input protection circuit using a layer resistance as an input protection resistance. (2) The insulating film is formed on the semiconductor substrate at a portion sandwiched between two n-type (or p-type) regions formed on the main surface of the semiconductor substrate, and is formed between the inversion layer, the signal input terminal, and the base of the transistor. 2. The semiconductor integrated circuit device according to claim 1, wherein the connections are made through the two n-type (or p-type) regions. (3) The inversion layer forming region is partially n-type (or p-type)
A semiconductor integrated circuit device according to claim 1 or 2, characterized in that an impurity diffusion region is interposed therebetween. (4) The semiconductor integrated circuit device according to any one of claims 1 to 3, wherein an oxide film for isolation between elements is used as the insulating film.