JPS58220469A - Semiconductor device - Google Patents

Abstract

PURPOSE:To improve the integration of a semiconductor device and to maintain effective logic operation of an FET by forming a light emitting element on the front surface and the FET on the back surface of a semi-insulating substrate, and electrically connecting the FET via a diffused layer in the substrate to the front surface. CONSTITUTION:Zn is diffused from both sides of a semi-insulating GaAS substrate 1 to form a region 2, an N type epitaxial layer 3 is formed on the surface 1A, a P<+> type GaAs film 4, a P type GaAs film 5, an N type GaAs active layer 6, an N type GaAlAs film 7 and an N<+> type GaAs film 8 are superposed on the surface 1B, and an ohmic electrode 9 deposited with Ni on Au-Ge eutectic layer is formed. Similar electrodes 12, 13 for a source and a drain are attached to the surface 1A, and annealed in N2. The layers 8-5 are selectively etched with H2SO4+H2O2+H2O, an AuZn alloy layer 10 is attached onto the layer 4, and annealed in N2. Then, the layer 3 on the region 2 on the surface 1A is opened, an AuZn alloy layer 11 is formed, superposed on part of the electrode 12 and annealed. Eventually, an aluminum gate 14 is attached. Both surfaces are effectively utilized to improve the integration, the light of a light emitting element is absorbed by the substrate so as not to reach the gate of the FET on the surface A, thereby effectively performing the operation of the FET.

Description

Detailed Description of the Invention (a) Technical Field of the Invention The present invention relates to @optical devices and field effect transistors (hereinafter referred to as F
l! ! The present invention relates to a semiconductor device in which two semiconductor devices (referred to as T) are formed on the same semi-insulating semiconductor substrate.

(b) Prior Art and Problems When forming an FET logic circuit and an optical semiconductor element on the same semiconductor substrate, conventionally they were formed on one surface of a semi-insulating semiconductor substrate. However, since the elements and FBTt:l thick circuits are placed on the same plane, the degree of integration does not increase.
Furthermore, since the light emitted from the light emitting element may hit the gate of the FHjT logic circuit, there is a problem that it is difficult to ensure normal logic operation.

(0) Object of the Invention The object of the present invention is to solve the above-mentioned conventional drawbacks, improve the degree of integration, and ensure reliable operation of the FKT.

(+1) Structure of the Invention A semiconductor device according to the present invention for achieving the above object has the following features:
A light emitting element is formed on one surface of the semi-insulating semiconductor substrate, and a field effect transistor is formed on the other surface of the semi-insulating semiconductor substrate. It is characterized by being electrically connected to one surface.

(θ) Example of the Invention Hereinafter, an example of the present invention will be described while explaining its manufacturing process.

As shown in FIG. 1, a GaAs substrate 1 having a thickness of 200 μm and having both surfaces mirror-finished was used as a semi-insulating semiconductor substrate. Although not shown, sputtering is performed on both sides at 810.
~aoooX coating, open a window with a diameter of 40 μm at the same location on both sides by normal photolithography and etching 1. Zn is diffused from both sides to form a semi-insulating base.
A diffusion region 2 is provided in the plate 1 . Surface damage caused by diffusion and layers with lateral spread of diffusion are removed by etching.

As a semi-insulating semiconductor substrate 1, GaA 3 with a thickness of 200 μm with both sides mirror-finished, then F' on one surface IA.
Acts as the active layer of BT (n-GaAe (donor impurity concentration n-lX101'cfIt-s, thickness t = α2 μm)
is grown by molecular beam epitaxy ('HBB) growth method.

Next, as shown in Figure 2, MHI! ! Other aspects of growth method IB
P as a buffer layer and a P contact layer of the laser on top.
-GaAs thickness n=3X10”ms, t=-2
3 μm) and a thick P-GaAtAs layer as a carrier confinement layer on top of the P-IXIO” tM.
−”.

t-1μm), n- as the active layer of the laser diode
GaAs layer 6 (n#1
μm), n-GaA as carrier confinement layer
tAe layer f(n=3×1011 examples-', t-1 μm),
n-eaas layer 8 (n jl
llo"cflI", t-1 μm) is grown continuously. Next, as shown in FIG. 3, an ohmic contact 9 on the n side (a eutectic layer of Au and Go and a Ni layer formed thereon) was vacuum-deposited at 3000K.

Width 10 μm using normal photolithography and etching.

The stripes are 300 μm long. Next, the source (s) l drain (
D) Ohmic contact layer 12. li1% 3
Then, AuGθ/Nt is formed by the lift-off method in the same manner as above, and heat treated at 420° C. for 1 minute in an N2 atmosphere.

Next, a photoresist is applied to the surface of the substrate 13, and then a photoresist film is formed by photolithography to a width of 250 μm and a length of 310 μm so as to cover the n-contact. Leave it at lJm.

Next, as shown in FIG. 4, H! S 04/H! 0 @ /
P” with J-etching liquid of HI 0 weight ratio (1:8:l)
- Etch until GaAe /ii4 is reached.

Next, an AuZn alloy layer is vacuum-deposited, and the upper P''-GaA layer is diffused with Zn using conventional photolithography and etching.
Place an AuZn alloy layer 1o on a part of gA.

Heat treatment at 400°C for 5 minutes* in an atmosphere.

Next, the n-GaA portion of the LA surface where Zn is diffused is
After removing the c1 layer 3 by etching, the AuZn alloy layer 11 is vacuum-deposited, and then the AuZn and Zn-diffused parts, the FIT operating layer, and the FI
After covering a portion of the ItT source (S) and electrode, heat treatment is performed at 400° C. for 5 minutes in an INFs atmosphere. Through this step, the source (S) electrode of the FIItT and the P electrode of the laser are electrically connected through the diffusion region 2 in the semi-insulating semiconductor substrate 1 described above.

Next, At as the gate metal of the FET on the IA part of the substrate.
14 is formed by a lift-off method. In this way, as shown in FIG.
An F-type 'r, a laser die, and an ode are formed on the B side, respectively.

(f) Effects of the Invention According to the present invention, both sides of a semi-insulating semiconductor substrate can be effectively utilized, so that the degree of integration is improved. Furthermore, the light emitted from the light emitting element is absorbed by the semi-insulating GaAs substrate, so it does not reach the gate of the FBT located on the A-plane. Therefore, the operation of FIltT is ensured.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIGS. 1 to 5 are cross-sectional views in the order of steps in manufacturing an embodiment of the present invention, and in particular, FIG. 5 is a diagram showing an embodiment of the present invention. . In the figure, 1 is a GaAs substrate and 2 is a diffusion region. 4 is a p+-GaAs layer, 5 is a p-GaAtAs layer, 6 is an n-Gaks layer, M is an n-GaAtAl layer, 8 is an n+
-GaA0 layer, 10.11 is AuZn alloy layer, 12.1
3 is the sauce.

Claims (1)

[Claims] A light emitting element on one surface of a semi-insulating semiconductor substrate. Field effect transistors are formed on the front and other back surfaces, respectively.
A semiconductor device characterized in that the field effect transistor is electrically connected to the one surface of the semi-insulating semiconductor substrate via a diffusion region formed in the semi-insulating semiconductor substrate.