JPS58220455A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS58220455A JPS58220455A JP10439882A JP10439882A JPS58220455A JP S58220455 A JPS58220455 A JP S58220455A JP 10439882 A JP10439882 A JP 10439882A JP 10439882 A JP10439882 A JP 10439882A JP S58220455 A JPS58220455 A JP S58220455A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- substrate
- patterns
- pattern
- conductor pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5382—Adaptable interconnections, e.g. for engineering changes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0286—Programmable, customizable or modifiable circuits
- H05K1/0292—Programmable, customizable or modifiable circuits having a modifiable lay-out, i.e. adapted for engineering changes or repair
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/225—Correcting or repairing of printed circuits
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
本発明はチップの交換が容易な半導体装置の改良に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a semiconductor device whose chips can be easily replaced.
従来、フレキシブルフィルム等の基板上に導体パターン
を形成し、この導体パターンに直接チップをバンプを介
して接続する方法が提案されている。Conventionally, a method has been proposed in which a conductor pattern is formed on a substrate such as a flexible film and a chip is directly connected to the conductor pattern via bumps.
例えば、第１図に示すように基板ｌ上に導体パターン２
を形成し、このパターンにチップ３のバンプ４を接続し
、上記チップと導体パターンを樹脂５により封止し、基
板ｌとチップ３との間隙に遮光用樹脂６を介在させてい
る。For example, as shown in FIG.
The bumps 4 of the chip 3 are connected to this pattern, the chip and the conductor pattern are sealed with a resin 5, and a light-shielding resin 6 is interposed in the gap between the substrate 1 and the chip 3.
しかし、この方法はＬＳＩチップが不良になると樹脂で
封止している為に、チップを基板より取外して、再びボ
ンティングすることが不可能で、チップが不良になると
基板自体を交換しなければならず、特に複数チップを有
する基板の場合、′基板全体を交換することはコスト的
に問題があり、容易に基板交換に応じられないという難
しい欠点を有していた。However, with this method, if the LSI chip becomes defective, it is sealed with resin, so it is impossible to remove the chip from the substrate and bond it again, and if the chip becomes defective, the substrate itself must be replaced. In particular, in the case of a board having a plurality of chips, it is costly to replace the entire board, and it is difficult to replace the board easily.
本発明は上記半導体装置の欠点を除去するため特
になされたもので、様に上記半導体装置に於て、上記基
板の導体パターンと反射面に、導体パターンと置換可能
な複修用の導体パターンを形成し、不良チーツブの交換
に即座に対応できるようにしたことを特徴とする。The present invention has been made especially to eliminate the drawbacks of the above-mentioned semiconductor device, and similarly, in the above-mentioned semiconductor device, a conductive pattern for repair that can be replaced with the conductive pattern is provided on the conductive pattern and the reflective surface of the above-mentioned substrate. It is characterized by being able to immediately respond to the replacement of defective chips.
以下、本発明の半導体装置の一実施例を図面に従って説
明する。An embodiment of the semiconductor device of the present invention will be described below with reference to the drawings.
第２図は本発明装置の断面図であって、第１図と同一部
分には同一符号を示している。図に於て、ｌはガラスエ
ポキシ材、あるいは紙エポキシ材等よりなる基板、２は
導体パターンで、基板表面の導体パターン２ａ、２ｂ、
２ｃ、２ｄに対向し、該パターンと置換可能な（不良チ
ップを交換するだめの）複修用導体バクーン２ ａ’
、 ２ ｂ 、 ２ ｃ’ 、 ２ （１’がそれぞれ
設けられている。例えばパターン２ａ。FIG. 2 is a sectional view of the apparatus of the present invention, and the same parts as in FIG. 1 are designated by the same reference numerals. In the figure, l is a substrate made of glass epoxy material or paper epoxy material, etc., 2 is a conductor pattern, and conductor patterns 2a, 2b on the surface of the substrate,
2c and 2d, a conductor for repair 2a' that can be replaced with the pattern (for replacing a defective chip)
, 2 b , 2 c' , 2 (1') are provided, respectively.For example, pattern 2a.
２ｂを基板ｌの裏面にスルーホール７を介して電気的に
同一関係になるようにパターン２ａ′、２ｂ′を基板裏
面に形成し、同様に、パターン２ｃ、２ｄをスルーホー
ル７′を介して基板裏面にパターン２ ｃ ｒ ２ ｄ
を形成する。従って、パターン２ａ。Patterns 2a' and 2b' are formed on the back surface of the substrate l so that they have the same electrical relationship through the through hole 7, and similarly patterns 2c and 2d are formed on the back surface of the substrate l through the through hole 7'. Pattern 2 cr 2 d on the back of the board
form. Therefore, pattern 2a.
２ｂにボンディングされたチップが不良となった場合は
、基板表面のパターン２ａ’、２ｂ’に良品のチップを
ボンディングする。同様にパターン２ｃ。If the chip bonded to 2b becomes defective, a good chip is bonded to patterns 2a' and 2b' on the surface of the substrate. Similarly pattern 2c.
２ｄにボンディングされたチップが不良となった場合、
パターン２ｃ’、２ｄ’にボンディングすることにより
不良チップに代見て良品のチップを取付けることができ
る。不良となったチップは回路基板から電気的に切離す
ため、ボンティングバク−く付祈の導体パターンを切断
するだけで良い。If the chip bonded to 2d becomes defective,
By bonding to patterns 2c' and 2d', a good chip can be attached in place of a defective chip. In order to electrically disconnect a defective chip from the circuit board, it is sufficient to simply cut the conductor pattern of the bonding backing.
以上説明したように本発明によれば、基板の裏面に基板
前曲の反射面に上記導体パターンと置換可能な複修用パ
ターンを設けたから、不良チップの交換が基板反対面の
導体パターンに新たにチップをボンディングすることに
より容易に達成でき、とくに基板自体が複数のチップを
拾載する場合、基板自体を取換える必要がないから、実
質上コスト低減に繋がるなどの利点を有する。As explained above, according to the present invention, since a repair pattern that can be replaced with the conductive pattern is provided on the reflective surface of the front curve of the board on the back side of the board, a defective chip can be replaced with a new conductive pattern on the opposite side of the board. This can be easily achieved by bonding chips to each other, and especially when a plurality of chips are mounted on the board itself, there is no need to replace the board itself, which has the advantage of substantially reducing costs.
第１図は従来の半導体装置の要部断面図、第２図は本発
明による半導体装置の一実施例を示す要部断面図である
。
１ 基板、２・導体パターン、３：チップ、４・バンプ
、５：樹脂、２ａ〜２ｄ：基板前面の導体パターン、２
ａ〜２ｄ ：基板裏面の導体パターン。FIG. 1 is a sectional view of a main part of a conventional semiconductor device, and FIG. 2 is a sectional view of a main part of an embodiment of a semiconductor device according to the present invention. 1 Substrate, 2. Conductor pattern, 3: Chip, 4. Bump, 5: Resin, 2a to 2d: Conductor pattern on front of board, 2
a to 2d: Conductor pattern on the back side of the board.
Claims (1)
該チップと導体パターンとを樹脂封止してなる半導体装
置において、 上記基板の導体パターンと、反対基板面に該導体パター
ンと置換可能な補修用の導体パターンを形成したことを
特徴とする半導体装置。[Claims] 1. Connecting the bumps of the chip to the conductor pattern on the substrate,
A semiconductor device formed by resin-sealing the chip and a conductor pattern, characterized in that the conductor pattern on the substrate and a repair conductor pattern replaceable with the conductor pattern are formed on the opposite substrate surface. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10439882A JPS58220455A (en) | 1982-06-16 | 1982-06-16 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10439882A JPS58220455A (en) | 1982-06-16 | 1982-06-16 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58220455A true JPS58220455A (en) | 1983-12-22 |
Family
ID=14379618
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10439882A Pending JPS58220455A (en) | 1982-06-16 | 1982-06-16 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58220455A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6127642A (en) * | 1984-07-18 | 1986-02-07 | Toshiba Corp | Manufacture of hybrid integrated circuit |
-
1982
- 1982-06-16 JP JP10439882A patent/JPS58220455A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6127642A (en) * | 1984-07-18 | 1986-02-07 | Toshiba Corp | Manufacture of hybrid integrated circuit |
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