JPS5821927A - Interface circuit - Google Patents

Abstract

PURPOSE:To ensure the stable conversion of level for an input/output circuit to the saturated working of a transistor and the fluctuation of a power supply, by supplying a constant current to each base of the transistor. CONSTITUTION:The same current I is supplied to the bases of transistors TR1 and TR2 when an output signal G0 of a gate circuit G has a rise. Thus both TR1 and TR2 are turned on. In this case, the collector currents of the TR1 and TR2 has the same value as long as TR3 and TR4 have the same characteristics with the resistances R1 and R2 set at the same value. Accordingly both TR1 and TR2 have the same saturated collector voltage and has the same change with each other to an input signal. The level of an output signal Q2 at this moment supplies the voltage of a certain level to an output circuit at all times as the reference voltage signal of the output circuit like an ECL, etc. Based on the signal Q2, an output signal Q1 having a desired and prescribed logical amplitude is produced at an output circuit in accordance with an input signal IN.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an interface circuit that performs level conversion between input and output circuits.

Generally, an interface circuit that performs level conversion is required between logic circuits that operate at different voltage levels. For example, ILL(, Int@grat@d −
Inj@ction Logie) and ECL (Emlt
For example, in an IC in which each logic circuit (Coupled Logic) is integrated on one chip, the operation tube of the ECLC (ECLC) is controlled by a signal from I"L. In this case, !1L is the DC voltage for circuit operation. is at a low potential near the ground potential (GND), whereas ECL operates at a high potential near the power supply potential due to non-saturation operation, so a level conversion interface circuit is required between the two. As shown in Fig. 1, such an interface circuit usually consists of a Niotsuta grounded bipolar transistor (hereinafter simply referred to as a transistor) Tr,' which is parallel to the ground side between the power supplies (between Vee and GND). An input signal IN and its inverted signal IN are supplied from an input circuit such as I''L to each of the transistors Trl and Try, and 1 to each collector of the transistors Trl and Try. , each emitter current of the transistor 〒r@, Tr is supplied through the resistor R+-Btu'', and the transistor Try.

Ding r4 is! A predetermined bias voltage V from an output circuit such as 1iCL is supplied to each pace0, and a power supply v@C is supplied to each collector of this transistor Tzs□Tr4 through resistors R1t and R4e, respectively. , an output signal Q having a voltage level corresponding to the circuit operation of an output circuit such as an ICL, and its inverted signal Qz are generated from each collector.

Such an interface circuit allows the input signals IN, I"L, etc., whose reference potential is at a low level, to be input from the input circuit such as I"L.
For N, the output Q of ICL etc. can be supplied to the tube. However, the above ■tLII! When the input circuit is a saturated operating circuit as shown in FIG.
Due to the influence of the saturation accumulation time tstg of rl, there is a time delay TL when the transistors Try and terl operate from on to off.
As a result, the output signal Q1 and its inverted signal Q! to the output circuit are generated as shown in FIG. This results in unstable signals such as becoming out of sync. In addition, in order to solve such drawbacks, the transistor Tr! to which the input signal n is supplied in the interface circuit shown in FIG. Instead, a resistor Rx tube is provided, and as shown in FIG. 3, a constant voltage level reference signal is generated as an output signal Qt' to be supplied to an output circuit such as HCL, and this signal Q! However, in this case, the variation in the saturation voltage Vsatl of the transistor Tr1 and the voltage
Due to the variation of lVee, the signal q! Output signal Q for
There is a drawback that the level of 1 becomes unstable.

This invention was made in view of the above circumstances, and it converts to a predetermined level according to the input signal from the input circuit, which is a saturation type operation circuit, and is stable against transistor operation of the input circuit and power supply fluctuation. An embodiment of the present invention will be described below with reference to the drawings.

FIG. 4 shows the configuration of the interface circuit shown in FIG. 1, in which transistors r1. T
r! A constant current I is supplied from a constant current source ii, xz to which a bias voltage V4 is applied from an input circuit such as I''L.
At this pace, the input signal IN is supplied from the input circuit, which is a saturation type operation circuit of the I'L type, via the gate circuit G (inverter circuit). As shown in FIG. 3, when the gate circuit G to which the input signal IN is currently supplied is in the off state, that is, in the state where the output signal G0 of the gate circuit G has risen (H level), the transistor Try.

The same current I is supplied to the pace of Trz, and the transistors Try and Try are turned on.If the transistors T rsl T'4 have the same characteristics, then the transistors 'l'r, , In the collector current rc1 and Iez of Tr2, Icl is as follows.

Here, R1: Resistance value vsatl of resistor R1: ) Saturation collector voltage vBz of transistor Trl, : ) 0, which is the voltage between base 0 and terminal 1 of transistor Tr3.And if resistor R3 and resistor R1 have the same value, then
The collector currents Icl and Iez have the same value, 0. Therefore, the transistors T rl * T rt have the same saturated collector voltage vmail t'', and they both make the same change with respect to the input signal. (From the above, the level of the output signal Q*-Q* at this time is Ql x= Yes -R1・Iel...
...(2) Q, = Wee -R1/2 ・I ex
...”・(3), where IL, :Resistance value of resistor a, ＄＄/!0, which is the resistance value of two resistors IL4, is the output signal Qt 4D level is the reference voltage of the output circuit of ICL$ Further, as shown in FIG. 5, the gate circuit G is in the on state, that is, the output signal G of the gate circuit is always constant and supplied to the Pel O voltage tube output circuit.
・If ' falls (L level) and transistor T r1 is off, output signal Q! The level of is almost the same as the power supply vCC 〇 In this way, by setting the resistance values of resistors No. R to predetermined values, the operation reference signal (output signal Qt ), and this signal Q2
Input signal INK from input circuit such as I”L with reference to
``The specified logic m*s' required for the output circuit such as ICL
generates an output signal Qs having . therefore,! 2
Transistors Try, Tr with saturation type operation path such as L
Saturation accumulation time of y! It is possible to prevent instability such as non-synchronization of the output signal Qs=Q due to the influence of "stg %", and to generate a stable output signal that can reliably set the operating voltage level of the output circuit according to the input signal IN. For example, since the output signal Qs-Q with respect to power supply V@co fluctuations has the same saturation voltage characteristics,
The stability of the level of t is determined by the transistor Tr@, diraK
0 obtained by stabilizing the supplied bias voltage Vo, that is, the resistance Ba which is the output load resistance
, R4 is determined by the characteristics of the transistors r1 to r4 and the resistor R1, as is clear from the above equation (1).
, Rt, so the output signal Q!
The level of the output signal Q1 can be kept constant at all times.
0, which is an interface circuit in which the level of 2 is left by a diode, that is, the resistor ml,,R,
A power supply Yec is supplied via the diode D, thereby producing an output signal QteQ! The level of will drop by the voltage drop across the diode. Furthermore, in the above embodiment,
Transistor Tr1. As mentioned above, each base of the Trl has a current! is supplied through a constant current source 11.11″f, which is connected to the bases of transistors 〒rl and 〒r4 and connected to a bias resistor R＠aR
s t-May be used 0 This circuit has the same effect and operation as the interface circuit shown in FIG. According to the present invention, for an input signal from an input circuit which is a saturation type operation path, a immersion reference signal having a reference voltage level corresponding to the operation of the output circuit and a predetermined cycle amplitude with respect to the reference signal are generated. By being able to generate a stable output signal converted to a level, an interface circuit 't41I can be provided which can perform stable level conversion of the input/output circuit against the saturation operation of the transistor in the input circuit and fluctuations in the power supply.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a conventional interface circuit, FIG. 2 is a diagram showing its timing chart, FIG. 3 is also a diagram showing its timing chart, and FIG. 4 is an interface according to an embodiment of the present invention. FIG. 5 is a diagram showing a timing chart thereof, and FIG. 6 is a diagram showing a configuration of an interface circuit according to another embodiment of the present invention. Ding rlx7r4...Paiborado 2ndista, RI~
R6...Resistance, 11.11... Constant current source, D...
Diode 0 Applicant's agent Patent attorney Takeshi Suzue tIIJ1W!
J 112W1 113gi1 1I4WI No.5

Claims (1)

[Claims] A first bipolar transistor and a second bipolar transistor with common emitters are provided in parallel between the power supplies and a predetermined constant current is supplied to each of the transistors;
and a third bipolar transistor and a fourth bipolar transistor, which are connected in parallel to each collector of the second bipolar transistor through a resistor, and the third and fourth bipolar transistors are connected to each collector of the second bipolar transistor through a resistor. means for supplying a predetermined voltage to each collector of the first bipolar transistor, an input signal from the input circuit is supplied to the first bipolar transistor, and an input signal from the input circuit is supplied to each of the third and fourth bipolar transistors. An interface circuit characterized in that a predetermined bias voltage is supplied from the output circuit, and each collector of the interface circuit supplies an output signal having a voltage level corresponding to the input signal and a reference voltage level of the output circuit to the output circuit.