JPS58161513A - Gain control amplifying circuit - Google Patents

Gain control amplifying circuit

Info

Publication number
JPS58161513A
JPS58161513A JP4410482A JP4410482A JPS58161513A JP S58161513 A JPS58161513 A JP S58161513A JP 4410482 A JP4410482 A JP 4410482A JP 4410482 A JP4410482 A JP 4410482A JP S58161513 A JPS58161513 A JP S58161513A
Authority
JP
Japan
Prior art keywords
transistor
voltage
current
signal
emitter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4410482A
Other languages
Japanese (ja)
Inventor
Yoshiaki Takahashi
高橋 義昭
Yasuhiro Sugimoto
泰博 杉本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP4410482A priority Critical patent/JPS58161513A/en
Publication of JPS58161513A publication Critical patent/JPS58161513A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03GCONTROL OF AMPLIFICATION
    • H03G1/00Details of arrangements for controlling amplification
    • H03G1/0005Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal
    • H03G1/0017Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal the device being at least one of the amplifying solid state elements of the amplifier
    • H03G1/0023Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal the device being at least one of the amplifying solid state elements of the amplifier in emitter-coupled or cascode amplifiers

Landscapes

  • Control Of Amplification And Gain Control (AREA)

Abstract

PURPOSE:To linearize the control voltage-gain characterisics, by inserting a transistor to a diode and supplying the input signal voltage given from an input signal source to the emitter of a current source transistor. CONSTITUTION:It is possible to set the DC voltage of a signal output terminal 11 at a fixed level owing to the function of a dummy circuit 22 despite variations of control voltage VC since diodes D an D' are inserted to the emitters of transistors TRQ2 and Q2' having a base common with each other. While input signal voltage ei is converted into a signal current I0 as shown by i0=ei/Ri if signal current i0 flowing to a constant current source 21 from an input signal source 14 via an input resistance Ri is much less than the current IO of a constant current source 21. Then the signal current i0 flows to TRQ1 and Q2 with a shunt ratio which is decided by the control voltage VC, and output signal voltage e0 is generated by a signal current i1 which flows to a load resistance RL. The gain control characteristics of this circuit depend approximately on a linear equation of the current I1 of the TRQ1 and becomes linear.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明はトランジスタ増幅回路、特に分流比可変Wiの
利得制御増幅回路に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a transistor amplifier circuit, and particularly to a gain control amplifier circuit with a variable shunt ratio Wi.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

この種の分流比可変型の利得制御増幅回路の従来例を第
1図に示す。すなわち、QtおよびQsU差動対をなす
NPN型のトランジスタであって、各エミッタが結合さ
れて接続されている。
A conventional example of this type of variable shunt ratio gain control amplifier circuit is shown in FIG. That is, they are NPN type transistors forming a Qt and QsU differential pair, and their emitters are connected together.

そして、一方のトランジスタQ1のコレクタは、信号出
力端子11に接続されると共に負荷抵抗RLを介して電
源子Bに接続され、他方のトランジスタQ濡のコレクタ
は直接に上記電源子Bに接続されている。また、上記差
動対のトランジスタQsおよびQ3の各ベース間に電圧
可変波の制御電源1jが接続されている。
The collector of one transistor Q1 is connected to the signal output terminal 11 and is also connected to the power supply element B via the load resistor RL, and the collector of the other transistor Q1 is directly connected to the power supply element B. There is. Further, a variable voltage wave control power source 1j is connected between the bases of the transistors Qs and Q3 of the differential pair.

一方、QIは電流源用のたとえばNPN型のトランジス
タであり、そのコレクタ扛前記差動対トラ/ゾスタQ>
aQzのダミ、りに接続され、上記トランジスタQ3の
エミッタはダミ、り抵抗R,を介して接地されている。
On the other hand, QI is, for example, an NPN type transistor for a current source, and its collector is connected to the differential pair transistor/zoster Q>
The emitter of the transistor Q3 is connected to the dummy resistor R of aQz, and the emitter of the transistor Q3 is grounded through the dummy resistor R.

IJはバイアス電源であって、上記トランジスタQsの
ペースに接続されている。14は入力信号源、15はそ
の内部抵抗であり、16は入力信号源14からの入力信
号を上記トランジスタQsのペースに供給する丸めの結
合容量である。
IJ is a bias power supply and is connected to the pace of the transistor Qs. 14 is an input signal source, 15 is its internal resistance, and 16 is a rounded coupling capacitor that supplies the input signal from the input signal source 14 to the pace of the transistor Qs.

さらに、11はダミー回路であり、これは差動対トラン
ジスタQ、/およびQ、/、電流源用トランジスタQ 
I’% ダミ、り抵抗R11バイアス電源1s′よりな
る。上記差動対トランジスタQ1′。
Furthermore, 11 is a dummy circuit, which includes differential pair transistors Q, / and Q, /, current source transistor Q
I'% Dummy consists of a resistor R11 and a bias power supply 1s'. The differential pair transistor Q1'.

Qs’の各コレクタは対応して前記差動対トランジスタ
Ql=Q1の各コレクタに対応して接続され、t*)ラ
ンジスタQ1およびQt’のベース同志が接続されると
共にトランジスタQ3およびQ、10ペース同志が接続
されている。なお、バイアス電源13の電圧とバイアス
電源13′の電圧と捻等しく、ダミ、り抵抗RIおよび
ljはそれぞれ等しい値が選定されている。
Each collector of Qs' is correspondingly connected to each collector of the differential pair transistor Ql=Q1, t*) The bases of transistors Q1 and Qt' are connected together, and the transistors Q3 and Q, 10 bases are connected together. Comrades are connected. Note that the voltage of the bias power supply 13 and the voltage of the bias power supply 13' are equal, and the dummy resistors RI and lj are selected to have equal values.

而して、バイアス電源IJの電圧によりトランジスタQ
sの直流電流I・が定まり、この電流l・は制御電源1
2からの制御電圧VCによって定まる分流比(11:I
s)で差動対トランジスタQ1およびQsに流れる。な
お、この動作と同様にダミー回路11が動作し、信号出
力端子11の直流電圧は制御電圧■cが変化しても一定
に保たれる。
Therefore, the voltage of the bias power supply IJ causes the transistor Q to
The DC current I of s is determined, and this current l is the control power supply 1
The shunt ratio (11:I) determined by the control voltage VC from 2
s) to the differential pair transistors Q1 and Qs. Note that the dummy circuit 11 operates in the same manner as this operation, and the DC voltage at the signal output terminal 11 is kept constant even if the control voltage ■c changes.

いま、入力信号源14から入力信号電圧e(が入力され
ると、この信号電圧e1はトランジスタQsで信号電f
t46に変換されこの信号電流制御電圧vcによって定
まる分流比(’l;ds)でトランジスタQ1およびQ
!に流れ、一方のトランジスタQ1の負荷抵抗RLに流
れる信号電流i1によって出力信号電圧eoが発生し、
この信号電圧eoの大きさは5lXRLである。
Now, when an input signal voltage e (is input from the input signal source 14), this signal voltage e1 is converted to a signal voltage f by the transistor Qs.
Transistors Q1 and Q with a shunt ratio ('l;ds) determined by this signal current control voltage
! An output signal voltage eo is generated by the signal current i1 flowing through the load resistor RL of one transistor Q1,
The magnitude of this signal voltage eo is 5lXRL.

したがって、信号電流(0の全てがトランジスタQxt
流れるとき、 4 ea  =<6xRL =−XRL、        
     −・・會+−(すR鳶 上記回路の利得Gを制御するためには、トランジスタQ
1を流れる信号電流(1を制御電圧■、によって変えれ
ばよい。ここで、利得制御特性を考察する。トランジス
タQ1.Qsのペース・ダミ、り閣電圧をvlml 1
 v112 、これらの差電圧をΔv、鳶12で表わす
と、 となる。
Therefore, the signal current (all of 0 is transistor Qxt
When flowing, 4 ea =<6xRL =-XRL,
-...+-(S) In order to control the gain G of the above circuit, the transistor Q
The signal current flowing through the transistor Q1 (1 can be changed by the control voltage ■).Here, consider the gain control characteristics.
v112, and these differential voltages are expressed as Δv and 12, as follows.

1、+Il ”I・           ・・・・・
・(4)であるから となp1制御電圧VcO変化に対する電流11の変化は
1h(Io−It)に依存する。
1, +Il ”I...
- Since (4) is satisfied, the change in the current 11 with respect to the change in the p1 control voltage VcO depends on 1h (Io-It).

一方、出力信号電圧e・、入力信号電圧e(はそれぞれ
前述したように ee −4s XRL        ”−(7)。イ
= j@ XRg        ・・・・・・(8)
であるから となる。そして、利得Gは であり、上式翰および削代(6)から となる。すなわち、上式aυから分るように、利得Gは
制御電圧VCの変化に対してトランジスタQ1の電流I
lの二乗特性で変化し、第3図中点線で示すように利得
制御特性が非線形となる欠点がありた。
On the other hand, the output signal voltage e・ and the input signal voltage e (as described above, are respectively ee −4s
This is because it is. Then, the gain G is obtained from the above formula and the cutting allowance (6). That is, as can be seen from the above equation aυ, the gain G is the change in the current I of the transistor Q1 with respect to the change in the control voltage VC.
There was a drawback that the gain control characteristic changed according to the square of l, and the gain control characteristic became nonlinear as shown by the dotted line in FIG.

〔発明の目的〕[Purpose of the invention]

本発明は上記の事情に鑑みてなされたもので、制御電圧
対利得特性を線形化し得る分流比可変屋の利得制御増幅
回路を提供するものである。
The present invention has been made in view of the above circumstances, and provides a gain control amplifier circuit with a variable shunt ratio that can linearize the control voltage vs. gain characteristic.

〔発明の概要〕[Summary of the invention]

すなわち本発明は、差動対トランジスタのうち信号出力
用でない方のトランジスタのエミ。
That is, the present invention relates to the emitter of the transistor that is not for signal output among the differential pair transistors.

り側にダイオードを挿入し、上記トランジスタのコレク
タ側にも負荷抵抗を挿入し、ダミー回路においても上記
トランジスタとベース同志が接続されるトランジスタの
エミ、り側にダイオードを挿入し、前記差動対トランジ
スタの電流源回路にベース接地型トランジスタを用い、
このトランジスタのエミッタ側に入力信号を供給するよ
うにしたものである。したがって、前記ダイオードの順
方向電圧降下が制御電圧に影響し、利得制御特性が線形
化されるようになる。
A diode is inserted on the opposite side, a load resistor is also inserted on the collector side of the transistor, and a diode is inserted on the emitter and rear side of the transistor whose bases are connected to each other in the dummy circuit. A common base transistor is used in the transistor current source circuit,
An input signal is supplied to the emitter side of this transistor. Therefore, the forward voltage drop of the diode affects the control voltage, and the gain control characteristics are linearized.

〔発明の実施例〕[Embodiments of the invention]

以下、図面を参照して本発明の一実施例を詳細に説明す
る。I!2図に示す分流比可変製の利得制御増幅回路は
、第1図を参照して前述した利得制御増幅回路に比べて
、ダイオードD 、 D’および負荷抵抗RL′を挿入
し、電流源トランジスタQsおよびQs’のエミ、り抵
抗(籐1図R,,RE’)に代えて定電流源21および
21′を接続し、入力信号源14からの入力信号電圧e
、を結合容量16および入力抵抗Riを直列に介して電
流源トランジスタQ3のエミッタに供給するようにした
点が異なり、その他は同じであるから第2図中第1図と
同一部分扛同一符号を付してその説明を省略する。
Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. I! The variable shunt ratio gain control amplifier circuit shown in FIG. 2 is different from the gain control amplifier circuit described above with reference to FIG. The input signal voltage e from the input signal source 14 is
The difference is that , is supplied to the emitter of the current source transistor Q3 through the coupling capacitor 16 and the input resistor Ri in series, and other things are the same, so the same parts in FIG. 2 as in FIG. The explanation will be omitted.

前記ダイオードDは、そのアノードがトランジスタQ!
のエミッタに接続され、そのカソードがトランジスタQ
lのエミ、りおよび電流源トランジスタQ3のコレクタ
に接続されている。
The diode D has an anode connected to the transistor Q!
is connected to the emitter of the transistor Q, and its cathode is connected to the emitter of the transistor Q
It is connected to the emitter of L and the collector of current source transistor Q3.

t7’E、他方のダイオードVは、そのアノードがトラ
ンジスタQ雪′のエミッタに接続され、そのカソードが
トランジスタQ、/のエミ、りおよび電流源トランジス
タQs’のコレクタに接続されている。そして、前記負
荷抵抗RL′は、トランジスタQ:およびQm’のコレ
クタ接続点と電源十Bとの間に接続されている。なお、
定電流源21゜21′の電流l・yI6’はそれぞれ等
しくされている。
t7'E, the other diode V has its anode connected to the emitter of the transistor Q', and its cathode connected to the emitter of the transistor Q, / and the collector of the current source transistor Qs'. The load resistor RL' is connected between the collector connection point of the transistors Q and Qm' and the power supply 1B. In addition,
The currents l and yI6' of the constant current sources 21° and 21' are made equal to each other.

而して、上記構成においては、それぞれのベースが共通
されたトランジスタQsIQ雪′のエミ、りそれぞれに
ダイオードD 、 D’が挿入されているので、制御電
圧vcが変化してもダミー回路22の従来例における動
作に準じ次動作によって、信号出力端子11の直流電圧
を一定化する作用が従来通り得られる。
In the above configuration, since the diodes D and D' are inserted into the emitters of the transistors QsIQ', which have a common base, even if the control voltage vc changes, the dummy circuit 22 remains unchanged. By the following operation similar to the operation in the conventional example, the effect of making the DC voltage at the signal output terminal 11 constant can be obtained as in the conventional example.

一方、入力信号源14から入力抵抗R(を経て定電流源
21に流れる信号電流(・が定電流源21の電流工・に
比べて充分小さければ、入力信号電圧e1は次式で示す
ように信号電流46に変換される。
On the other hand, if the signal current flowing from the input signal source 14 to the constant current source 21 via the input resistor R is sufficiently small compared to the current of the constant current source 21, the input signal voltage e1 will be as shown in the following equation. It is converted into a signal current 46.

そして、上記信号電流(・は制御電圧■。によって定ま
る分流比(jx;jx)でトランジスタQtおよびQx
に流れ、負荷抵抗RLに流れる信号電流(1によって出
力信号電圧e・が発生する。
Then, the transistors Qt and Qx are controlled at the shunt ratio (jx; jx) determined by the signal current (・ is the control voltage
The signal current (1) flowing through the load resistor RL generates an output signal voltage e.

次に、上記回路の利得制御特性を考察する。Next, the gain control characteristics of the above circuit will be considered.

ダイオードDの順方向電圧降下をVDで表わすと、Vc
 ” Vmml −VD −Vmm2    =・・(
131が成立する。ここで、ダイオードDおよびトラン
ジスタQ3のエミ、りには同じ電流!雪が流れているの
で、 ■ゎ=V□2       ・・・・・・α荀(但し%
Il:)ランジスタの飽和電fi)が成立する。
When the forward voltage drop of diode D is expressed as VD, Vc
” Vmml −VD −Vmm2 =...(
131 is established. Here, the same current flows through the emitters of diode D and transistor Q3! Since the snow is flowing, ■ゎ=V□2 ・・・・・・α荀(However, %
Il:) saturation voltage fi) of the transistor is established.

II +I、 =Io、、、、、、αeであるから となる。一方、利得Gは削成〇□に準じてとなり、上式
α優および創成Qeから となる。すなわち、上式−から分るように、利得制御特
性は近似的にトランジスタQ1の電流工1の一次式に依
存し、第3図中実線で示すようKIII形になる。
This is because II +I, =Io, , , , αe. On the other hand, the gain G is obtained according to the reduction 〇□, and is obtained from the above equation α Yu and the creation Qe. That is, as can be seen from the above equation, the gain control characteristic approximately depends on the linear equation of the current factor 1 of the transistor Q1, and becomes a KIII type as shown by the solid line in FIG.

なお、本発明は上記実施例に限られるものではなく、電
流源トランジスタQ3および定電流源21として、要は
ペース接地型の電流源トランジスタを用いてなる電流源
回路を設ければよい、同様に、ダミー回路22において
も電流源トランジスタQs’および定電流源21′とし
て要は電流源回路を設ければよい。
It should be noted that the present invention is not limited to the above-mentioned embodiment, and it is sufficient to provide a current source circuit using pace-grounded current source transistors as the current source transistor Q3 and the constant current source 21. Also in the dummy circuit 22, a current source circuit may be provided as the current source transistor Qs' and the constant current source 21'.

〔発明の効果〕〔Effect of the invention〕

上述したように本発明の利得制御増幅回路によれば、制
御電圧対利得特性を線形化できるので、デジタル機器に
おいて制御電圧をデジタル的に可変することにより、入
出力特性が線形のデジタル制御増幅回路を実現できるな
ど、適用範囲が広くなる利点がある。
As described above, according to the gain control amplifier circuit of the present invention, the control voltage vs. gain characteristic can be linearized, so by digitally varying the control voltage in a digital device, a digital control amplifier circuit with linear input/output characteristics can be created. It has the advantage of widening the scope of application, such as being able to realize the following.

【図面の簡単な説明】[Brief explanation of the drawing]

菖1図は従来の利得制御増幅回路を示す回路図、第2図
は本発明に係る利得制御増幅回路の一実施例を示す回路
図、第3図は第2図および第1図の制御特性を示す特性
図である。 Qs −Qs  e Qx’〜Qs”=)ランゾスタ、
DID′・・・ダイオード、RLIRL′・・・負荷抵
抗、11・・・信号出力端子、12・・・制御電源、1
3・・・バイアス電源、14・・・入力信号源、21.
21’・・・定電流源、22・・・ダミー回路。 出願人代理人  弁理士 鈴 江 武 彦第1図
Figure 1 is a circuit diagram showing a conventional gain control amplifier circuit, Figure 2 is a circuit diagram showing an embodiment of the gain control amplifier circuit according to the present invention, and Figure 3 shows the control characteristics of Figures 2 and 1. FIG. Qs −Qs e Qx′〜Qs”=) Lanzosta,
DID'...Diode, RLIRL'...Load resistance, 11...Signal output terminal, 12...Control power supply, 1
3... Bias power supply, 14... Input signal source, 21.
21'... constant current source, 22... dummy circuit. Applicant's agent Patent attorney Takehiko Suzue Figure 1

Claims (2)

【特許請求の範囲】[Claims] (1)信号出力用トランジスタQr と、このトランジ
スタQl と差動対をなすトランジスタQ!と、このト
ランジスタQ3のエミ、りと前記トランジスタQ1のエ
ミッタとの間に順方向に挿入接続されたダイオードDと
、このダイオードDと上記トランジスタQ1との接続点
と接地端との間に接続されペース接地型電流源トランジ
スタQsを用いてなる電流源回路と、前記トランジスタ
Q1およびQ3の各コレクタに対応して電源との間に接
続された負荷抵抗R5およびRL′と、前記トランジス
タQ1およびQlのペース間に挿入接続された電圧可変
型の制御電源12と、前記トランジスタQ1のコレクタ
の直流電圧を一定化するダミー回路22と、前記電流源
回路のトランジスタQ3のエミ、り側に入力信号を供給
する手段とを具備することを特徴とする利得制御増幅回
路。
(1) A signal output transistor Qr and a transistor Q that forms a differential pair with this transistor Ql! A diode D is inserted and connected in the forward direction between the emitter of the transistor Q3 and the emitter of the transistor Q1, and a diode D is connected between the connection point between the diode D and the transistor Q1 and the ground terminal. A current source circuit using a grounded current source transistor Qs, load resistors R5 and RL' connected to a power supply corresponding to the respective collectors of the transistors Q1 and Q3, and An input signal is supplied to a variable voltage control power supply 12 inserted and connected between the paces, a dummy circuit 22 that stabilizes the DC voltage of the collector of the transistor Q1, and the emitter and rear sides of the transistor Q3 of the current source circuit. 1. A gain control amplifier circuit comprising means for.
(2)前記ダミー回路22は、前記トランジスタQ3の
コレクタにコレクタが接続され前記トランジスタQ1の
ペースにペースが接続されるトランジスタQ、1と、こ
のトランジスタQ、/と差動対をなし前記トランジスタ
Qsのコレクタにコレクタが接続され前記トランジスタ
Qsのペースにペースが接続されるトランジスタQ寞′
と、このトランジスタQ、’llDエミッタと前記トラ
ンジスタ91′のエミ、りとの間に順方向に挿入接続さ
れたダイオードVと、このダイオードがと上記トランジ
スタQ、1の工<y夕との接続点と接地端との間に接続
される電流源回路とを具備することを特徴とする特許請
求の範囲第1項記載の利得制御増幅回路。
(2) The dummy circuit 22 forms a differential pair with a transistor Q,1 whose collector is connected to the collector of the transistor Q3 and whose pace is connected to the pace of the transistor Q1, and the transistor Qs. a transistor Q' whose collector is connected to the collector of and whose pace is connected to the pace of the transistor Qs;
and a diode V inserted and connected in the forward direction between the emitter of this transistor Q,'llD and the emitter of the transistor 91', and this diode is connected to the emitter of the transistor Q,1. 2. The gain control amplifier circuit according to claim 1, further comprising a current source circuit connected between the point and the ground terminal.
JP4410482A 1982-03-19 1982-03-19 Gain control amplifying circuit Pending JPS58161513A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4410482A JPS58161513A (en) 1982-03-19 1982-03-19 Gain control amplifying circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4410482A JPS58161513A (en) 1982-03-19 1982-03-19 Gain control amplifying circuit

Publications (1)

Publication Number Publication Date
JPS58161513A true JPS58161513A (en) 1983-09-26

Family

ID=12682300

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4410482A Pending JPS58161513A (en) 1982-03-19 1982-03-19 Gain control amplifying circuit

Country Status (1)

Country Link
JP (1) JPS58161513A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0220109A (en) * 1988-07-08 1990-01-23 Sony Corp Variable gain amplifier
US5949286A (en) * 1997-09-26 1999-09-07 Ericsson Inc. Linear high frequency variable gain amplifier

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0220109A (en) * 1988-07-08 1990-01-23 Sony Corp Variable gain amplifier
US5949286A (en) * 1997-09-26 1999-09-07 Ericsson Inc. Linear high frequency variable gain amplifier

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