JPS6024707A - Bias circuit - Google Patents

Abstract

PURPOSE:To prevent the fluctuation of AGC DC due to a power source voltage by enabling to supply a bias current which is not influenced by the fluctuation of power source voltage even when the power source voltage of a level shift circuit of a linear integrated circuit is fluctuated. CONSTITUTION:The base potential VB5 of a TRQ5 is set to a specified potential by a series circuit of diodes D1, D2 and a resistance R6 connected to the collector of the transistor (Tr) Q5, and a emitter current IE5 of TrQ5 attains to a value obtained by dividing the difference between the emitter potential VE6 of TrQ6 and the emitter potential VE5 of TrQ5 by a resistance R8. The potential difference between VE6 and VE5 is nearly equal to the difference between base potential VB6, VB5 of Tr Q6 and Q5, and potential difference between VB6 and VB5 is equal to the forward voltage drop VJ of a diode D3. Accordingly, the emitter current of TrQ5 goes to VJ/R8, and the emitter current IE5 hardly depends on the power source voltage VCC.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a bias circuit, and particularly to a bias circuit suitable for use in a level shift circuit of a linear integrated circuit.

[Technical background of the invention]

In general, linear integrated circuits that have a circuit structure that amplifies, modulates, and performs various processing on continuously changing analog amounts of voltage and current are bipolar integrated circuits formed using bipolar transistors. is used.

By the way, when various functional elements such as amplification and detection are to be integrated, they are often directly connected in a direct current manner because of the restriction on the number of bins and the inability to incorporate a large capacity. Therefore, when several stages are directly connected, in order to match the DC level between stages,
A level shift circuit is required.

Therefore, conventionally, the output signal Vl of the preceding functional element is level-shifted using a level shift circuit as shown in FIG.
The output level Vout was applied to the input terminal of the subsequent stage element.

In FIG. 1, the output v of the previous stage element to be level shifted
1 is applied via input 1 to the base of transistor Q1. The collector of transistor Q1 is connected to power supply terminal 2 to be supplied with power supply voltage VCC, and the emitter of transistor Q1 is connected to the collector of transistor Q2 via resistor R1, and the emitter of transistor Q2 is connected to resistor R2. grounded via. Also,
The base of transistor Q2 is connected to the emitter of transistor Q3 and grounded via resistor R3, and the base of transistor Q3 is further connected to the base of transistor Q4. The collector of the transistor Q3 is connected to the power supply terminal 2, and the base thereof is connected to the power supply terminal 2 via the resistor R4.
connected to the collector. The emitter of transistor Q4 is grounded via resistor R5. The level-shifted signal Vout appears at the connection point between the resistor R1 and the collector of the transistor Q2, is taken out from the output terminal 3, and is applied to the input terminal of the next stage element.

On the left, an NPN transistor is used for transistor Qx=Q4.

In such a configuration, in the case of an integrated circuit, it is assumed that the characteristics of each transistor Ql-Q4 are uniform, and the resistor R1'' R
If a value of 5 is selected, since the transistor Q2 and the transistor Q4 have a current mirror configuration, the collector current of the transistor Q2 approximately reaches the collector current of the transistor Q4 in an equilibrium state. Therefore, in this case, the emitter current IE1 of the transistor Q1 and the emitter current IE4 of the transistor Q4 are also approximately equal.

In this circuit, the input level v1 applied to the input terminal 1 is the voltage IEI・R1 (= VLS ) at the resistor R1.
The signal is level-shifted by the amount and is taken out from the output terminal 3.

[Problems with background technology]

However, the above conventional circuit has the following problems.

In the above circuit, if the voltage between the base and emitter of the transistor is VJ, then the emitter current IE4 of the transistor Q4 is as follows. Therefore, the emitter current IE4 of the transistor Q4 is proportional to Vcc 2VJ, and as a result, due to the current mirror effect, the bias current, that is, the emitter current IEI of the transistor Q1 is also proportional to VCC-2VJ. It becomes dependent. Therefore, the level shift amount VLS also does not depend on the power supply voltage VCC, and the voltage VLS fluctuates in response to changes in the power supply voltage VCC. For example, in the circuit shown in Figure 1, resistor 3%1 = 4Ω, R2 = R5 = 3Ω
, R3= IOKΩ, Rs= 33Ω, vcc=
5v.

If VJ-0.7V, the level shift voltage VLS is
= 0.4 (v). Also, only the power supply voltage Vcc is changed, Vcc = 7
If V, then VLS = 0.62 (V), which is 55% of the VLSO value at Vcc-5v.
will increase. For this reason, a circuit in which it is not preferable for the level shift voltage VLS to be affected by fluctuations in the power supply voltage Vcc, for example, an AG that detects the voltage based on the voltage VLS,
The C (automatic gain control) circuit has a problem in that fluctuations in the power supply voltage Vcc appear as fluctuations in the DC level of the AGC voltage.

[Purpose of the invention]

In view of the above points, the present invention provides a bias circuit in which the bias current is not affected by fluctuations in the power supply voltage, and therefore, for example, in a level shift circuit, the level shift voltage is not affected by fluctuations in the power supply voltage. The purpose is to provide

[Outline of the invention]

The bias circuit of the present invention includes a DC power supply that supplies a power supply voltage, a first diode whose anode is connected to the DC power supply through a first resistor, and whose cathode is grounded through a second resistor. a first transistor whose emitter is connected to the DC power supply through a third resistor, whose base is connected to the anode of the first diode and whose collector is grounded; a second transistor connected to the emitter of the first transistor, the base connected to the cathode of the first diode, and the collector grounded through a series circuit consisting of a second diode, a third diode, and a fifth resistor; By configuring a circuit equipped with the above-mentioned circuit and further configuring a current mirror circuit using this circuit, a current corresponding to the emitter current of the second transistor is generated, and a bias current independent of the power supply voltage is supplied. It is.

[Embodiments of the invention]

Embodiments of the present invention will be described below based on the drawings.

FIG. 2 is a circuit diagram showing an embodiment of a level shift circuit using a bias circuit according to the present invention.

In this figure, the same reference numerals as in FIG. 1 indicate the same or corresponding parts.

In FIG. 2, an input v1 with a level shift of t is applied to the base of the transistor Qs via the input terminal 1. The collector of transistor Ql is connected to power supply terminal 2 and supplied with power supply voltage VCC. Furthermore, the emitter of transistor Q1 is connected to the collector of transistor Q2 via resistor R1, and the emitter of transistor Q2 is grounded via resistor R2. Transistor Q2
The base of the transistor Qa is connected to the emitter of the transistor Qa, and the other end is grounded through a resistor R2. The collector of the transistor Q3 is connected to the power supply terminal 2, and the base thereof is connected to the collector of the transistor Q5 and grounded via a series circuit of diodes Di, D2 and a resistor R6. The emitter of transistor Q5 is connected to power supply terminal 2 via series-connected resistors R7 and Rs. The emitter of a transistor Q6 is connected to the connection point between the resistors R7 and R8, and its collector is grounded. A diode D3 is connected between the base of the transistor Q6 and the base of the transistor Q5, and the base of the transistor Q6 is further connected to the power supply terminal 2 via the resistor R1, and the base of the transistor Q5 is connected to the power supply terminal 2 through the resistor R1.
The base of is grounded via a resistor RIG. The level-shifted signal appears at the connection point between the resistor R1 and the collector of the transistor Q2 and is taken out from the output terminal 3. Note that NPN) transistors are used for the transistors Q1 to Q3, and PN transistors are used for the transistors Qs and Qs.
P) A transistor is used.

In such a configuration, the base potential VB5 of the transistor Q5 is set to a predetermined potential by the series circuit of the diode D□sDz and the resistor R6 connected to the collector of the transistor Q5, and the emitter current I of the transistor Q5 is set to a predetermined potential.
E5 is the difference between the emitter potential VE6 of the transistor Q6 and the emitter potential VE5 of the transistor Q5 divided by the value of the resistor R8. The potential difference between VB2 and VB2 is approximately the base potential V of transistors Qa and Qs.
B6 , VB5 is equal to the /D difference, and the potential difference between VB6 and VB5 is equal to the forward voltage drop VJ of diode D3. Therefore, the emitter current IE5 of transistor Q5
is \, and the emitter current IE5 hardly depends on the power supply voltage VCC. On the other hand, transistors Qa+Q,
Since the base potential of the transistor is set to a predetermined potential, if the characteristics of each transistor are made uniform and the value of each resistor is selected, transistor Q5 and transistor Q2 will have a current mirror configuration, and the emitter current IE5 of transistor Q5 will be approximately Therefore, it becomes the emitter current IEI of the transistor Q1. Therefore, resistance ■1. Level shift voltage VLS generated in
is almost no longer dependent on the power supply voltage vcc,
For example, in an AGC circuit using this level shift circuit, A
The DC level of the GC voltage is almost unaffected by fluctuations in the power supply voltage.

FIG. 3 is a circuit diagram showing another embodiment of the present invention, in which a resistor R1s and a diode D3 are connected between the base of the transistor Q6 and the base of the transistor Q5 shown in FIG.
A plurality (n) of r. That is, in this circuit, if the forward voltage drop of the diode is VJ, then the emitter current of transistor Q5 can be changed by changing resistors R11 and n in addition to resistors R9 and RIO. I
The dependence ratio of E5 on the power supply voltage Vcc can be changed. Note that the circuit shown in FIG. 2 is connected to R1 in FIG.
This corresponds to the case where 1=0 and n=1. For example, in the circuit shown in FIG. 3, n = 2, R, , =6 has Ω, and R9 = 10 has Ω, R,. When Ω is set to =20, IE5= 0.0083VCC+ 0.0833VJ
The level shift voltage VLS is set to R1=4 and Ω, Vt, s=&sIgs== 0.0332VCC+0
．． 3332 Becomes VJ. Also, in this case, V
J2 0.7V.

When vcc = 5 V, VLS = 0.4 (V), and when Vcc = 7 V, VLS = 0.466 (V), which is 16. compared to the value of VLS when Vcc = 5 V.
This will be an increase of 5%. It can be seen that this variation rate is significantly reduced compared to the variation rate of 55 described for the circuit of FIG.

〔Effect of the invention〕

As described above, according to the present invention, even if the power supply voltage fluctuates, it is possible to supply a bias current that is not affected by the fluctuation. Therefore, for example, in a level shift circuit in an AGC circuit, the AGC DC level changes depending on the power supply voltage. This makes it possible to avoid this problem and enable a suitable circuit design.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing a level shift circuit using a conventional bias circuit, Fig. 2 is a circuit diagram of a level shift circuit using a bias circuit showing an embodiment of the present invention, and Fig. 3 is a circuit diagram showing a level shift circuit using a bias circuit according to an embodiment of the present invention. FIG. 7 is a circuit diagram of a level shift circuit using a bias circuit showing another embodiment. R9...first resistor, D3...first diode,
R.I. ...Second resistance, vcc...Power supply voltage, R7...
Third resistor, R8... Fourth resistor, Q6... First transistor, Dl... - Second diode, D2...
・30th diode, R6...5th resistor, Qs...
- Second transistor, Ql-Q3...transistor, R, ~R3...resistance. Agent Patent Attorney Kensuke Chika (and 1 other person) Figure 1 Figure 2

Claims (1)

[Claims] a DC power supply that supplies a power supply voltage; a first diode whose anode is connected to the DC power supply through a first resistor and whose cathode is grounded through a second resistor; and an emitter connected to a third resistor. a first transistor connected to the DC power supply through a fourth resistor, a base connected to the anode of the first diode, and a collector grounded; and an emitter connected to the emitter of the first transistor through a fourth resistor. The base is connected to the cathode of the first diode, and the collector is connected to the cathode of the first diode. A circuit including a third diode and a second transistor grounded through a series circuit including a fifth resistor is configured, a current mirror circuit is configured using this circuit, and the second transistor is connected to the second transistor. A bias circuit characterized in that it generates a bias current that is independent of a power supply voltage and corresponds to an emitter current of.