JPH0255972B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an interface circuit that performs level conversion between input and output circuits.

Generally, an interface circuit that performs level conversion is required between circuits such as logic circuits that operate at different voltage levels. For example, I ² L (Integrated
−Injection Logic) and ECL (Emitter Coupled
This is the case when the ECL operation is controlled by the signal from I ² L in an IC in which each logic circuit (Logic) is integrated on a single chip. In this case, the DC voltage for circuit operation of ^I2L is at a low potential near the ground potential (GND), whereas ECL operates at a high potential near the power supply potential because it operates in a non-saturated manner. Therefore, a level conversion interface circuit is required between the two.

Such an interface circuit usually
As shown in the figure, there are parallel emitter-grounded bipolar transistors (hereinafter simply referred to as transistors) Tr ₁ and Tr ₂ on the ground side between the power supplies (between Vcc and GND).
At the bases of these transistors Tr ₁ and Tr ₂ , I ² L
An input signal IN and its inverted signal are supplied from input circuits such as . Furthermore, the emitter currents of the transistors Tr ₃ and Tr ₄ are supplied to the collectors of the transistors Tr ₁ and Tr 2 via the resistors R ₁ and R ₂ , respectively, and the transistors Tr ₃ and _{Tr 4 are} connected to the ECL A predetermined bias voltage V ₀ from an output circuit such as the like is supplied to each base. And these transistors Tr ₃ and Tr ₄
The power supply Vcc is supplied to each collector through resistors R ₃ and R ₄ , and the ECL
An output signal Q ₁ and its inverted signal Q ₂ having voltage levels corresponding to the circuit operation of the output circuit are generated.

With such an interface circuit,
In response to an input signal IN whose reference potential is at a low level from an input circuit such as I ² L, output signals Q ₁ and Q ₂ whose reference potential is at a high level can be supplied to an output circuit such as ECL. However, if the input circuit is a saturated operation circuit like the above I ² L, the transistor
Due to the influence of the saturation accumulation time t _stg of Tr ₁ and Tr ₂ , a time delay occurs when transistors Tr ₁ and Tr ₂ turn from on to off, and as a result, the output to the output circuit changes as shown in Figure 2. Signal Q ₁ and its inverse signal
Q ₂ becomes unsynchronized, resulting in an unstable signal. In addition, in order to solve such drawbacks, the first
The input signal in the interface circuit shown in the figure
A resistor instead of the transistor Tr ₂ supplied with IN
Rx is provided, and as shown in Figure 3, an output signal Q ₂ to be supplied to an output circuit such as ECL is generated as a reference signal of a constant voltage level, and the above output is output according to the level of output signal Q ₁ with respect to this signal Q ₂ . There are ways to make the circuit operate. However, in such a method, when a variation in the saturation voltage Vsat ₁ of the transistor Tr ₁ occurs due to a variation in the power supply Vcc or heat generation, the voltage level of the output signal Q ₂ serving as a reference signal and the corresponding output signal Q ₁ The amount of variation in the voltage level of each voltage level is different. Therefore, relative to output signal Q ₂ at the reference level, output signal Q ₁
The disadvantage is that the level of

An object of the present invention is to stably output an output signal that is a reference level and an output signal that has a certain level difference with respect to the reference level, even when power fluctuations occur, in accordance with the input signal from the input circuit. The object of the present invention is to provide an interface circuit that can always stably perform input/output level conversion operations.

An embodiment of the present invention will be described below with reference to the drawings. FIG. 4 is a circuit diagram showing the configuration of the interface circuit of the same embodiment. As shown in FIG. 4, in the circuit of the same embodiment, transistors Tr ₁ and Tr ₂ having the same saturation characteristics are provided in parallel.
A constant current I from constant current sources 11 and 12 is supplied to each base of the transistors Tr ₁ and Tr ₂ .
A bias voltage Vi from an input circuit such as I ² L is applied to the constant current sources 11 and 12, for example. Furthermore, the input signal IN from the input circuit is connected to the base of transistor Tr ₁ by a gate circuit (inverter).
It is input via G.

On the other hand, transistors Tr ₃ and Tr ₄ operate with a predetermined bias voltage V ₀ from an output circuit such as ECL.
is provided. Bias voltage V ₀ is applied to each base of transistors Tr ₃ and Tr ₄ .
The transistors Tr ₃ and Tr ₄ have the same characteristics, and are configured to output output signals Q ₁ and Q ₂ at a predetermined voltage level from their respective collectors to the output circuit.

Next, the operation of this embodiment will be explained. When the input signal IN is input from the input circuit, the gate circuit G generates a signal as shown in Fig. 5 according to the input signal IN.
It will output G ₀ . Depending on the level (H or L) of this signal _G0 , the transistor _Tr1 operates to be on or off. First, when the signal _G0 changes to the "H" level, a constant current I is supplied from the constant current source 11 to the base of the transistor _Tr1 , and the transistor _Tr1 is turned on. At this time, since the same constant current I is supplied from the constant current source 12 to the base of the transistor Tr ₂ , the transistor Tr ₂ is also in an on state. At this time, assuming that the transistors Tr ₃ and Tr ₄ have the same characteristics, _the collector currents Ic ₁ and Ic ₂ of the transistors Tr ₁ and Tr ₂ are as follows.

Ic ₁ = V ₀ −Vsat ₁ −V _BE3 /R ₁ ...(1) where R ₁ : Resistance value of resistor R ₁ Vsat ₁ : Saturation collector voltage of transistor Tr ₁ V _BE3 : Base voltage of transistor Tr ₃
It is the voltage between emitters. If the resistance R ₁ and the resistance R ₂ have the same value, the collector currents Ic ₁ and Ic ₂ have the same value. Therefore, transistors Tr ₁ and Tr ₂ have the same saturated collector voltage Vsat ₁ , and both make the same change in response to the input signal. And above (1)
Therefore, the levels of the output signals Q ₁ and Q ₂ at this time are Q ₁ = Vcc−R ₃ · Ic ₁ ...(2) Q ₂ = Vcc−R ₃ /2 · Ic ₂ ...(3), Here, R ₃ : resistance value of resistor R ₃ R ₃ /2: resistance value of resistor R ₄ . The level of this output signal _Q2 serves as a reference voltage signal for an output circuit such as an ECL, and a voltage at a constant level is always supplied to the output circuit. Furthermore, as shown in FIG. 5, when the gate circuit G is in the on state, that is, the output signal _G0 of the gate circuit falls (L level) and the transistor _Tr1 is in the off state, the output signal _Q1
The level of is almost the same as the power supply Vcc.

In this way, by setting the resistance values of the resistors R ₁ to R ₄ to predetermined values, the operation reference signal (output signal Q ₂ ) of the output circuit such as ECL is set in advance,
Using this signal Q ₂ as a reference, an output signal Q ₁ having a predetermined logic amplitude necessary for an output circuit such as ECL is generated in response to an input signal IN from an input circuit such as I ² L.
By the way, since the transistors Tr ₁ and Tr ₂ have the same saturation characteristics, for example, when a fluctuation occurs in the power supply Vcc, the amount of level fluctuation of the output signals Q ₁ and Q ₂ becomes almost the same. Therefore, the level difference of the output signal Q ₁ is always constant relative to the output signal Q ₂ at the reference level. As a result, even if fluctuations in the power supply or the like occur, it is possible to always achieve stable input/output level conversion operations.

Note that each level of the output signals Q ₁ and Q ₂ is calculated using the above formula.
As is clear from (1) to (3) etc., the transistor Tr ₁
It is determined by the characteristics of Tr ₄ and the resistance values of resistors R ₁ to R ₄ .

FIG. 6 shows the output signals Q ₁ ,
This is an interface circuit in which the level of _Q2 is shifted by a diode. i.e. resistance
The power supply Vcc is supplied to R ₃ and R ₄ via the diode D, and thereby the levels of the output signals Q ₁ and Q ₂ are lowered by the voltage drop across the diode. Furthermore, in the above embodiment, the transistor
As mentioned above, a current I is applied to each base of Tr ₁ and Tr ₂ .
is supplied via constant current sources 11 and 12,
Bias resistors R ₅ and R ₆ connected to the bases of transistors Tr ₃ and Tr ₄ may be used as this constant current source. This circuit also has the same effect and operation as the interface circuit shown in FIG. 4, so the same reference numerals will be used and the explanation will be omitted.

As detailed above, according to the present invention, an output signal serving as a reference level and an output signal always having a constant level difference (logical amplitude) with respect to the reference level are output in accordance with the input signal from the input circuit. Can be output to the circuit. Therefore, even if power supply fluctuations occur, stable input/output level fluctuation operation can always be realized.

[Brief explanation of the drawing]

Figure 1 is a configuration diagram of a conventional interface circuit, Figure 2 is a diagram showing its timing chart,
FIG. 3 also shows the timing chart, FIG. 4 is a configuration diagram of an interface circuit according to an embodiment of the present invention, FIG. 5 shows a timing chart thereof, and FIG. FIG. 2 is a configuration diagram of an interface circuit according to an embodiment of the present invention. Tr ₁ ~ Tr ₄ ...Bipolar transistor, R ₁ ~ _{R 6}
...Resistor, 11, 12... Constant current source, D... Diode.

Claims (1)

[Claims] 1. A first bipolar transistor with a grounded emitter, which is provided between power supplies and operates by a constant current supplied to the base in response to an input signal from an input circuit; a second bipolar transistor with a grounded emitter that has the same saturation characteristics and is provided in parallel between the power supplies and operates by supplying a constant current having the same current value as the constant current to the base; An emitter is connected to the collector of the transistor via a first resistor, and the collector is connected to a power supply via a second resistor.
It is operated by a predetermined voltage from the output circuit supplied to the base, and outputs an output signal of a predetermined reference voltage level determined based on the resistance values of the first and second resistors from the collector to the output circuit. a third bipolar transistor for output; an emitter connected to the collector of the first bipolar transistor via a third resistor, the collector having a resistance value approximately twice the resistance value of the second resistor; It is connected to the power supply via a fourth resistor, operates with a predetermined voltage from the output circuit supplied to the base, and changes its level in accordance with the input signal to create a predetermined level difference with respect to the reference voltage level. and a fourth bipolar transistor that outputs an output signal from the collector to the output circuit.