JPS5821790A - Display stabilization circuit for still picture display - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a screen and display device that transmits a signal in synchronization with the output of a synchronization signal generator. The present invention relates to a display stabilizing circuit that prevents display surface disturbance caused by.

The still image display device includes a synchronization signal generator that generates a horizontal synchronization signal HD and a vertical synchronization signal VD using the output of a reference oscillator, and counts the branch output of the reference oscillator as a display clock, thereby increasing the image memory. It is equipped with a horizontal display counter and a starting display counter for addressing and displaying a stationary l111g1 display signal, and the counter and horizontal display counter that divide and cycle the output of this reference generator l111g1 are output from the synchronizing signal generator. The horizontal and vertical deflection counters are reset by the output horizontal synchronization signal, and the vertical movement counter is reset by the vertical synchronization signal, thereby synchronizing the horizontal and vertical deflection with the still image display signal read from the image memory. .

In this case, since the synchronization signal generator is composed of an MO8 integrated circuit, the output signal will drift to some extent as the internal temperature rises. In particular, the drift of the horizontal synchronization signal HD will cause This will cause jitter in the display. In other words, when the counter that divides the output of the reference oscillator and outputs the display clock counts up at the rising edge of the input signal, the horizontal synchronization signal output from the synchronization signal generator will fall on the rising edge of the oscillation output. When synchronized, the reset position of the frequency division counter fluctuates by one force count due to the drift of this horizontal synchronization signal.

In this way, when the reset condition of the frequency division counter changes, the count value of the horizontal display counter, which counts the output of this division counter as the display clock, will also fluctuate with respect to the horizontal deflection, and this fluctuation will cause the horizontal direction on the screen to fluctuate. This appears as jitter.

Accordingly, one object of the present invention is to provide a display stabilization circuit for a still image display device that prevents the drift of the horizontal synchronization signal output from the synchronization signal generator from appearing as jitter on the display screen. .

To achieve this purpose, the present invention uses the horizontal synchronization signal output from the synchronization signal generator and the oscillation output of the reference oscillator as input, and detects the coincidence between the count-up operation position and the reset operation position of the frequency division counter. A working position-diffusion output circuit is provided, and when the working position-diffusion output circuit detects a match, a phase inverted output of the reference oscillation output is supplied to the branch counter. This is to avoid being affected by the

Hereinafter, a display stabilizing circuit in a still image display device according to the present invention will be described in detail using embodiments shown in the drawings.

FIG. 1 is a circuit diagram showing an embodiment of a display stabilizing circuit in a still-image display device according to the present invention. In the figure, numeral 1 is a reference oscillator, which sends out a p-clock pulse OK based on a reference signal of, for example, 286 MHz. A synchronizing signal generator configured by a 2H MO8 integrated circuit, the reference oscillator l
A horizontal synchronizing signal HD and a vertical synchronizing signal VD are generated by inputting a reference clock pulse OK supplied from the oscillator. 3 inputs the reference clock pulse 0KILA, inputs the reference clock OK' which has been inverted and has an opposite phase by input 4, and selects the A input by the select signal 10m supplied to the control input terminal 8. At the same time, @1m selects the B input and sends it out from the output terminal Y. 5 is a 5-base counter for dividing the frequency, and 6 is a 5-base counter that counts the output of selector 3 while being reset by the horizontal synchronization signal HD4C. Counts the display clock DK output from 5 and horizontal synchronization signal HD.
7 is a vertical display counter that counts the display clock DK and is reset by Fucho Shikibo VD; 8 is a vertical display counter that counts the display clock DK and is reset by the output of the horizontal display counter 5 and vertical display counter 6; This is an image memory from which image information is read out. On the other hand, reference numeral 9 denotes a working position-integration output circuit which detects the coincidence of the working position of the reference clock pulse OK for the 5-way counter 5 and the working position of the horizontal synchronization signal HD for the 5-way counter 5. It is constituted by extraction circuits such as differentiating circuits 9m and 9b for extracting the rising edge of each of the OK and horizontal peer signals HD, and an AND gate 11 for detecting coincidence of the differential outputs respectively output from both circuits. Here, as mentioned above (・:
・Since the differentiating circuits 9m and 9b need only extract the rising edges of the reference clock pulse OK and the horizontal synchronizing signal HD, for example, a pair of circuits that are kicked at the rising edges of the reference clock pulse OK and the horizontal synchronizing signal HD, respectively, is sufficient. This differential circuit wI9a * 9b can be formed by a mono multi-no 9 ibrator of A pair of two-man AND gates may be provided to apply the synchronizing signal HD to one of the input terminals after being slightly delayed through the input terminal. 12 is a Frizzo 70 circuit that constitutes a holding circuit. By supplying the 111 signal set by the output of the AND gate 11, reset by the initial reset signal IR, and sent from the set output terminal Q to the control input terminal S of the selector 3, the signal is sent to the B input terminal. Select the supplied inverted, 4 quasi-clock pulse OK'.

In the display stabilizing circuit in the still image display device configured as described above, when the power is turned on, an initial reset signal IR is generated and the ARITZO 70 TZO circuit 12 is reset. In the reset state of the slip-flop circuit 12, its set output terminal is p, 6''°, so the selector 3 selects the input terminal A@ and outputs it.

In this state, when the reference oscillator 1 generates the reference clock/cells OK shown in FIG. 2(a)K.

The inverter 4 outputs a reference clock pulse OKI, which is obtained by inverting the phase of the reference clock pulse OK, as shown in FIG. 2(b). First, when the synchronous signal generator 2 inputs the standard reference a tsuknogles OK, the synchronization signal generator 2 generates the signal shown in Fig. 2 (
Horizontal synchronization signal) ID and vertical synchronization signal VD shown in c)
form and output. In this case, since the differentiating circuits 9m and 9b of the operating position/integration output circuit 9 are for differentiating the horizontal synchronizing signal HD and the reference clock pulse OK, the horizontal synchronizing signal HD and the horizontal synchronizing signal HD and the reference clock pulse OK shown in FIG. , second
If only the differential output that coincides with the rising 9 portion of the reference p-sock pulse OK shown in the figure (,) is taken out, then K is obtained.

In this case, h'''ca is the point of action of the counting operation on the input signal of the s-adic counter 5, that is, the rising edge of the reference clock 7 OK and the rising edge of the horizontal synchronizing signal HD, which is the point of action of resetting the counter 5. The upper and lower time points do not match, and in this state, even if the horizontal synchronizing signal HD fluctuates somewhat, the count start of the quinary counter 5 is fixed at time t1.Therefore, from the quinary counter 5,
The quinary count output shown in Figure 2(d) is displayed.
It is output as K. The horizontal display counter 6 and the vertical display counter 7 convert the display clock DK output from the quinary counter 5 into a horizontal synchronization signal HD and a vertical synchronization signal VD.
By counting while being reset by and addressing the image memory 8 by the count output,
Image information is read out in synchronization with the horizontal and vertical synchronization ID and VD.

Next, when the generation of the horizontal synchronizing signal HD output from the synchronous No. 16 generator 2 coincides with the rising edge of the reference clock pulse OK as shown in FIG. 2(e), the drift of the horizontal synchronizing signal HD As a result, the counting start point of the quinary counter 5 will vary over one period of the reference clock pulse OK, and such conditions must be avoided.

In this case, the differential circuits 9m, 9 of the action position-scattering output circuit 9
b differentiates the horizontal synchronizing signal HD and the reference 4-pulse OK, and its positive differential output is connected to the diodes 10m and 10b.
This diode 10m
, 10b inputs the output of ANDG) 11 becomes "l". In this way, the coincidence of the operating positions, that is, the fluctuation of the horizontal synchronizing signal HD, is a condition that greatly affects the counting operation of the quinary counter 5. is detected and the @1-(PL signal is output from the AND gate 11, the Frizzo 70 circuit 12 is set and continues to maintain that state. When the Frizzo 70 circuit 12 is set, the set Since the output @10 is supplied to the control input 8 of the selector 30, this selector 3 receives the reference clock pulse OK shown in FIG. 2(b) inverted by the inverter 4.
' Select and output. As a result, the rising point of the horizontal synchronizing signal HD supplied as a reset signal to the 5-ary counter 5 is the falling point of the reference clock pulse OK' as a counter input, and even if the horizontal synchronizing signal HD fluctuates a little, This will be a relationship that will not be affected in any way. In this case, the quinary counter 5 sequentially discloses the count from the start-up time at the time t1 of the reference clock signal OK/ shown in FIG. The count output shown in f) is output as the display clock DK.

Therefore, in the circuit configured as described above, when a condition in which the drift of the horizontal synchronizing signal VD greatly affects the counting operation of the 5-way counter is detected by the active position-scattering/accumulating circuit, the 5-way counter By inverting the phase of the reference clock pulse OK supplied as a count input, the coincidence of the operating positions is automatically shifted.

In the above example, the horizontal synchronizing signal HD of the 5-ary counter and the count input are all applied at the rising edge, but this is not limiting, and the falling edge t9 is A combination of a rising edge and a falling edge may be used, and it goes without saying that in this case, it is necessary to change the extraction of the differential curve and the detection of coincidence in accordance with these conditions. Further, the counter that divides the reference clock pulse is not limited to a quinary one, but any counter that can obtain a display clock DK with a predetermined period in relation to the oscillation period of the reference oscillator 1. good.

As explained above, the display stabilization circuit in the still image display device according to the present invention divides the reference clock pulses into horizontal and vertical display counters by counting them while being reset by the horizontal synchronization signal. Since the input to the counter that supplies the horizontal synchronization signal is automatically shifted so that the reset time by the horizontal synchronization signal and the count time do not match, the horizontal synchronization signal output from the synchronization signal generator may drift slightly. It has the advantage of providing stable and good images at all times without affecting the displayed image.

[Brief explanation of drawings]

FIG. 11 is a circuit diagram showing an embodiment of a display stabilizing circuit in a still image display device according to the present invention, and FIGS.
) are operation waveform diagrams of each part in FIG. 1. 1... Reference oscillator, 2... Synchronization signal generator, 3...
・Selector, 4... Inputer, 5... Quintal counter, 6... Horizontal display counter, 7... Vertical display counter, 8... Image memory, 9... Action position. Scatter-product output circuit, 12... fritzoflop circuit.

Claims (1)

[Claims] (1) a synchronization signal generation circuit that receives a reference clock pulse and generates a horizontal synchronization signal and a vertical synchronization signal;
When the reference cropping signal is counted while being reset by the horizontal synchronization signal, a counter that divides into K and sends out a display pk, and a counter that counts the display pk supplied from the counter and outputs an image memory. In a still image display device equipped with horizontal and vertical display counters that read out still image information by addressing the counter, a reset operation is performed by a runt-up action position and a horizontal synchronization signal of a reference base, a pick, and an arm for the counter. A still image comprising: an action position coincidence detection circuit for detecting position coincidence; and a selector activated by a coincidence detection output of the action position coincidence detection circuit to select an opposite phase signal of the reference clock and supply it to the counter. Display stabilization circuit in display device,