JPS58213447A - Semiconductor device - Google Patents

Abstract

PURPOSE:To keep an insulated P<+> region at minimum potential sufficiently extending over the whole IC by forming the insulated region in a pattern separate from a buried P<+> region diffused into a semiconductor substrate in a double diffusion insulating system. CONSTITUTION:Buried N<+> regions 12 and buried P<+> regions 13 are formed onto the substrate 11. When an epitaxial layer 14 of an N type semiconductor is grown onto the substrate 11, the buried P<+> region 13 is not formed in a region 17, in which an element is not formed, as much as possible in order to reduce the effect of a P type impurity. The epitaxial layers 14 are grown onto the substrate 11. The high-concentration P type impurity is diffused from the upper sections of the epitaxial layers 14 to form the insulated P<+> regions 15. An element region is insulated and isolated completely through the diffusion. The P type impurity in the insulated P<+> regions 15 is widened sufficiently.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to semiconductor devices, and particularly to insulation and isolation of semiconductor integrated circuits.

As one method for forming electrically independent element regions in a semiconductor integrated circuit (hereinafter abbreviated as IC), a double diffusion method is used as shown in FIG. This is p
A buried n+ region is formed in a semiconductor substrate l, and at the same time, p-type impurities (hereinafter referred to as buried p+ region) similar to those of the substrate are also formed at certain intervals in the buried n+ region. An n-type epitaxial layer 4tl- is formed on the substrate, and a p-type impurity (hereinafter referred to as an insulating p+ region) is buried from above the epitaxial layer in the same region as the surface on which the buried p+ region is formed. Spread to reach territory. The portion above the buried n-region becomes the epitaxial layer 4 in which the element is placed. In this insulation isolation method, before forming the n-type epitaxial layer, the insulating region (region without elements) of the p-type substrate is
Since the high-concentration type impurity is diffused, the high-concentration p-type impurity of the layer is re-diffused into the epitaxial layer during the formation of the n-type epitaxial layer and disturbs the impurity concentration of the epitaxial layer. If the proportion of #1 increases, the re-diffusion will increase, making it difficult to control the impurity in the epitaxial layer. In severe cases, it will reverse and become p-type. Conventionally, as a countermeasure to this problem, a batten design was performed so that the buried p-region for element isolation and the insulating p-region were made as small as possible. That is, in the epitaxial region 7 where no element is included, there is no buried p+ region or insulating p+ region.

Normally, the insulating p-type region of an IC is set to the lowest potential, but in conventional methods, the resistance between the lowest potential electrode and the lowest potential electrode is higher in the area separated from the lowest potential. Therefore, it was not possible to sufficiently suppress the potential to the lowest level.

An object of the present invention is to provide an IC in which the influence of highly concentrated p-type impurities on a p-type substrate on an epitaxial layer is eliminated, and an insulating region is sufficiently maintained at the lowest potential over the entire IC.

A feature of the present invention is that a layer containing impurities of a second conductivity type formed on a semiconductor substrate of a first conductivity type is separated into multiple element regions by regions of the first conductivity type existing above and below the layer. In a semiconductor integrated circuit having such a structure, the planar area occupied by the first conductive region in the upper part of the layer is larger than the planar area of the first conductive type region in the lower part of the layer.

In the present invention, in the double diffusion insulation method, the insulating p+ region diffused from above the engineered taxial layer and the buried p+ region diffused into the semiconductor substrate have a different pattern. That is, the area of the buried p+ region is made as small as possible, and the insulating p region is made into most of #1 regions other than the element region. According to the invention, therefore:
While using the double diffusion method, the re-diffusion of impurities into the epitaxial layer can be minimized, and the wide dielectric strength region can uniformly maintain the insulating region of the IC at the lowest potential.

Examples will be described below using the drawings.

An example is shown in FIG. A buried n+ region 2 and a buried p+ region 3 are formed on the substrate 11. When growing the epitaxial layer 14, which is an n-type semiconductor, on the substrate 11, p
In order to reduce the influence of type impurities, the buried p+ region 13 is not placed in the region 17 where no element is placed, as in the conventional case. An epitaxial layer 14 is formed on this substrate 11.
grow. Next, a high concentration p-type impurity is diffused from above the epitaxial layer 14 to form an insulating p-type region 15.

This diffusion completes the isolation of the element region.

The p-type impurity in the insulating p-region 15 is sufficiently wide so as not to have any adverse effect on the epitaxial layer 14 in the element region.

Unless an insulating p+ region is also formed in a region where no element is included as in the conventional method, the p-type impurity diffusion region for insulation isolation in the vicinity where the lowest potential electrode 16 is connected will be kept at a sufficiently low potential. However, as you move away from that point, the potential is suppressed only through the substrate 11, so the potential of the p-type impurity diffusion region for insulation separation gradually increases, causing parasitic effects on elements such as transistors. start. Of course, this problem can be solved by arranging the lowest potential electrodes everywhere, but in actual semiconductor integrated circuits, it may be impossible to arrange them sufficiently due to wiring. Therefore, in order to ensure a sufficiently wide insulating p+ region 5 on the epitaxial layer 14 as in the present invention, the p-type impurity diffusion region for insulation separation, which is separated from the lowest potential electrode 16, is connected to the substrate 11 and the insulating p region 15. Since the voltage is applied through a sufficiently low impedance, the potential that rises above the lowest potential is also small.

As explained above, according to the present invention, it is possible to obtain an IC in which the influence of high concentration impurities on the semiconductor substrate on the epitaxial layer is eliminated, and the insulating region is sufficiently maintained at the lowest potential throughout the IC. .

[Brief explanation of the drawing]

FIG. 1(a) is a plan view of the conventional example, and FIG. 1(b) is a sectional view taken along line xx' of the conventional example (a). Figure 2 (aJ is a plan view of the embodiment of the present invention, Figure 2 (bJ is the embodiment (a)
It is a sectional view taken along YY of . In the figure, 1, 11...semiconductor substrate, 2
゜12...Embedded n+ area 3, 13...
・Buried resistance region, 4.14...Epitaxial layer, 5, 15・Mountain...Insulating p+ region 6, 16...
- Lowest potential electrode, 7, 17 - Old: This is an epitaxial layer on which no element is formed.

Claims (1)

[Claims] A layer containing impurities of a second conductivity type formed on a semiconductor substrate of a first conductivity type is formed on a semiconductor substrate of a first conductivity type.
In a semiconductor device having a structure in which a conductive type region is separated into multiple element regions, the planar area occupied by the first conductive region in the upper part of the layer is larger than the planar area of the first conductive type region in the lower part of the layer. A semiconductor device characterized by: