JPS5821295B2 - Electronic computer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic computer having an address matching function section.

Conventionally, computers with address match registers are started by setting data from the console panel, and the addresses compared with the address match register are memory addresses that appear during the execution of instructions in the central processing unit. , the operation of the central processing unit was temporarily stopped when an address match was established.

Therefore, in the conventional address match function, the process is repeated (during program debugging, etc.), sequentially setting data from the console section, checking the stop every time an address match is found, and checking the status of registers, etc. Because of the nature of the work, it required a lot of time.

Also, since the address to be compared is the memory address when the central processing unit accesses the main memory, the DMA
(Direct Memory Access)
Even if the device accesses the main memory, no address match is detected and the DMA device is definitely accessing the expected memory address, or conversely, the DMA device is accessing the expected memory address.
It was not possible to easily determine whether the MA device was accessing a memory address that should not be accessed.

This invention was made in view of the above-mentioned circumstances, and addresses the problem of address matching and DMA during memory access of the central processing unit.
Address matching when accessing the memory of the device can be selected arbitrarily, address matching by logical address and address matching by physical address can be arbitrarily selected, and data can be input to the address matching register not only by the console but also by a command. An object of the present invention is to provide an electronic computer which enables program interrupts by detecting an address match and enables efficient and easy program debugging and hardware failure diagnosis.

An embodiment of the present invention will be described below with reference to the drawings.

Figures 1 and 2 show one implementation according to this proposal. In Figure 1, 1 is a content processing unit (hereinafter referred to as AU), and 2 is a storage device and DMA device that directly transfers data between 3 is AUl and DMA
Address management unit (hereinafter referred to as AMU) that controls main memory access from device 2; 4 is a DMA bus that connects AMU 3 with ALT 1 and DMA device 2; and 5 is a DMA bus that serves as an access path to the main memory; DM on part of DMA bus 4
Logical block information (LB) from A device 2 is sent to AM
6 is the same bus that transmits segment information from DMA device 2 to AM and U3; 7 is the same bus that is part of DMA bus 4 and transmits segment information from AUI and DMA device 2 to U3; 8 is a segment register (SGR) that holds segment information used during main memory access in AU, and 9 holds logical addresses in AUl. Memory address register (MAR
), 10 is a segment register (SG
RD), 11 is a memory address register (MAR) in the DMA device 2, 12 is a switching circuit (MPXI) for switching between segment information from the AUI and segment information from the DMA device 2, and 13 is a logical block of the AUI. information (LB) and logical block information of DMA device 2 (
LB) and a switching circuit (MPX 2 ) for switching between
14 is a conversion table (CT) that converts a logical address to a physical address; 15 is a conversion table (CT) 1
A physical address (PA) created from the result of subtracting 4 and the logical address DISP, 16 is logical address information from AUI or DMA device 2, 17 is segment information from AUI or DMA device 2, 18 is a conversion table (CT
) 14, the lower part of the physical address (PA) that is created has the same data length as the logical address information 16, and 19 is the part corresponding to the lower part 18 of the physical address (PA, ). This is the upper part of an address other than

Furthermore, FIG. 2 shows the configuration of the address 4 address match function section provided in conjunction with the AMU 3, in which 20 indicates the segment information 17 and a portion of the same data length as the upper portion 19 of the physical address (AMR 11) and one or more A first address match register (AMRI) consisting of redundant bits (three bits A, S, and L in the embodiment); address match register, (AMR2), 2
2 is the upper part of the address (17 or 19) and the AMR11 section c! of the first address match register 20! : A first comparator circuit (CMP
1 ), 23 is a second comparison circuit (CM
P2), 24 is the first address match register (AMR
1) This is an output signal line of 20 1-redundant pins L-L, and this bit L is a bit that specifies whether an address match is performed based on a logical address or a physical address.

25 is also the first address match register (AMRI
) This is the output signal line of 1 redundant bit S in 20, and this bit S can be used to match segment information when performing an address match based on logical addresses, or to compare only logical address information regardless of segment information. This bit specifies whether it is a match.

26 is also the first address match register (AMRI
) is the output signal line of 1 redundant pin l-A of 20, and this bit A determines whether an address match is taken when accessing the main memory from the AUI or when accessing the main memory from the DMA device 2. This is the bit to specify.

21 is a switching circuit (MPX3) for selecting segment information 11 or address upper sentence 1-9 as information to be compared with the AMR11 section of the first address match register 20 in the first comparison circuit 22; 2 comparison circuit 23
In the second address match register (AMR2) 2
A switching circuit (MPX
4), 29 is the coincidence detection signal line of the first comparison circuit (CMP 1 ) 22, and 30 is the second comparison circuit (CMP 2 ).
23 is a coincidence detection signal line, 31 is a main memory access timing input signal line, 32 is a signal input line indicating whether the main memory is being accessed by AUI or DMA device 2, and 33 is a console panel A signal line 34 is a signal line from a flip-flop (not shown) in AUI, which is one of the conditions for setting the flip-flop 35 to cause an interrupt in AUI when an address match is found on the signal line from the switch. On the signal line, the flip-flop is set to the address match register (AM) by the instruction.
The signal line 34 becomes a set state when data is set in R1 and AMR2), and this signal line 34 is a 1 line for setting the flip-flop 35 when an address match is found.
There are two conditions.

35 is an interrupt flip-flop that is set when the address match conditions are met to cause an interrupt to AU1; 36 is an output signal line of the flip-flop 35;
This is an address match interrupt signal line for notifying the AUI of an address match.

Further, 37 is the first address match register (AMRI
) 20 redundant bits L signal line 24 output and redundant bit S
38 is an OR gate that receives the output of the AND gate 31 and the coincidence detection signal of the first comparison circuit (CMPI) 22; 39 is an OR gate 3;
The AND gate 40 receives the output of 8, the coincidence detection signal 30 of the second comparator circuit (CMP 2 ), and the main memory access timing input signal 31, and determines whether it is the AUI that is accessing the main memory or not. The signal line 32 output and the first address match register (AMRI) indicating whether
A logic circuit receives the signal line 26 output of 1 redundant bit A of 20 and obtains one condition signal for the address match interrupt, 41 is an OR gate that receives the output of signal lines 33 and 34, and 42 is an AND gate 39 This is an AND gate that receives the output of the logic circuit 40, the output of the OR gate 41, and obtains a signal for setting the flip-flop 35.

To explain the operation here, Fig. 1 shows part of the system configuration of a computer, and when a logical address is given from AUl or DMA device 2 and the main memory is accessed, conversion to a physical address is done by AMTJ3. This indicates that the AU1 and DMA device 2 have segment registers (SGR) &
(SGR-D) 10 and memory address registers 9 and 11 for holding logical addresses within the segment, respectively.

These segment information and logical address information are determined whether access to the main memory is by the AUI or by the DMA device 2.
A switching circuit (MPXI)
) 12 and (MPX2) 13, segment information 17 and logical address information 16 are extracted.

On the other hand, the segment information selected by the switching circuit (MPXI) 12 and the logical block information selected by the switching circuit (MPX2) 13 are given to the conversion table (CT) 14, and from this conversion table (CT) 14, the physical blocks are (PB
) is extracted, and this is combined with a part (DISP) that corresponds one-to-one to the physical address of the physical address information of the logical address information to obtain the physical address PA1.
5 is obtained.

From physical address PA, data length is logical address information 1
A lower part 18 of the physical address PA that is the same as 6 and an upper part 19 of the physical address PA that has the same data length as the segment information 17 are extracted.

Also, the address match register (AMRI) 20 in FIG.
and (AMR2) 21 are registers in which desired data can be set by commands or by operations from the console panel.

The output signal 24 of bit L of the first address match register (AMRI) 20 causes addresses to be compared by logical addresses when the logic is ``1'', and to cause addresses to be compared by physical addresses when the logic is ``0''. , controls the switching circuits (MPX3) 27 and (MPX4) 28.

At this time, one of the comparison data of the first comparison circuit (CMP1) 23 is selected by the switching circuit (MPX3) 27, and the other one is the data selected by the address match register (AMR1).
) 1 part of AMR1 out of 20.

Also, 1 of the comparison data of the second comparison circuit (CMP2) 23
One is selected by the switching circuit (MPX4) 28,
The other one is an address match register (AMR2) 21.

1st. Second comparison circuit (CMPI) 22. (CMP2)
23, when a match is detected, the respective match detection signal lines 29 and 30 become logic "1".

The bit L output signal line 24 that controls the switching circuits (MPX3) 27 and (MPX4) 2B is also one input of the AND gate 37, and when the address is compared using the physical address, the logic is ``0'', so the AND gate 3T is used.
The output of the first comparator circuit (CMP
1) The coincidence detection signal 29 of 22 becomes valid.

The output signal 25 of bit S of the first address match register (AMRl) 20 specifies an address match including segment information when it is logic ``1'', and specifies an address match including segment information when it is logic ``0''. 2 comparison circuit (CMP2)
23 specifies that an address match is to be detected only by comparison.

When the output signal line 24 of the bit L is logic ""1'' and the address match is specified by the logical address at 2, the output signal line 25 of the bit S is the logic eY 199, which is the first comparator circuit (CMP 1) 22. Coincidence detection signal 29 becomes valid, and on the other hand, if bit S output signal line 25 is logic "0", it becomes irrelevant to signal line 29. Of the three inputs of AND gate 39, signal line 30 is connected to second comparator circuit (CMP 2)
23, the signal line 43 is ORed between the output of the AND gate 37 and the signal line 29, and the Shingetsu line 31 is the memory timing created by AUl when accessing the main memory. It's a signal.

The output of this AND gate 39 becomes one positive pulse when an address match is found in the mode specified by bits S and L of the first address match register (AMRI) 20, but at this stage From a logic circuit perspective, this means that an address match has been detected.

Bit A of the first address match register (AMRI) 20 is a bit that specifies whether address match detection is performed by main memory access from AUl or by access from DMA device 2, and its output signal line 26 is logic''
1'' specifies access from AUI.

This signal line 26 is one input of the logic circuit 40, and the other one is the signal line 32, which is the logic n 1y
This signal line indicates that AU1 is permitted to access the main memory when t, and when the logic is ``0'', it indicates that the DMA device 2 is permitted to access the main memory.

When the signal lines 26 and 30 logically match whether an address match is to be achieved by accessing the main memory by AU1 or by access by the DMA device 2, the logic circuit 40 outputs the output from the logic circuit 40 by logic tt, Discrimination is made by setting n.

Are the signal lines 33 and 34 instructed by a switch from the console panel to perform an address match?
Or, it indicates whether it is instructed by an instruction, and both indicate that an address match is taken when the logic fl1jj is set, that is, an instruction is given to notify AU1 of an address match interrupt.

The signal lines 33 and 34 are connected to an AND gate 42 via an OR gate 41.

An address match is detected in the address match detection mode specified by the redundancy bit of the address match register (AMRI) 20, and an at1 match is detected by a switch on the console panel or by a command. Address match interrupt flip-flop 35 is set when instructed to notify AUl when detected.

Output signal line 36 of flip-flop 35 notifies AU1 that an address match interrupt has occurred.

Furthermore, when AUl detects this interrupt, signal lines 33 and 3
4, the computer is stopped when instructed by a switch on the console panel, and a program interrupt is caused when instructed by an instruction.

As described in detail above, according to the present invention, it is possible to switch and determine an address match based on a logical address and an address match based on a physical address. It becomes easy to diagnose whether the cause of the malfunction is due to the cause of the malfunction, or whether the cause of the malfunction is due to the side that operates by supplying the physical address (mainly the hardware side).

[Brief explanation of the drawing]

FIGS. 1 and 2 are block diagrams showing one embodiment of the present invention. 1...AU (Central Processing Unit), 2...
DMA device, 3...AMU (address management unit)
, 4...DMA bus, 12, 13, 27.28
. . . Switching circuit, 14 . . . Conversion table (CT), 20 . . . First address match register (AMR1), A, S. L...Redundant bit, 21...Second address match register (AMR2) 22...First comparison circuit (CMP1), 23... Second
Comparison circuit (CMP 2 ), 35... flip-flop, 37, 39, 42... AND gate, 40... logic circuit.

Claims (1)

[Claims] 1. In an electronic computer that converts a logical address into a physical address to specify the address of a main storage device. A register in which predetermined data is set, an address conversion circuit that converts the logical address into a physical address, a selection information setting section for selecting the logical address or the output of the address conversion circuit, and a selection information setting section from the selection information setting section. a circuit for detecting a match between the logical address or the output of the address conversion circuit and the contents of the register based on a selection signal; and a circuit for sending an interrupt signal to a processing device based on the output of the match detection circuit. An electronic computer characterized by comprising means. 2. The electronic computer according to claim 1, wherein the selection information setting section is provided as a redundant bit in the register.