JPS5380923A - Electronic calculator - Google Patents

Electronic calculator

Info

Publication number
JPS5380923A
JPS5380923A JP15694776A JP15694776A JPS5380923A JP S5380923 A JPS5380923 A JP S5380923A JP 15694776 A JP15694776 A JP 15694776A JP 15694776 A JP15694776 A JP 15694776A JP S5380923 A JPS5380923 A JP S5380923A
Authority
JP
Japan
Prior art keywords
memory unit
electronic calculator
address
giving
cpu
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15694776A
Other languages
Japanese (ja)
Other versions
JPS5821295B2 (en
Inventor
Tadashi Hayashi
Yukiro Shiraokawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP51156947A priority Critical patent/JPS5821295B2/en
Publication of JPS5380923A publication Critical patent/JPS5380923A/en
Publication of JPS5821295B2 publication Critical patent/JPS5821295B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]

Abstract

PURPOSE:To secure a highly efficient fault diagnosis for program debug and the hardware when an access is given to the main memory unit by giving a logic address from CPU or memory unit directly, by having a conversion to the physical address at the address control part.
JP51156947A 1976-12-25 1976-12-25 Electronic computer Expired JPS5821295B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP51156947A JPS5821295B2 (en) 1976-12-25 1976-12-25 Electronic computer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP51156947A JPS5821295B2 (en) 1976-12-25 1976-12-25 Electronic computer

Publications (2)

Publication Number Publication Date
JPS5380923A true JPS5380923A (en) 1978-07-17
JPS5821295B2 JPS5821295B2 (en) 1983-04-28

Family

ID=15638808

Family Applications (1)

Application Number Title Priority Date Filing Date
JP51156947A Expired JPS5821295B2 (en) 1976-12-25 1976-12-25 Electronic computer

Country Status (1)

Country Link
JP (1) JPS5821295B2 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4735832U (en) * 1971-05-11 1972-12-21
JPS51147144A (en) * 1975-06-13 1976-12-17 Hitachi Ltd Information processor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4735832U (en) * 1971-05-11 1972-12-21
JPS51147144A (en) * 1975-06-13 1976-12-17 Hitachi Ltd Information processor

Also Published As

Publication number Publication date
JPS5821295B2 (en) 1983-04-28

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