JPS58211229A - Input interface circuit - Google Patents

Abstract

PURPOSE:To set freely an inverted voltage level, and to apply it to an interface circuit of a window comparator type, by placing in parallel the first and the second bias setting means, and supplying a current corresponding to an input signal to each bias setting means from a current supplying means. CONSTITUTION:The first bias setting means which connects in series a multi- emitter type transistor TR Q5 whose conduction is controlled by an input signal Vin functioning as a current supplying means, and resistances R4, R5 is provided between an electric power source + and a ground point GND. Also, the second bias setting means is formed by connecting in series resistances R6, R7 between the other emitter of the TR Q5 and the ground point. Also, the first TR Q6 is connected between a connecting point of the resistances R6, R7 and the ground point, and the conduction is controlled by the potential of the connecting point of the resistances R4, R5. Also, the second TR Q7 is connected between an output terminal (out) and the ground point, and it is controlled by the potential of the connecting point of the resistances R6, R7. Subsequently, a value of the resistances R4-R7 is set to R4/R5>R6/R7, and an inverted voltage level is set freely.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a window comparator type input interface circuit that connects a linear circuit and an I"L circuit. [Technical Background of the Invention and Problems thereof] Conventionally, As an I!L circuit dynamic drive input interface circuit, published in JP-A-54-87143 and JP-A-5
4-102955 discloses the circuit shown in FIGS. 1 and 2.

That is, in the circuit shown in FIG. 1, an NPN type transistor Q is disposed between a constant current source I and a ground point, and a resistor R is connected between the base of this transistor Q1 and a power supply Vcc.
, and a PNP type transistor Q2 are connected in series. Then, the input signal Vin is applied to the base of the transistor Q.
is supplied, this transistor Q is controlled to be conductive, and the resistor R3 and the transistor Q,
The conduction of the transistor Q is controlled by the current supplied through the transistor Q, so that an output signal Vout k is obtained from the collector side of the transistor Q.

In the circuit shown in Fig. 2, an NPN transistor Q and engineered resistors R, R, are connected in series between the power supply VCC and the ground point, and the potential at the connection point of the resistors R1 and R8 is used to control the next stage. 1” Connected between the input gate of L circuit 1-1 and the ground point f
l N P N-type transistor Q4 is controlled to be conductive.

i! iI! In the configuration shown in Figure 2, the input signal (
When the clock signal CP reaches the i ('H') level, the transistor Q3 turns on, and the transistor Q
At the pace of 4, transistor Q, ↓ and resistor Ry
Since current is supplied through k, this transistor Q4
0 is turned on. Therefore, a low ("L") level signal is supplied to the input gate of the I'L circuit No. 1 at the next stage. Furthermore, when the input signal CP goes to the "L" level, the transistor Q3 is turned off, so the transistor Q4
is also turned off, and an H'' level signal is supplied to the input gate of the I'L circuit No. 1 at the next stage.

As mentioned above, the circuits shown in Figure 1 and Figure 2 work as an interface circuit between the linear circuit and the I'L circuit.In recent years, however, in the interface circuit between the linear circuit and the I'L circuit, multiple A window comparator type input interface circuit having inverted voltage levels is desired.

[Purpose of the invention]

This invention was made in view of the above-mentioned circumstances.
What is the purpose of this, the inversion voltage level? [Summary of the Invention J] That is, in this invention, the first and second bias setting means are arranged in parallel, and the above-mentioned bias setting means are arranged in parallel. The current supply means supplies the entire current corresponding to the input signal to the first and second bias setting means.Then, the first transistor is connected between the second bias setting means and the ground point to set the first bias. A second transistor is connected between the output terminal and the ground point, and one of the transistors is connected to the second bias setting means to control the conduction.

[Embodiments of the invention]

Below is a drawing of an embodiment of this invention? Refer to and explain. Figure 3 shows its configuration, in which a multi-emitter type NPN transistor whose conduction is controlled by the input signal Vin is connected between one power source and the other source (ground point GND) as a current supply means. Qn, ↓ and resistance R4, R, (
(first bias setting means)? In addition to connecting in series, the other emitter of the transistor Q and the ground point G N
]), there is resistance between [? ,,R,(second bias setting means)? Connect in series. - A first C') N P N-type transistor Qe k is connected between the connecting point of the resistors R, , R7 and the grounding point GND, and conduction is controlled by the potential of the connecting point of the resistors R4 and R. In addition, a second NPN transistor Qyk is connected between the output terminal OUT and the ground point GND,
Continuity is controlled above the connection point of the resistor R6+Rf.

- In the above-mentioned configuration, the operation is explained.

In this circuit, in order to achieve the operating characteristics of the window comparator, the resistance ratios of the respective resistors are set to satisfy the following relationship.

When the input signal Vln is at a low level (for example, OV), the conduction resistance of transistor Q is high, so transistor Q3
, Q7 are both non-conductive, and I
If the ``I'' circuit is provided, the output signal Volt will be at the ``TI'' level.Then, as the level of the input signal Vln gradually increases and the conduction resistance of the transistor Q decreases, first the transistor Q1 becomes conductive, and the level of the output signal VOuI is inverted.The voltage at this time, where the input voltage is VthT, is as follows.When the input signal voltage Vjn is lower than the above Vt)IL, the base voltage of the transistor Q6 vn!l
is shown by the following formula (3).

Here, 'Vln (VthL J), so if we transform the above equation (3), we get the following.The condition of the above equation (1)? Substitute it into the above equation (4),
is found. In other words, the input voltage Vln is the inverted voltage vtht
, when ELI is also low, the base voltage V n 6 of transistor Q6 is VBI! () The voltage required for the transistor to conduct) Since the area is also small, - this transistor Q
6 is a non-conducting state.

Next, the input signal voltage Vin becomes even higher than the inversion voltage vthi, and the voltage Vthll expressed by the following equation (6)
When the voltage becomes higher than , the transistor Q becomes conductive.

When the transistors Q and l become conductive, the base of the transistor Q is grounded through the transistor Qsk, so the transistor Q becomes non-conductive, and the output signal You t becomes the HII level. Input signal voltage vin and output signal voltage Vout
The relationship between the two brothers is shown in Figure 4. As shown in the figure, when the output signal reaches the ``L# level, ``vthL<vIn<■
During the period "thII", the window comparator operates.

Operation of the input interface circuit according to this invention? To confirm, conduct an experiment using the circuit shown in Figure 5. In this circuit, instead of the multi-emitter type transistor Qs in the circuit of FIG. 3, a transistor Q II 1Qok is provided, and conduction of each of the seven transistors is controlled by a signal Vln. Also a transistor to obtain the output signal Vout k. ,
A load resistor R6? is connected between the collector of and the power supply vCC. It is set up. In the figure, resistance R4 = 22Ω.

R,=R, -R7=R, 1-5, 6 are set to Ω. Therefore, the theoretical value of the inversion voltage vtht, VthH is v
thL=2.1yVthH:4.2V. In the above circuit, as a result of inputting a triangular wave of frequency fIn=xKHz as the power supply voltage vcc-6V, vtht=2.2 V and VthH=4.2 V, confirming that it is operating accurately.

In addition, we confirmed that the operation is normal when the frequency fln = 100KH7, <7) triangular wave F is input.

FIG. 6 shows an example of the circuit configuration when the input interface circuit according to the present invention is used as an input interface circuit of the Kelinian circuit and the I"L circuit, and shows the output terminal o.
ut f I'L circuit No 1 transistor Q
Connect to the IO gate.

The gate of this transistor Q10 is connected to the injector current 1 from the power supply Vcc through the transistor Q11.
1nj is supplied. -] °C, transistor Q,
. The inverted output of the circuit shown in FIG. 3 above is obtained from the collector of .

In addition, I! L circuit NPN transistor Q. Since the injector current is supplied from the transistor Ql+,
The resistor R6 shown in FIG. 5 is not necessarily required in this embodiment! d has been omitted.

FIG. 7 shows another embodiment of the present invention, in which the inversion voltage vtht? in the circuit shown in FIG. It is designed so that it can be set to a low value.

That is, between the power supply Vec and the ground point CND, an NPN type transistor Q whose conduction is controlled by the input signal Vin, and a resistor Ran, R11' are connected in series, and between the power supply Vcc and the ground point GND. Resistance R, ↓ and PNP
shaped transistor. It k is connected and the transistor Q3. conduction is controlled in common with the transistor Q by the input signal Vin. Furthermore, the power supply Vcc and the ground point GN
NPN type transistor Q9 manufactured resistor RamR between D
An NPN type transistor Qak is connected between the connection point of the resistors R, , R, and the ground, and conduction is controlled by the potential of the connection point of the resistors R4 and R. Then, a fl N P N type transistor Q7 k is connected between the output terminal out and the ground point, and conduction is controlled by the potential at the connection point of the resistors R, , R, to obtain an output signal Vout k.

According to such a configuration, VthL can be made wider than in FIG. 5. In the circuit shown in FIG. 5 above, due to circuit constraints, the inversion voltage level VthL k
1.4 V (~2 VIIK) It will not work unless it is set 1 higher. In other words, this is due to the fact that the voltage Eri, which is the sum of vng of transistor Q7 and VB''k of transistor Q6, cannot operate unless the level of input signal Van is high.C) On the other hand, in the circuit shown in FIG. , vtht.

? It can be set to 0.7V-.

FIG. 8 shows a circuit that can further widen the inversion voltage of the circuit shown in FIG.
+2 in addition to transistors Qo and Q14, respectively, and resistors R10*R, ? Power supply voltage Vcc f
It was designed to be supplied. According to such a configuration, the inversion voltages VthL and Vthl+ are respectively v
tht > ov VthH > g, 7 v, and the range of the inversion voltage can be set widely.

Figure M9 shows the multi-emitter transistor Q! in the circuit of Figure 3 above. , at the pace of transistor Q+s,
Qr6 is provided in Darlington connection, and connected to the collector rson, 'eJL grounding point GN1) of the transistor Q1seQ+a, and connected to the power supply 1 through the paceke resistor L2'f of the transistor Q5, The base trap input signal Vlnf of the transistor Q16 is supplied to control the conduction of the transistor Q16. According to such a configuration, the widths of the inversion voltages Vt11+, Vt11n can be set wider than those of the embodiments shown in FIGS. 7 and 8.

By the way, the window comparator can be applied as various detection circuits, and the window comparator type input interface ff1l M ? r It can be used as a Hals Tutei detection circuit. Normally, when the signal is supplied to the average value circuit as a two-pulse signal with a duty of 50, a voltage of 1/2 Vcc is obtained and is supplied to the voltage comparator. Now, the window comparator has the input/output transfer characteristics shown in Figure 4 above, and VthL
= 0.4 VCC Vthn = Q, when set to 5 Vcc, input fc Hals duty is 4
When the signal goes outside the range of 0% to 60ch, the window comparator outputs a signal at the "H" level.

Therefore, abnormalities in pulse duty can be detected.Furthermore, the window comparator type input interface circuit according to the present invention can also be applied as a frequency multiplier circuit. This will be explained below using the timing chart of FIG. The triangular wave Bks corresponding to the reference rectangular wave signal A is the input interface shown in Fig. 3 above.
When input as the input signal Vjn of the 7-eighth circuit, at the rise and fall of the triangular wave B, vth, ,
By inverting the output signal Vout at vth, a rectangular wave signal C having twice the frequency of the reference rectangular wave signal A is obtained. At this time, the duty ratio of the rectangular wave signal C is the inversion voltage vth, , vth, 1 resistance R, , R, and R6mR? The input interface circuit according to the present invention is set to a predetermined value by adjusting the ratio of 0 to a predetermined value. 124 is a comparator, vref1 to Vref4 are reference voltages, RII!
"R18 is a resistor, and Q+7 to Qv are transistors.The reference voltages Vref1 to Vref4 are "Vre
f, (Vref, (Vref, (Vref4J). Now, assuming that the output terminal out is precharged to H" level, when the level of the input signal Vln is below the reference voltage Vrefl, the transistor Q+? ~Qm
are all in the off state, so the output signal Vout is H“
Level roars.

Next, when the level of the input signal Vln becomes "Vref, (vin (Vref2-J),
The output of the comparator 121 becomes "H" level, transistor Q+7 is in the on state, and transistors QI8 to Q2
0 is off state. Therefore, the output signal Vout is “L”
# level. Next, the level of the input signal v1n is [V
When ref2 (Min (Vref3) becomes J, the output of the comparator 'l+12.' becomes 'H' level.

For this reason, transistor Q1. is on, transistor Q+? *Q+o+Qm is turned off. Therefore, the output signal Vout becomes H" level. Furthermore, the level of the input signal V'in becomes "Vref, 3 (V
ln (When Vref4-no is reached, the comparator 121
．． The output of 121 and 12g becomes ゛H# level,
Transistor CI Ig * Q +7 is on, Q
+s+Qm goes into a dead state, and the output signal Vout becomes the "■・" level (>Next, when the level of the input signal Vln becomes equal to or higher than the reference voltage Vre・f4, the outputs of the comparators 12.-12. all become 'H'. ” level, transistor Q+a+Q+s is on, Q+o * Q1
0 is in the off state, and the output signal VoIlt is “)I
“It becomes a level.

As mentioned above, this circuit inverts the level of the input signal Vin at the -C1 reference voltages VrefI to Vraf4. Now, if a triangular wave corresponding to the reference rectangular wave is input as the above input signal Vln, the output will be inverted four times each at the rise and fall of the triangular wave, so the output will be four times that of the reference rectangular wave. A square wave with a period of is obtained. In other words, it operates as a frequency multiplier circuit.

Figures 12 to 14 show examples of the 12-circuit input interface of the Indian comparator type according to the present invention, in which Figure 12 shows a circuit with three inversion voltages, and Figure 13 shows a circuit with four Figure 14 shows a circuit with four inversion voltages, and the width of the inversion voltage? This is a circuit that can be configured in a wide range of settings.

In the circuit shown in FIG. 12, in addition to the circuit configuration shown in FIG. 3, a transistor Q21% for inverting the output of C1 and a resistor RIT#RIAp for controlling conduction of this transistor Qt+ at a predetermined potential are provided. . Here, each resistor R4 to R7.

Rt? *The resistance value of R1^ has a different relationship w Hr, :, ↓ ○According to this configuration, there are three inversion voltage levels? Since there is a square wave signal as a reference? When input, a rectangular wave signal with a period three times that of the reference rectangular wave signal is obtained as an output.

In addition to the configuration shown in FIG. 12, FIG. 13 further includes a transistor Q22 and a resistor ■<. , Rzo' is added to °C. Here, the resistance value ratio of each resistor is set as follows. This circuit has four inversion voltage levels. Therefore, it becomes a 4-times frequency multiplier circuit. FIG. 14 shows a circuit that can widen the level of the inversion voltage of the circuit shown in FIG. 13 above. Darlington connected transistor Q231Q? 4 ↓ and resistance R2
1*R2! This has been established. Since this circuit is similar to the circuit shown in FIG. 9, its explanation will be omitted.

In each of the above embodiments, a resistor is used as the bias setting means. However, the same effects as in each of the above embodiments can be obtained even if other impedance means such as a diode are used.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to obtain a window comparator type input interface circuit in which the inversion voltage level r can be freely set.

[Brief explanation of drawings]

1 and 2 are diagrams showing a conventional input interface circuit, FIG. 3 is a diagram showing a window comparator type input interface circuit according to an embodiment of the present invention, and FIG. 4 is a diagram showing a conventional input interface circuit. Figure 5 is a diagram showing the relationship between the input signal voltage and output signal voltage of the circuit shown in Figure 3. Figure 5 is a diagram showing the configuration of the circuit used in the experiment to confirm the operation of the circuit in Figure 3 above. An example of a circuit configuration when used as an input interface circuit for the human interface circuit iI'L circuit shown in Figure 3 above? Figures 7 to 9 are diagrams showing other embodiments of the present invention, and Figure 10 is the circuit shown in Figure 3 above. FIG. 11 is a timing chart for explaining the operation 4 when used as a frequency multiplier circuit, FIG. 11 is a diagram for explaining the general basic principle of the input interface circuit according to the present invention, and FIGS. FIG. 2 is a diagram showing a specific example of the circuit configuration of an input interface circuit according to the invention. 10...power supply, -(GND)...ground point, R4...first resistor, R2...second resistor, R, l...third resistor, ■ri,... Fourth resistor, Qll...multi-emitter transistor (current supply means), Q6...
First transistor, Q, second transistor, in
...Input terminal, out...Output terminal, Vin.
...Input signal, Vout output signal. Applicant's Representative Patent Attorney Takehiko Suzue Figure 3 (GND) Figure 944 VthL VthH Voltage (Vin) - Is Figure 6 (GND) Figure 7 Figure 8 Figure 119

Claims (4)

[Claims] (1) First. Currents corresponding to the input signals in the second bias setting means and the first and second bias setting means, respectively? a first transistor connected between the second bias setting means and the ground point and whose conduction is controlled by the first bias setting means; and a first transistor connected between the output terminal and the ground point; 1. An input interface 7-eighth circuit comprising: a second transistor whose conduction is controlled by means of the second bias setting means; (2) The input interface circuit according to claim 1, wherein the current supply means is comprised of a multi-emitter type transistor whose conduction is controlled by an input signal. (3) Does the bias setting means described above consist of a plurality of resistors connected in series? An input interface circuit according to claim 1, characterized in that: (4) The input interface circuit according to claim 1, wherein each of the bias setting means comprises a plurality of diodes connected in series.