JPS58210575A - Fault diagnosing method of electronic circuit package - Google Patents

Fault diagnosing method of electronic circuit package

Info

Publication number
JPS58210575A
JPS58210575A JP57092761A JP9276182A JPS58210575A JP S58210575 A JPS58210575 A JP S58210575A JP 57092761 A JP57092761 A JP 57092761A JP 9276182 A JP9276182 A JP 9276182A JP S58210575 A JPS58210575 A JP S58210575A
Authority
JP
Japan
Prior art keywords
circuit element
electronic circuit
suspected
package
circuit package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57092761A
Other languages
Japanese (ja)
Inventor
Yasuyoshi Aoki
青木　康能
Toshimi Yoshida
吉田　敏美
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP57092761A priority Critical patent/JPS58210575A/en
Publication of JPS58210575A publication Critical patent/JPS58210575A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
    • G01R31/2836—Fault-finding or characterising
    • G01R31/2843—In-circuit-testing

Abstract

PURPOSE:To make a normal/defective decision without detaching a circuit element which is suspected to be faulty from a substrate, by connecting the suspected circuit element in a high impedance state in parallel to a normal circuit element, and operating a electronic circuit package to make the decision. CONSTITUTION:A circuit element 2a suspected to be faulty is an element which has one of three states, i.e. ''1'', ''0'', '' neither 1 nor 0''. An electronic circuit package is put in operation and the suspected circuit element 2a is placed in the state ''neither 1 nor 0'', i.e. high impedance state. Then, the normal circuit element 3 which is of the same kind with the suspected circuit element 2a is connected to the circuit element 2a with a clip 4 in parallel. Then, the electronic circuit package is put in operation. In this case, if the package operates normally, it is judged that the circuit element 2a is normal. Consequently, whether the suspected element is normal or not is judged without detaching it from the wired substrate.

Description

【発明の詳細な説明】 本発明は電子回路パッケージの故障診断方法に関し、特
に入出力が［Ｊ、ｒｏＪ、ｒｌでもＯでもない」の三つ
の状態を取り得る論理素子を搭載した電子回路パッケー
ジの故障診断方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for diagnosing failures of electronic circuit packages, and in particular to a method for diagnosing failures of electronic circuit packages, particularly for electronic circuit packages equipped with logic elements whose input/output can take three states: [Neither J, roJ, rl nor O]. Related to failure diagnosis method.

従来、論理素子を搭載した電子回路パッケージ等が正常
に動作しない場合の診断方法としては、外部との接続部
にある入力データを与え、これに対する回路の応答を入
力側よシ順次追跡し、他の方法によって得られた正しい
状態との差異を発見することによシネ良の素子を推定す
る方法がとられていた。しかるに、回路が複雑化するに
伴い、正しい状態をあらかじめ得ることが極めて難しく
なってきた。Conventionally, the diagnostic method for when an electronic circuit package etc. equipped with logic elements does not operate normally is to apply input data to the connection part with the outside, track the response of the circuit to this sequentially from the input side, etc. The method used was to estimate the cine quality by finding the difference from the correct state obtained by the above method. However, as circuits have become more complex, it has become extremely difficult to obtain the correct state in advance.

又、仮に不良と思われる回路素子が推定できたとしても
、それを不良と断定する材料に乏しく、被疑素子を配線
基板よシ取外して試験しなければならなかりた。しかし
、配線基板からの回路素子の取外しは多大の工数を要す
るのみならず、その回路素子の周辺の配線や他の回路素
子にも損傷を与え配線基板の信頼性を著しく損うという
欠点があった。Furthermore, even if it were possible to guess which circuit element was defective, there was insufficient material to determine that it was defective, and the suspect element had to be removed from the wiring board and tested. However, removing a circuit element from a wiring board not only requires a large amount of man-hours, but also has the drawback that it can damage the wiring around the circuit element and other circuit elements, significantly impairing the reliability of the wiring board. Ta.

本発明は上記欠点を除去し、ｒｌＪ、ｒｏ、ｊ。The present invention eliminates the above drawbacks and provides rlJ, ro, j.

「１でも０でもない」の三状態を取ル得る回路素子を配
線基板よシ取外すことなシその良否を判定できる電子回
路パッケージの故障診断方法を提供するものである。To provide a failure diagnosis method for an electronic circuit package that can determine the acceptability of a circuit element capable of detecting three states of "neither 1 nor 0" without removing it from a wiring board.

本発明の電子回路パッケージの故障診断方法は、故障し
た電子回路パラマージの被疑故障回路素子を高インピー
ダンス状態にする手順と、前記被疑故障回路素子と同一
極類で予め良品である仁とが確認されている良品回路素
子を前記被疑故障回路素子罠並列に接続する手順と、前
記電子回路パッケージを動作させ、正常動作したときは
前記被疑故障回路素子を不良回路素子と判定する手順と
を含んで構成される。The fault diagnosis method for an electronic circuit package according to the present invention includes a procedure for bringing a suspected faulty circuit element of a faulty electronic circuit parameter into a high impedance state, and a step in which a defective circuit element of the same polarity as the suspected faulty circuit element is previously confirmed to be a good product. a step of connecting good circuit elements that are in good condition in parallel with the suspected faulty circuit element; and a step of operating the electronic circuit package and determining the suspected faulty circuit element as a defective circuit element when the electronic circuit package operates normally. be done.

次に１本発明の実施例について図面を用いて説明する。Next, an embodiment of the present invention will be described with reference to the drawings.

第１図は本発明の一実施例を説明するための斜視図であ
る。FIG. 1 is a perspective view for explaining one embodiment of the present invention.

電子回路パッケージの配線基板１には回路素子２が多数
搭載され、接続されている。このうち、回路素子２ａが
不良になっていると疑われている被疑故障回路素子とす
る。A large number of circuit elements 2 are mounted on and connected to a wiring board 1 of an electronic circuit package. Among these, the circuit element 2a is assumed to be a suspected faulty circuit element that is suspected to be defective.

被疑故障回路素子２ａはｒ−ＩＪ、ｒＯｊｒｌでも０で
もない」の王状態を取シ得る回路素子であれば良い。こ
のような回路素子は多数あって、マイクロプロセッサ（
例ｔｔｆ、μＰＩＭ’７８０．Ｚ８０等）等がその例で
ある。「１でも０でもない」状態とはオープン状態かあ
るいはそれに近い高インピーダンス状態であることを意
味する。The suspected faulty circuit element 2a may be any circuit element that can take the state "r-IJ, neither rOjrl nor 0". There are many such circuit elements, and a microprocessor (
Example ttf, μPIM'780. Z80 etc.) etc. are examples. The state "neither 1 nor 0" means an open state or a high impedance state close to it.

まず、電子回路パッケージを操作して被疑故障回路素子
２ａを「１でも０でもない」状態、即ち高インピーダン
ス状態にする。First, the electronic circuit package is operated to bring the suspected faulty circuit element 2a into a "neither 1 nor 0" state, that is, into a high impedance state.

次に、被疑故障回路素子２ａと同一種類で、予め良品で
あることが確認されている良品回路素子３をクリップ４
によって被疑故障回路素子２８に並列に接続する。そし
て、電子回路パッケージを動作させる。このとき、電子
回路パッケージが正常動作したならば、被疑故障回路素
子２ａは不良品動作したならば、被疑故障回路素子は不
良であると判断される。なぜならば、（１）被疑故障回
路素子２ａをパッケージ内の他の素子と電気的に接続し
てパッケージ全体を試験したとき結果は否であった。（
２）被疑故障回路素子２ａを電気的に他の回路よシ独立
させ、その代シに被疑故障回路素子２ａと同一種類で、
かつ予め良品であることが確認されている良品回路素子
３を並列接続して電子回路パッケージ全体を試験したと
き、その結果は良である。Next, a non-defective circuit element 3 that is the same type as the suspected faulty circuit element 2a and has been confirmed to be non-defective in advance is attached to the clip 4.
is connected in parallel to the suspected faulty circuit element 28 by. Then, the electronic circuit package is operated. At this time, if the electronic circuit package operates normally, and if the suspected faulty circuit element 2a operates as a defective product, then the suspected faulty circuit element 2a is determined to be defective. This is because (1) When the suspected faulty circuit element 2a was electrically connected to other elements in the package and the entire package was tested, the result was negative. (
2) Make the suspected faulty circuit element 2a electrically independent from other circuits, and replace it with the same type as the suspected faulty circuit element 2a,
When the entire electronic circuit package is tested by connecting in parallel the non-defective circuit elements 3 that have been confirmed to be non-defective in advance, the result is good.

以上の二つのことから被疑故障回路素子を不良と判定で
きるのである。Based on the above two factors, the suspected faulty circuit element can be determined to be defective.

以上詳細に説明したように、本発明によれば、被疑故障
回路素子を配線基板から取外すことなく良品か不良かを
判定できるのでその効果は大きい。As described in detail above, according to the present invention, it is possible to determine whether a suspected faulty circuit element is good or defective without removing it from the wiring board, which is highly effective.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明−の一実施例を説明するための斜視図で
ある。 １・・・・・・配線基板、２・・・・・・回路素子、２
ａ・・・・・・被疑故障回路素子、３・・・・・・良品
回路素子、４・・・・・・クリップ。 ３８２ ＄ｔいFIG. 1 is a perspective view for explaining one embodiment of the present invention. 1... Wiring board, 2... Circuit element, 2
a... Suspected faulty circuit element, 3... Good circuit element, 4... Clip. 382 $t

Claims (1)

【特許請求の範囲】[Claims] 故障した電子回路パッケージの被疑故障回路素子を高イ
ンピーダンス状態にする手順と、前記被疑故障回路素子
と同一種類で予め良品であることが確認されている良品
回路素子を前記被疑故障回路素子に並列に接続する手順
と、前記電子回路パッケージを動作させ、正常動作した
ときは前記被疑故障回路素子を不良回路素子と判定する
手順とを含むことを特徴とする電子回路パッケージの故
障診断方法。A procedure for bringing a suspected faulty circuit element of a faulty electronic circuit package into a high impedance state, and placing a non-defective circuit element of the same type as the suspected faulty circuit element and previously confirmed to be a good product in parallel with the suspected faulty circuit element. A method for diagnosing a fault in an electronic circuit package, comprising the steps of: connecting the electronic circuit package; and operating the electronic circuit package, and determining the suspected faulty circuit element as a defective circuit element when the electronic circuit package operates normally.
JP57092761A 1982-05-31 1982-05-31 Fault diagnosing method of electronic circuit package Pending JPS58210575A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57092761A JPS58210575A (en) 1982-05-31 1982-05-31 Fault diagnosing method of electronic circuit package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57092761A JPS58210575A (en) 1982-05-31 1982-05-31 Fault diagnosing method of electronic circuit package

Publications (1)

Publication Number Publication Date
JPS58210575A true JPS58210575A (en) 1983-12-07

Family

ID=14063407

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57092761A Pending JPS58210575A (en) 1982-05-31 1982-05-31 Fault diagnosing method of electronic circuit package

Country Status (1)

Country Link
JP (1) JPS58210575A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2957423A1 (en) * 2010-03-09 2011-09-16 Peugeot Citroen Automobiles Sa Failure mode measuring method for sensitive component in electronic circuit of motor vehicle, involves placing identified critical component under defect condition, and measuring behavior of electric circuit representative of failure mode

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2957423A1 (en) * 2010-03-09 2011-09-16 Peugeot Citroen Automobiles Sa Failure mode measuring method for sensitive component in electronic circuit of motor vehicle, involves placing identified critical component under defect condition, and measuring behavior of electric circuit representative of failure mode

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