JPS58209163A - Thin-film transistor - Google Patents
Thin-film transistorInfo
- Publication number
- JPS58209163A JPS58209163A JP9118182A JP9118182A JPS58209163A JP S58209163 A JPS58209163 A JP S58209163A JP 9118182 A JP9118182 A JP 9118182A JP 9118182 A JP9118182 A JP 9118182A JP S58209163 A JPS58209163 A JP S58209163A
- Authority
- JP
- Japan
- Prior art keywords
- glass
- substrate
- film
- sio2
- phase
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 10
- 239000011521 glass Substances 0.000 claims abstract description 36
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 10
- 238000005191 phase separation Methods 0.000 claims description 5
- 229910052814 silicon oxide Inorganic materials 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 9
- 239000010408 film Substances 0.000 abstract description 7
- KKCBUQHMOMHUOY-UHFFFAOYSA-N Na2O Inorganic materials [O-2].[Na+].[Na+] KKCBUQHMOMHUOY-UHFFFAOYSA-N 0.000 abstract description 3
- 239000003513 alkali Substances 0.000 abstract description 3
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 abstract description 2
- 238000002844 melting Methods 0.000 abstract description 2
- 230000008018 melting Effects 0.000 abstract description 2
- 229910052681 coesite Inorganic materials 0.000 abstract 4
- 229910052906 cristobalite Inorganic materials 0.000 abstract 4
- 235000012239 silicon dioxide Nutrition 0.000 abstract 4
- 229910052682 stishovite Inorganic materials 0.000 abstract 4
- 229910052905 tridymite Inorganic materials 0.000 abstract 4
- 238000007654 immersion Methods 0.000 abstract 1
- 238000010438 heat treatment Methods 0.000 description 6
- 230000004913 activation Effects 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 238000000137 annealing Methods 0.000 description 3
- 239000005388 borosilicate glass Substances 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 238000001994 activation Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000000704 physical effect Effects 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 235000001674 Agaricus brunnescens Nutrition 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000010828 elution Methods 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000005361 soda-lime glass Substances 0.000 description 1
- 239000007858 starting material Substances 0.000 description 1
- 239000002023 wood Substances 0.000 description 1
- 238000004857 zone melting Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明はガラス基板上に形成されたSi 系半導体材
料を基板が破損することなく、高温で活性化し、移゛′
#A度の高い薄膜トランジスタの製造方法に関する。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention activates and transfers a Si-based semiconductor material formed on a glass substrate at high temperature without damaging the substrate.
The present invention relates to a method for manufacturing a thin film transistor with a high degree of #A.
通常のソーダ石灰ガラスやホウケイ酸ガラスの耐熱衝撃
性ノー一般に悪く、アルカリの極めて少いガラスでもそ
の耐熱@@性Δ’11j600′C匂下でるり、この上
にSi系材料金堆積し半導体デバイス金製造する際に、
活性化させるための熱処理温度全600℃以上に上げる
ことに困難であった。従って半導体材料の活性化が不充
分であり、例えば半導体材料としてポリシリコンを中い
てもその粒径が0.5p以下であった。一方基板に石英
ガラスを用いればこれらの欠点1は解消されるが、石英
ガラスはコストが高く、加工が困難であるという欠点が
ある1、
〔発明の目的〕
本発明はこのような欠点を改良するためになされたもの
であり、その目的とするところtryガラスの分相現象
全利用し、従来の石英々ラスの溶融温度より400〜5
0 0c低い温度で分相性ガラスの中から、低アルカリ
のシリカ系ガラスを分離、抽出しこれを基板として移動
度の高い薄膜トランジスタを得ることKある、
〔発明の概要〕
本発明のデバイスに用いられるガラスとしては分相性ガ
ラスを用いる。例えばSiO,−Bo3−Na,0系ガ
ラスを用いる。この系のガラスは分相現象が極めておこ
し易く、例えば500〜600℃の温度で熱処理を行う
と、Siへ成分とに’5−Naρ系成分とに容易に相分
離をおこす。90℃程度の温度で希塩酸でB2O3−N
a20成分を溶出すれば、後に5i02成分がほぼ98
′チ程度のシリカ系ガラスが工業的に得られるこのガラ
スは別名バイコールガラスとも言われるがこのガラスの
物性及び耐熱衝撃性は石英ガラスに近いものであり、コ
ストも石英ガラスの1/2以下である。これを従来の薄
膜トランジスタのシリコンウェハーの代りに用いて、ガ
ラス基板薄膜トランジスタを作製することが可能である
。The thermal shock resistance of ordinary soda-lime glass and borosilicate glass is generally poor, and even glass with very little alkali has a heat resistance of Δ'11j600'C. When manufacturing gold,
It was difficult to raise the total heat treatment temperature for activation to 600°C or higher. Therefore, activation of the semiconductor material is insufficient, and even when polysilicon is used as the semiconductor material, the particle size is 0.5p or less. On the other hand, if quartz glass is used for the substrate, these drawbacks 1 will be eliminated, but quartz glass has the drawbacks of being expensive and difficult to process.[Objective of the Invention] The present invention improves these drawbacks. Its purpose is to make full use of the phase separation phenomenon of try glass, and to lower the melting temperature by 400 to 500
It is possible to separate and extract a low-alkali silica-based glass from a phase-separating glass at a low temperature and use it as a substrate to obtain a thin film transistor with high mobility. [Summary of the Invention] Used in the device of the present invention As the glass, phase splitting glass is used. For example, SiO, -Bo3-Na,0-based glass is used. This type of glass is extremely susceptible to phase separation, and when heat treated at a temperature of, for example, 500 to 600° C., phase separation easily occurs into a Si component and a '5-Naρ component. B2O3-N with dilute hydrochloric acid at a temperature of about 90℃
If the a20 component is eluted, the 5i02 component will be approximately 98
This glass, which can be industrially obtained as a silica-based glass with a grade of be. By using this in place of the silicon wafer of conventional thin film transistors, it is possible to fabricate glass substrate thin film transistors.
木ガラスを基板としてこの上にS i OH1多結晶シ
リコンを堆積させる。Pのイオン注入ヲ10肩うち込む
基板温度ヲ700〜800℃に保ちながら多結晶シリコ
ン全レーサー、又は電子ビームアニールを行うかあるい
はゾーンメルトヲ行って、活性化あるいはグレインの成
長を行う。これを用いてP−channel FETの
移動度は100〜13ocr4AIsec程度のものか
えられる。Using wood glass as a substrate, S i OH1 polycrystalline silicon is deposited thereon. After P ion implantation, activation or grain growth is performed by performing polycrystalline silicon whole laser or electron beam annealing or zone melting while maintaining the substrate temperature at 700 to 800°C. Using this, the mobility of the P-channel FET can be changed to about 100 to 13 ocr4AIsec.
実施例1
図面にガラス上につけたポリシリコンP−chan−n
el、klゲートF’FJTの断面構造を示した。ガラ
スは分相性ガラスからノリカ成すに抽出(7た。即ち5
ift 75% Btu3204 Na2O5%のホウ
ケイ酸ガラスを出発原料として、500℃2時間熱処理
後5i02と’ho3Na2Q成分と’e 2N−H2
S04で溶出抽出しシリカ系ガラス金(5i0298チ
)をえた、この、厚さ0.5mのガラスをアニール後板
状に加工した。5i02(03μ)その上にLp−cv
D法により多結晶シリコン0.7μつけた、これを基板
としPのイオン注入を130KeV、 10Aの条件
下で行った。その後10WAr レーザでスポット径1
00μ基板温度700℃で10分間全面アニールを行っ
たっこれを基板としてP−channetFgT k作
製した。W/L = 16 /8のもの(Enhanc
ement )に対し電界効果正孔移動度1d130d
/Vsec 、 Vth =−1,5Vであった。Example 1 Polysilicon P-chan-n attached on glass in the drawing
The cross-sectional structure of the el, kl gate F'FJT is shown. Glass is extracted from phase splitting glass (7.
ift 75% Btu3204 Using borosilicate glass with 5% Na2O as a starting material, after heat treatment at 500°C for 2 hours, 5i02 and 'ho3 Na2Q components and 'e 2N-H2
Silica-based glass gold (5i0298) was obtained by elution and extraction with S04, and this glass with a thickness of 0.5 m was annealed and then processed into a plate shape. 5i02 (03μ) Lp-cv on it
Polycrystalline silicon of 0.7 µm was deposited using the D method, and using this as a substrate, P ion implantation was performed under conditions of 130 KeV and 10 A. Then use a 10 WAr laser with a spot diameter of 1
The entire surface was annealed at a substrate temperature of 700° C. for 10 minutes, and this was used as a substrate to fabricate a P-channel FgTk. W/L = 16/8 (Enhanc
field effect hole mobility 1d130d for
/Vsec, Vth = -1.5V.
なお熱処理、活性化、レーザーアニール時等の際のウェ
ハー破損はなかった3、
実施例2
実施例1と同様にP−ch annetA Lゲー)
、F’ETを作製した。基板ガラスとしては分相性ガラ
スからシリカ成分を抽出する方法で高シリカガラスを得
た。即ち、5i0270%B20327チNano 3
%のホウケイ酸ガラスを原料とし600℃1時間熱処理
後分相を行わしめた。これを3N−HcL溶液90℃で
溶出し、シリカ成分を抽出した。抽出後5iO297%
のガラスを再溶融し、アニール後板状に加工した1、こ
れを基板としてこの上K 5i02 (0,3μ)をつ
け、5i02上にLP−CVD法により多結晶シリコン
0.7μつけた。多結晶シリコンの中にPのイオン注入
全130Key。Note that there was no wafer damage during heat treatment, activation, laser annealing, etc. 3. Example 2 Same as Example 1, P-ch annetA L game)
, F'ET was produced. As the substrate glass, high silica glass was obtained by extracting the silica component from phase splitting glass. That is, 5i0270%B20327chi Nano 3
% borosilicate glass was used as a raw material, and after heat treatment at 600°C for 1 hour, phase separation was performed. This was eluted with a 3N-HcL solution at 90°C to extract the silica component. 5iO297% after extraction
The glass was remelted, annealed, and then processed into a plate shape. This was used as a substrate, and K 5i02 (0.3μ) was applied thereon, and polycrystalline silicon 0.7μ was deposited on the 5i02 by the LP-CVD method. A total of 130 keys of P ion implantation into polycrystalline silicon.
1 1O廓の条件下で行った。1 The test was carried out under conditions of 10°C.
その後5WXYAGレーザーで基板温度750℃スポッ
ト径80μで全面アニールし単結晶を成長させた。結晶
粒径は約10μであった。この基板上にP−chann
etFET (W/L=16/8’) enhance
mentタイプの電界効果正孔移動度は120crn/
V、 see Vth=−1,7Vであった。なお、熱
処理、活性化、アニールの際の基板の破損はなかった。Thereafter, the entire surface was annealed using a 5WXYAG laser at a substrate temperature of 750° C. and a spot diameter of 80 μm to grow a single crystal. The crystal grain size was approximately 10μ. P-channel on this board
etFET (W/L=16/8') enhance
The field effect hole mobility of ment type is 120 crn/
V, see Vth=-1.7V. Note that there was no damage to the substrate during heat treatment, activation, and annealing.
表1に本基板ガラスの物性値を石英ガラスと比以上前記
の如く本基板は石英ガラスよりもはるかに低温で合成出
来、コストも石英ガラスの1/2以下であり、物性値も
石英ガラスに近いものでありこれを用いて普通の薄膜ト
ランジスタを作製すると半導体材料を加熱アニール活性
化する際に高温で基板が破損、たわむことなく、高猛動
度のFETが得られるので工業的にすぐれたガラス基板
薄膜トランジスタであるということができる。Table 1 shows the comparison of the physical properties of this substrate glass with that of silica glass.As mentioned above, this substrate can be synthesized at a much lower temperature than silica glass, the cost is less than half that of silica glass, and the physical properties are also comparable to those of silica glass. It is similar to this, and if an ordinary thin film transistor is made using this glass, the substrate will not be damaged or bent at high temperatures when the semiconductor material is activated by heating annealing, and a high-vibration FET can be obtained, making it an excellent glass for industrial use. It can be said to be a substrate thin film transistor.
図面はガラス基板P−channetA l ケートF
’ETの断面図である。図において1は溶出ガラス基板
、2はSiO茸膜、3は多結晶シリコン膜、4ばSin
、、5はkt電極である。The drawing shows glass substrate P-channel A l Kate F
'ET is a cross-sectional view. In the figure, 1 is an eluted glass substrate, 2 is a SiO mushroom film, 3 is a polycrystalline silicon film, and 4 is a Sin
, 5 are kt electrodes.
Claims (2)
ス基板上に形成され念薄膜トランジスタ。(1) A thin film transistor formed on a silica-based glass substrate synthesized using phase separation development.
−ら構成されることを特徴とする特許 第1項記載の薄膜トランジスタ。(2) Regarding the substrate, glass, silicon oxide JE-6
- The thin film transistor described in Patent No. 1, characterized in that it is comprised of:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9118182A JPS58209163A (en) | 1982-05-31 | 1982-05-31 | Thin-film transistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9118182A JPS58209163A (en) | 1982-05-31 | 1982-05-31 | Thin-film transistor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS58209163A true JPS58209163A (en) | 1983-12-06 |
Family
ID=14019279
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9118182A Pending JPS58209163A (en) | 1982-05-31 | 1982-05-31 | Thin-film transistor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58209163A (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5582466A (en) * | 1978-12-14 | 1980-06-21 | Matsushita Electric Ind Co Ltd | Preparation of thin-film transistor |
JPS5731179A (en) * | 1980-07-31 | 1982-02-19 | Sharp Corp | Formation of thin-film transistor |
-
1982
- 1982-05-31 JP JP9118182A patent/JPS58209163A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5582466A (en) * | 1978-12-14 | 1980-06-21 | Matsushita Electric Ind Co Ltd | Preparation of thin-film transistor |
JPS5731179A (en) * | 1980-07-31 | 1982-02-19 | Sharp Corp | Formation of thin-film transistor |
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