JPS58209135A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To facilitate the operation of a test by selectively fitting semiconductor switches among pads around a semiconductor chip and among the pads and an internal circuit, transmitting a signal through a select bus and switching connection among the pads and the internal circuit. CONSTITUTION:Switch elements 5a-5g are set up among the pads 2a-2g and the internal circuits A-F in a predetermined manner, 5a, 5c, 5e are formed in N channels and 5b, 5d, 5f in P channels, and the pad 2g is connected to a select bus 6. The bus 6 is connected to each input to the elements 5a-5f. When a 'H' signal is transmitted over the pad 2g from a terminal T4 for the test, the elements 5a, 5c, 5e are turned OFF and others ON, and the circuits B, D, E can be inspected. When a 'L' signal is transmitted from the terminal T4, ON-OFF is reversed, and the circuits A, C, E can be inspected. According to the constitution, terminals T may be n+1 pieces on 2n pads, the IC of a large number of pins can be tested by a tester of a small number of terminals, and a test board is easily manufactured.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor integrated circuit device, and more particularly to the improvement of a semiconductor integrated circuit device that facilitates dust removal by an LSI tester or the like.

[Technical background of the invention and its problems]

Recently, advances in L and SI technology have made it possible to integrate a large number of elements into one chip, and with this, the difficulty of t-testing all the functions included in one chip has come to the fore. are doing. In addition, as Rudai's performance increases, the number of input and output pins will also increase, especially in the logic circuit issue.
It is expected that the output circuit waiting for the input/output pin to reach the oo pin will be destroyed. To test such a multi-bin circuit, an LSI tester is required that has test terminals equal to or greater than the number of bins supported by the integrated circuit to be measured. But 6.
Multi-pin LSI gusta are extremely expensive, and the large number of connections between test terminals and pins makes the operation of the equipment extremely cumbersome. For this reason, there is a strong demand for a technology that can measure and evaluate multi-bin integrated circuits with a low-cost LSI tester and an LSI tester with a small number of retests.

FIG. 1 is a diagram illustrating an integrated circuit test force formula designed to meet the above requirements. On the periphery of the semiconductor chip 10, there are bonding pads 2&r2 corresponding to input circuits A, B, C, D and output circuits E, F.
br2c+2d, 2e, and 2f are provided, respectively.

Test terminal Ti + T2 + on the LSI tester side
T3 +T4 are four, and the terminals Tl t~+T3
through contacts 4a+4bt4c'i of relay 3! Nomad 2a + 2b, Nomad 2c + 2d and No7ad 2
e.

Each of the 2nd floor is covered with Ha.

Further, the test terminal T4 is connected to the relay 3.

Therefore, 1 is applied to relay 3 from test terminal T47.
By changing the number of test terminals T+t~+T3
and each pad 2a r~.

Being able to cut through evil and connect with 2F becomes a skill.

However, in this case, it is necessary to prepare a large number of switching relays (contacts) depending on the number of integrated circuits and rads (bins), and the test board (performance board) becomes complicated. There was a temple cabinet meeting that made the study difficult.

[Purpose of the invention]

For the purpose of the present invention, is it possible to measure and evaluate multi-pin integrated circuits without complicating the test board? It is an object of the present invention to provide a semi-integrated integrated circuit device that can perform testing using an LSI 7'' star with a small number of test terminals and contributes to facilitating test operations.

[Summary of the invention]

The gist of the present invention is to achieve the same function as the system shown in FIG. 1 by connecting some circuits to the semi-integrated chip in the external circuitry such as the relays.

That is, the present invention provides a semiconductor compensation circuit device having one pad arranged on the side side of a cow 49f-tenno and connected to an internal circuit, in which a semiconductor switch is provided between the pad and the internal circuit. In addition to connecting the elements to each other, a select path is provided which is connected to each input terminal of these switch elements, and by applying a signal from the outside to the select bus mentioned above, the function test is excluded. The connection between the pad and the internal circuit is shown in a cutaway view.

〔Effect of the invention〕

According to the present invention, it is possible to control the ON/OFF state of the switching element by applying an external signal to the select path, thereby controlling the connection state between the pad connected to the test terminal and the internal circuit. can be cut and delivered. Therefore, even integrated circuits with a large number of pins can be easily tested using an LSI tester with a small number of test terminals.

In addition, there is no inconvenience such as requiring external circuits such as relays or complicating the test grid.
[l]] FIG. 2 is a circuit diagram showing the main part of an information circuit device according to one embodiment of the present invention, and FIG. 3 is a diagram showing the main part structure of the above-mentioned embodiment. FIG. Note that the same parts as in FIG. 1 are designated by the same reference numerals throughout, and detailed explanation thereof will be omitted. The pad 2a is connected to the input circuit A and is also connected to the pad 2b via a switch element 5a consisting of a MOS transistor (MOS transistor), and like this pad 2b, the pad 2c is connected to the input circuit CK. It is connected to the node 2d via the switch element 5cf, and the node 2d is connected to the node 2d through the switch element 5cf.
is connected to the input circuit D K via the switch element 5d.
It is. Further, ・Set 2@ is connected to the output circuit EK and connected to the node 2f/' via the switch element 5e.
The C-connected motherboard 2f is connected to the output circuit FK via a switch element 5f. Here, switch element 5
a + 5 c 156 is N channel, switch +5
b, 5d, and 5f are P channels.

- 10,000, the pad 2g is connected to the select bus 6 arranged around the periphery of the semi-integrated chip l, and this select path 6 is connected to the valley input terminal of @Δ已 switch 15a +~, 5f. has been done. The test terminal TI of the LfS desk is brought into contact with the pad 2b, the terminal T2 is brought into contact with the pad 2d, the terminal T3 is brought into contact with the pad 2f, and the terminal T4 is brought into contact with the pad 2gK.

To solve this problem, apply a high 1 level signal to the pad 2 g K High 1 level from the test terminal T4. Switch elements 5 a + 5 c + 5 e are OFF, and switch elements 5 b, 5 d, and 5 f are ON. Then, circuits B, D, and F can be checked. Also,
Low 1 level from test terminal T4 to pad 2g
- When a signal is applied, the switch element 5 a r
5 cr 5 e is ON, switch elements 5b, 5
d, 5f are OFF, circuit A.

C and E can be checked.

Thus, according to this example, there are two input/output terminals ()
The number of test terminals of the LSI tester is (n) for the number of (2n)
+1) That is a good thing, LSI with fewer terminals
It is possible to test a multi-bin accumulation path using a tester. This method is effective when checking good quality products in the wafer state (guiso r), and it is necessary to make 222 contact pinots. It also has advantages such as ease of use.

2. The present invention is not limited to the above-mentioned examples, and may be implemented with various modifications without departing from the spirit thereof. For example, as shown in FIG. 4, there are two select paths, cut-off hats 2g and 2b are provided, and switch elements 7a+ to 7di are provided to form a test terminal T.

It is also possible to switch the circuit to any of the three circuits A, B, and C. In this bank, the input/output terminal (-4'
) of e (3n), the test Nishiko is (n + 2
) That would be a good thing. There are 100,000,000 ways to do this, and it is also possible to reduce it to Daifuku with a of the terminal for the test, which is necessary for the test. 1.The switch switch is not a MOS F7 model, but the switch is equipped with a switch that can be formed on the chip.

[Brief explanation of drawings]

Figure 1 explains the Hatsu and youngest son ceremony, Figures 2 and 3 are each uninvented - S Figure 3 is a plan view, and Figure 4 explains the modification. This is a picture of Hou Ni.
゛1... Semiconductor chip, 2a, ~, 2h... Pad,
5 & P ~+ 5 g + 7 SL + ~+
7 d"' Switch element, 6...Select path. Patent attorney Suzue Takehiko 163 11 ^ H2r11 .43,1 4g 1

Claims (2)

[Claims] (1) Pads arranged on the periphery of the semiconductor chip and connected to the internal circuit, the above-mentioned i4 pad, and the switch selectively connected between the above-mentioned pad and the internal circuit, and these switches. Select terminals connected to each input terminal of the element.
The above-mentioned
1. A semiconductor integrated circuit device characterized in that the condition of f-rad and internal circuitry can be varied. (2) The semiconductor chip switch confectionery according to claim 1, wherein the selection path is located outside the pad. It must consist of a MOS transformer! # Scope of the ship's main function Item dIll: The main body of the semiconductor integrated circuit device.