JPH0290650A - Semiconductor device - Google Patents

Abstract

PURPOSE:To facilitate a work at the time of a test and to improve a testability in a semiconductor integrated circuit using an insulated gate field-effect transistor by a method wherein an output power reducing circuit and a pad for output control signal use are connected to the output control signal of an input/output driving circuit cell. CONSTITUTION:An output power reducing circuit 3 and a pad 12 for output control signal use are connected to an input/output driving circuit 2, whereby the state of an output control signal of the input/output driving circuit cell can be monitored outside of an LSI chip. Moreover, in case a signal for output control use is inputted from the exterior of the chip through the pad 12, there is a low output power buffer element 8 in the interior of the circuit 3 and as the output control signal can not overcome the signal from the outside of the chip, the output control signal of the input/output driving circuit cell can be directly controlled.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to simplification of work associated with reliability testing in master slice type or standard cell type semiconductor integrated circuits.

[Prior Art J] In a conventional master slice type or standard cell type semiconductor integrated circuit, it is possible to control and monitor the output control signals of the input/output drive circuit cells arranged around the LSI chip from outside the LSI chip. could not.

[Problem to be solved by the invention] However, in the conventional technology, the output control signal cannot be controlled outside the LSI chip, and the test state is created and tested using the logic circuit inside the LSI chip, so testability is extremely poor. It was bad.

SUMMARY OF THE INVENTION The present invention is intended to solve the problems of conventional semiconductor devices, and its purpose is to provide an input/output drive circuit cell that includes an output control signal with good testability.

[Means to solve the problem]

The semiconductor device of the present invention includes: a) a semiconductor integrated circuit using an insulated gate field effect transistor;

b) an input/output drive circuit cell having an output control signal, and c) an output capability reduction circuit and an output control signal pad connected to the output control signal of the input/output drive circuit cell.

[Example] Examples of the present invention will be described below based on the drawings. FIG. 1 is a circuit diagram showing a first embodiment. In Figure 1, the part surrounded by solid line 1 is the input/output drive circuit cell, broken uA.
The part surrounded by 2 is an input/output drive circuit, and the part surrounded by a broken line 3 is an output capability reduction circuit. Further, a low output capacity buffer element 8 is used in the output capacity reduction circuit 3.

By connecting the output capability reduction circuit 3 and the output control signal pad 12 to the input/output drive circuit 2, the state of the output control signal can be monitored outside the LSI chip. In addition, when inputting an output control signal from outside the LSI chip through the output control signal pad 12, a low output capacity buffer element 8 is provided inside the output capacity reduction circuit 3.
Since signals from outside the SI chip cannot be overcome, the output control signals of the input/output driving circuit cells can be directly controlled.

The above embodiment is just one example, and similar effects can be obtained even when connected as shown in FIG.

In the embodiments described above, the operability during testing is improved, the associated work is facilitated, and the testability is also improved.

[Effects of the Invention] As explained above, the present invention can simplify testing work by adding and connecting an output capacity reduction circuit and an output control signal pad in an input/output drive circuit cell. , it also has the effect of improving testability.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a first embodiment, FIG. 2 is a circuit diagram showing a second embodiment, and FIG. 3 is a circuit diagram of a conventional input/output drive circuit cell. 101.108...Input terminals 102, 105. 103, l 06゜104, 10 11.15 ・ 13 ・ ・ ・ 12.14 ・ l , 4.7 ・ 2, 5 ・ ・ 8, 9 ・ ・ ・ Output terminal Output control terminal Connection terminal Input/output pad output Pad input/output drive circuit for pad output control terminal Cell input/output drive circuit Low output capacity buffer One element replacement 1 Figure above 2 days Applicant: Seiko Epson Corporation Agent Patent attorney: Masayoshi Kamiyanagi (1 other person) No. 30

Claims (1)

[Claims] (1) a) In a semiconductor integrated circuit using an insulated gate field effect transistor, b) In an input/output drive circuit cell having an output control signal, and c) In a semiconductor integrated circuit using an insulated gate field effect transistor; A semiconductor device characterized by connecting a circuit and an output control signal pad.