JPS58208845A - 重ね合せ表示方式 - Google Patents
重ね合せ表示方式Info
- Publication number
- JPS58208845A JPS58208845A JP57092863A JP9286382A JPS58208845A JP S58208845 A JPS58208845 A JP S58208845A JP 57092863 A JP57092863 A JP 57092863A JP 9286382 A JP9286382 A JP 9286382A JP S58208845 A JPS58208845 A JP S58208845A
- Authority
- JP
- Japan
- Prior art keywords
- slave
- crtc
- crt
- display
- crt controller
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000015654 memory Effects 0.000 claims description 25
- 230000001360 synchronised effect Effects 0.000 claims description 13
- 238000000034 method Methods 0.000 claims description 4
- 230000001934 delay Effects 0.000 claims description 2
- 102100029968 Calreticulin Human genes 0.000 abstract description 61
- 101100326671 Homo sapiens CALR gene Proteins 0.000 abstract description 26
- 238000010586 diagram Methods 0.000 description 11
- 230000003111 delayed effect Effects 0.000 description 4
- 102100040775 CREB-regulated transcription coactivator 1 Human genes 0.000 description 2
- 101000891939 Homo sapiens CREB-regulated transcription coactivator 1 Proteins 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000002457 bidirectional effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000004397 blinking Effects 0.000 description 1
- 210000004556 brain Anatomy 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- PLAIAIKZKCZEQF-UHFFFAOYSA-N methyl 6-chloro-2-oxo-3h-1,2$l^{4},3-benzodithiazole-4-carboxylate Chemical compound COC(=O)C1=CC(Cl)=CC2=C1NS(=O)S2 PLAIAIKZKCZEQF-UHFFFAOYSA-N 0.000 description 1
- 238000003786 synthesis reaction Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Landscapes
- Digital Computer Display Output (AREA)
- Controls And Circuits For Display Device (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57092863A JPS58208845A (ja) | 1982-05-31 | 1982-05-31 | 重ね合せ表示方式 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57092863A JPS58208845A (ja) | 1982-05-31 | 1982-05-31 | 重ね合せ表示方式 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58208845A true JPS58208845A (ja) | 1983-12-05 |
| JPH0373897B2 JPH0373897B2 (enrdf_load_stackoverflow) | 1991-11-25 |
Family
ID=14066260
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57092863A Granted JPS58208845A (ja) | 1982-05-31 | 1982-05-31 | 重ね合せ表示方式 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58208845A (enrdf_load_stackoverflow) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60135985A (ja) * | 1983-12-26 | 1985-07-19 | 株式会社日立製作所 | 表示制御装置 |
| USRE33922E (en) * | 1984-10-05 | 1992-05-12 | Hitachi, Ltd. | Memory circuit for graphic images |
| US5175838A (en) * | 1984-10-05 | 1992-12-29 | Hitachi, Ltd. | Memory circuit formed on integrated circuit device and having programmable function |
| JPH06161414A (ja) * | 1993-06-14 | 1994-06-07 | Hitachi Ltd | 表示制御システム |
| US5424981A (en) * | 1984-10-05 | 1995-06-13 | Hitachi, Ltd. | Memory device |
| US5448519A (en) * | 1984-10-05 | 1995-09-05 | Hitachi, Ltd. | Memory device |
| US5592649A (en) * | 1984-10-05 | 1997-01-07 | Hitachi, Ltd. | RAM control method and apparatus for presetting RAM access modes |
| US5923591A (en) * | 1985-09-24 | 1999-07-13 | Hitachi, Ltd. | Memory circuit |
| US6028795A (en) * | 1985-09-24 | 2000-02-22 | Hitachi, Ltd. | One chip semiconductor integrated circuit device having two modes of data write operation and bits setting operation |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5582362A (en) * | 1978-12-18 | 1980-06-21 | Hitachi Ltd | Operation processing unit |
-
1982
- 1982-05-31 JP JP57092863A patent/JPS58208845A/ja active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5582362A (en) * | 1978-12-18 | 1980-06-21 | Hitachi Ltd | Operation processing unit |
Cited By (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60135985A (ja) * | 1983-12-26 | 1985-07-19 | 株式会社日立製作所 | 表示制御装置 |
| US5610622A (en) * | 1983-12-26 | 1997-03-11 | Hitachi, Ltd. | Display control device |
| US5606338A (en) * | 1983-12-26 | 1997-02-25 | Hitachi, Ltd. | Display control device |
| US5523973A (en) * | 1984-10-05 | 1996-06-04 | Hitachi, Ltd. | Memory device |
| US5175838A (en) * | 1984-10-05 | 1992-12-29 | Hitachi, Ltd. | Memory circuit formed on integrated circuit device and having programmable function |
| US5448519A (en) * | 1984-10-05 | 1995-09-05 | Hitachi, Ltd. | Memory device |
| US5450342A (en) * | 1984-10-05 | 1995-09-12 | Hitachi, Ltd. | Memory device |
| US5475636A (en) * | 1984-10-05 | 1995-12-12 | Hitachi, Ltd. | Memory device |
| US5493528A (en) * | 1984-10-05 | 1996-02-20 | Hitachi, Ltd. | Memory device |
| US5499222A (en) * | 1984-10-05 | 1996-03-12 | Hitachi, Ltd. | Memory device |
| US6643189B2 (en) | 1984-10-05 | 2003-11-04 | Hitachi, Ltd. | Memory device |
| US5592649A (en) * | 1984-10-05 | 1997-01-07 | Hitachi, Ltd. | RAM control method and apparatus for presetting RAM access modes |
| US5424981A (en) * | 1984-10-05 | 1995-06-13 | Hitachi, Ltd. | Memory device |
| USRE33922E (en) * | 1984-10-05 | 1992-05-12 | Hitachi, Ltd. | Memory circuit for graphic images |
| US5719809A (en) * | 1984-10-05 | 1998-02-17 | Hitachi, Ltd. | Memory device |
| US5781479A (en) * | 1984-10-05 | 1998-07-14 | Hitachi, Ltd. | Memory device |
| US5838337A (en) * | 1984-10-05 | 1998-11-17 | Hitachi, Ltd. | Graphic system including a plurality of one chip semiconductor integrated circuit devices for displaying pixel data on a graphic display |
| US6359812B2 (en) | 1984-10-05 | 2002-03-19 | Hitachi, Ltd. | Memory device |
| US6028795A (en) * | 1985-09-24 | 2000-02-22 | Hitachi, Ltd. | One chip semiconductor integrated circuit device having two modes of data write operation and bits setting operation |
| US5923591A (en) * | 1985-09-24 | 1999-07-13 | Hitachi, Ltd. | Memory circuit |
| JPH06161414A (ja) * | 1993-06-14 | 1994-06-07 | Hitachi Ltd | 表示制御システム |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0373897B2 (enrdf_load_stackoverflow) | 1991-11-25 |
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