JPS58207633A - Defect detection system - Google Patents

Abstract

PURPOSE:To securely detect defects by preventing malfunctions generated by small pattern projection or quantization errors by a method wherein an inspection is prohibited, when the outputs of guard sensors provided on both sides at positions apart from a center by previously determined values in the direction crossed with a direction are in the output relation which is previously determined. CONSTITUTION:The number of logic ''0''s which exists in sensors S1 and S2 in horizontal directions from the bit positions P of these sensors S1 and S2 is inputted to a subtracting circuit 8, then the difference thereof is compared with the reference value in a comparing circuit 11, and accordingly the processing whether it can be used as the center or not is performed. When the output from the comparing ciruit 11 is logic ''1'', i.e. when the bit position P can be used as the center and if logic ''0'' is contained in either bit position of the guard sensor G1 or of guard sensor G2, the number of logic ''0''s which exists in sensors S3 and S4 in vertical directions from the bit positions P of the sensors S3 and S4 is inputted to an adding circuit 9 on the other hand, and, if the sum output thereof is within the range set by comparing circuits 14 and 15, then a defect signal generates from a NAND circuit 16.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to an improvement in a defect inspection method using intersecting length measurement sensors when inspecting patterns for defects.

(2)0 Background of the Invention On printed circuit boards and integrated circuits, four-conductor patterns are formed through a process using a photomask. It is an important matter that determines the life or death of the electronic circuit that is used.
Instead of the primitive visual inspection method using microscopic theory, an automatic horizontal placement device has been developed for practical use in detecting defects. However, this device may not be able to successfully perform its detection function depending on the state of the irregularities surrounding the defect occurring in the conductive pattern, and there is a need for technical improvements.

(3) Prior art and problems The device that suffers from the above-mentioned disadvantages measures the length of the 4S electric pattern in the left and right directions to find its center, and then measures the length of the 4S electric pattern in the left and right directions, and then measures the length of the pattern in the vertical direction from the center. A method is adopted in which defects are determined by determining the sub-length of the protrusions6.This method of simply performing the sub-length in the orthogonal direction causes malfunctions in determining defects in small pattern protrusions that can be measured, resulting in rounded and rounded protrusions. There is a problem that a corner portion of a pattern is mistakenly determined to be a defect.

(4) Purpose of the Invention The present invention was created to solve the above-mentioned technical problems, and its purpose is to prevent malfunctions caused by small pattern protrusions or sweetening errors and to ensure reliable defect detection. The purpose of this invention is to provide a defect inspection method that can be used.

(5) 9 Structure of the Invention The purpose of this invention is to directly capture a pattern optically, to binarize it, to preserve the pattern of the pattern, to store it in a memory circuit, and then to create a binarized pattern. Measure the length of the non-pattern part in one of the intersecting directions at any pit position where there is a signal representing the non-pattern part of In a defect inspection method that measures the length of a pattern portion and inspects whether or not there is a defect in the pattern, a sensor is provided at a position separated by a predetermined value on both sides from the center in a direction intersecting the one direction above. This is accomplished by inhibiting the above test when the outputs of the guard stations are in a predetermined output relationship.

(6) First Embodiment The present invention will be described in detail below with reference to the accompanying drawings.

FIG. 1 shows the configuration of an apparatus for implementing the present invention.

Reference numeral 1 indicates a sample to be inspected, such as a printed circuit board, which has a pattern consisting of a patterned portion 2 and a non-patterned portion 3. Reference numeral 4 denotes an imaging 1 system, such as a television camera, and a laser scanning device, which scans the sample to be inspected, reads the pattern, and supplies the pattern to the binarization circuit 5. 6
is a storage circuit that is synchronized with the scanning of the imaging system 4 and sequentially stores the binarized signals of the binarization circuit 5. 7 is a test circuit, the details of which are shown in FIG.

In FIG. 2, for each arbitrary bit position P of the pattern which is binarized and stored in the memory circuit 6, the required bits are input from the memory circuit 6 in a direction that intersects, for example perpendicularly, with this as the center. The length measurement sensor is Sl, 82.83. S4
From the bit position P, the length measurement sensor 83
゜ Guard sensor Gl is placed in the same direction as the length measurement sensors 81 and 82 at a position separated by a predetermined value in the direction of S4.
, G2 are provided.

611j length sensors 81 and 82 each subtract the number of consecutive identical binary signals from the pit position P by a circuit 8.
is configured to supply a corresponding input of the . or,
The length measurement sensors 83 and 84 each measure bit positions [P to the sensor Sl].

S2 is configured to supply the number of consecutive identical binary signals to the corresponding input of the adder circuit 9. In addition to this, guard sensor G1. G2 separately corresponds to each of the above-mentioned sensors S1.82. S3. It is configured to logically supply the same signal as the signal counted above to the corresponding input of the two-person AND circuit 10 when all pit positions have inverted signals of the binary signals counted in S4. .

The output of the subtraction circuit 8 is connected to one input of a comparison circuit 11, and the other input of the comparison circuit 11 is configured to be supplied with a preset reference value. The output of the comparison circuit 11 is connected to one input of the two-person AND circuit 12,
The output of the AND circuit 10 is connected to the other input. The output of the AND circuit 12 is connected to one input of the two-man AND circuit 13.

The output of the adder circuit 9 is connected to one input of the upper limit comparison circuit 14 and the lower limit comparison circuit 15, the other input of the upper limit comparison circuit 14 is supplied with a preset upper limit reference value, and the other input of the lower limit comparison circuit 15 is connected to the other input of the upper limit comparison circuit 14. The configuration is such that a preset lower limit reference value is supplied to the input. The outputs of both comparison circuits 14 and 15 are connected to a NAND circuit 16, and the output of the NAND circuit 16 is connected to the other input of the AND circuit 13.

Next, the operation of the apparatus implementing the present invention having the above configuration will be explained.

A storage circuit in which a pattern formed on the sample to be inspected 1 is read by an imaging system 4, the analog signal thereof is binarized by a binarization circuit 5, and a storage operation is generated in synchronization with the imaging system 4. 6 is stored. Therefore, when the storage operation is completed, the pattern portion 2 of the pattern of the sample to be inspected is set to the logical value of one of the binary signals, for example, "1".
``'', and the non-pattern portion 3 is binarized to the other logical value of the binary signals, for example, "O", and the pattern form is preserved and stored.

After this memorization operation is completed, the length measurement sensors S1°82, S3
．． The intersection point P of S4 is located at each pit position of the memory circuit 6, and from that position, the sensors S1, 82 and the sensor S3. S
Each logical value of a pit position extending a predetermined number of times in a direction intersecting with S1, S2. S3, 84, and guard sensor G1. Each logical value of the pit position corresponding to 4 in G2 is taken in.

Assuming that such intake has come to a pit position P as shown in FIG. 3, for example, the defect inspection at this pit position is as follows.

From the pit position P (ia logic is "0") of the sensors S1 and S2, the number of logical "θ" existing in these sensors 81°S2 in the left and right direction is input to the subtraction circuit 8, that is, The length is measured, and the difference between the two is output from the subtraction circuit 8.

The difference is compared with the reference value in the comparator circuit 11, and the comparator circuit 1
If a logic "θ"' is generated from the comparator circuit, which indicates that no output can be obtained from 1, that is, the bit position fP cannot be centered, then the above-mentioned question can be used as to whether or not it can be used as the center for the next pit position. Processing takes place.

When the output from the comparator circuit 11 is the logic u1'', that is, it is centered around the pit position P (the center is found), the guard sensor G1 and the guard sensor G2 have a logic "θ" at either of the pit positions. ”, logic “1” is input to each input of the AND circuit 10, and logic “1” is input from its output.
1# is generated, and therefore the AND circuit 12 also outputs a logic “1”.
” occurs.

On the other hand, sensor 83. These sensors 83. The number of logical "0"s present in S4 is manually input to the adder circuit 9, that is, length measurement in the vertical direction is performed. The sum output of the power lI calculating circuit 9 is the comparator circuit 14.1.
If it is not within the range set to 5, a logic "0" is generated at the output of the NAND circuit 16. Therefore, the AND circuit 13
No defect signal is generated. Conversely, if the upper Hapioro output is within the range set in the comparator circuit 14.15, then
A defect signal is generated from the NAND circuit 16.

In defect inspection for such a pit position P,
Either the guard sensor G1 or the card sensor G2 includes a wire 11" in all of its pit positions (for example, in the example shown in FIG. ), even if the center is found as described above, the output of the AND circuit 10 is logic "0", so the logic "1#" is not generated from the AND circuit 12. In other words, regarding the pit position P, Therefore, inspection of small protrusions A as shown in FIG. 3 is prohibited.
Malfunctions in defect inspection caused by this can be prevented. Such a function of preventing malfunctions in defect inspection is exhibited even in the slanted slope portion of the pattern, and reliability in defect inspection of the pattern can be obtained.

Also, a sensor such as that described above may be provided at a 90 degree offset, and associated circuitry may be provided to produce the same processing as described above.

In the above embodiment, the pattern section is set to logic "θ",
It is also possible to construct a circuit with the non-pattern portion set to logic "1".

(7) 9 Effects of the Invention In short, according to the present invention, a guard is placed at a position a predetermined value γ away from the intersection point in the direction that intersects the direction to find the center of the intersecting length measurement sensors. Since a sensor is installed and defect inspection is prohibited depending on whether or not the output is in a predetermined relationship, it is possible to prevent malfunctions caused by small pattern protrusions or quantization errors and to perform reliable defect inspection. , such effects can be achieved by adding relatively simple circuits.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of an apparatus for carrying out the present invention, FIG. 2 is a detailed diagram of an inspection circuit, and FIG. 3 is an enlarged diagram of a part of a pattern of a sample to be inspected. In the figure, 1 is a sample to be inspected, 4 is an imaging system, 5 is a binarization circuit, 6 is a storage circuit, 7 is an inspection circuit, and Sl. S2. S3. S4 is a length measurement sensor, Gl and G2 are guard sensors, 8 is a subtraction circuit, 9 is an addition circuit, 10°12.13
is an AND circuit, 11 is a comparison circuit, 14 is an upper limit comparison circuit,
15 is a lower limit comparison circuit, and 16 is a NAND circuit. Figure 1 Figure 2

Claims (1)

[Claims] 1) After optically reading a pattern and binarizing it, saving the type of the pattern and storing it in a storage circuit, there is a signal representing a non-pattern part of the binarized pattern. Measure the length of the non-pattern part in one of the intersecting directions at an arbitrary bit position to find its center, and measure the length of the non-pattern part from the center in the direction intersecting the above one direction to find the pattern. In a defect inspection method for inspecting whether there is a defect in a card, the output of a card sensor provided at a predetermined value on both sides of the center in a direction intersecting the one direction is predetermined. A defect inspection method characterized in that the above inspection is prohibited when there is an output relationship. 2) The defect inspection method according to claim 1, wherein the upper and lower intersections are orthogonal.