JPH0134323B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to an improvement in a defect inspection method using intersecting length measurement sensors when inspecting a pattern for defects.

(2) Background of the Invention Conductive patterns are formed on printed circuit boards and integrated circuits through a process using a photomask. This is an important matter that determines the life or death of a circuit, and automatic inspection equipment is being developed for practical use in place of the primitive method of visual inspection using a microscope to detect defects. However, this device may not be able to successfully perform its detection function depending on the state of irregularities surrounding the defect occurring in the conductive pattern, and therefore, technical improvements are desired.

(3) Prior art and problems The device that causes the above-mentioned problems measures the length of the conductive pattern in the horizontal direction to find its center, and then measures the length of the pattern in the vertical direction from the center. A method is used to determine defects. This method of simply measuring the length in orthogonal directions causes malfunctions in determining defects in small pattern protrusions that would otherwise be acceptable.
There is a problem that a corner part of a rounded pattern is mistakenly determined to be a defect.

(4) Purpose of the Invention The present invention was devised to solve the above-mentioned technical problem, and its purpose is to provide a defect inspection that can prevent malfunctions caused by small pattern protrusions or quantization errors and ensure defect detection. The purpose is to provide a method.

(5) Purpose of the invention This purpose is to optically read a pattern, to binarize it, to save the form of the pattern and to store it in a storage circuit, and then to generate a signal representing the non-pattern part of the binarized pattern. Measure the length of the non-pattern part in one of the intersecting directions at an arbitrary bit position to find its center, and measure the length of the non-pattern part from the center in the direction intersecting the one direction. In a defect inspection method for inspecting whether or not there is a defect in the pattern, the output of a guard sensor installed at a predetermined value on both sides of the center in a direction crossing the one direction is determined in advance. This is achieved by inhibiting the above-mentioned test when a determined output relationship exists.

(6) Embodiments of the invention Hereinafter, embodiments of the invention will be described with reference to the accompanying drawings.

FIG. 1 shows the configuration of an apparatus for implementing the present invention.
Reference numeral 1 indicates a sample to be inspected, such as a printed circuit board, which has a pattern consisting of a patterned portion 2 and a non-patterned portion 3. Reference numeral 4 denotes an imaging system, such as a television camera or a laser scanning device, which scans the sample to be inspected, reads the pattern, and supplies the pattern to the binarization circuit 5. Reference numeral 6 denotes a storage circuit which is synchronized with the scanning of the imaging system 4 and sequentially stores the binarized signals from the binarization circuit 5. 7
is a test circuit, the details of which are shown in FIG.

In FIG. 2, for each arbitrary bit position P of the pattern which is binarized and stored in the memory circuit 6, required bits in a direction that intersects, for example perpendicularly, can be inputted from the memory circuit 6. The length measurement sensors are indicated by S1, S2, S3, and S4, and the length measurement sensors S1 and S2 are located in the same direction as the length measurement sensors S1 and S2 at a position separated from the bit position P by a predetermined value in the direction of the length measurement sensors S3 and S4. guard sensor G
1 and G2 are provided.

The length measurement sensors S1 and S2 are each configured to supply the number of successive identical binary signals from the bit position P to the corresponding input of the subtraction circuit 8. Further, the length measurement sensors S3 and S4 are each configured to supply the number of consecutive same binary signals from the bit position P to the corresponding input of the addition circuit 9, assuming that the sensors S1 and S2 are the same. has been done. In addition to this, guard sensors G1, G
2 is for each of the above-mentioned sensors S1, S2, S
3. When the inverted signal of the binarized signal counted in S4 is present at all bit positions, it is configured to logically supply the same signal as the signal counted above to the corresponding input of the two-input AND circuit 10. ing.

The output of the subtraction circuit 8 is connected to one input of a comparison circuit 11, and the other input of the comparison circuit 11 is configured to be supplied with a preset reference value. The output of the comparison circuit 11 is a two-input AND circuit 1
2, and the output of the AND circuit 10 is connected to the other input. Then, the output of the AND circuit 12 is the two-input AND circuit 1
Connected to one input of 3.

The output of the adder circuit 9 is connected to one input of the upper limit comparison circuit 14 and the lower limit comparison circuit 15, the other input of the upper limit comparison circuit 14 is supplied with a preset upper limit reference value, and the other input of the lower limit comparison circuit 15 is connected to the other input of the upper limit comparison circuit 14. It is configured such that a preset lower limit reference value is supplied to the input. Both comparison circuits 14 and 15
The output of the NAND circuit 16 is connected to the NAND circuit 16, and the output of the NAND circuit 16 is connected to the other input of the AND circuit 13.

Next, the operation of the apparatus implementing the present invention having the above configuration will be explained.

The pattern formed on the sample to be inspected 1 is read by the imaging system 4, and its analog signal is binarized by the binarization circuit 5, and a storage operation is generated in synchronization with the imaging system 4. It is stored in the memory circuit 6. Therefore, when the storage operation is completed, the pattern portion 2 of the pattern of the sample to be inspected is set to one of the logical values of the binary signals, for example, "1".
Further, the non-pattern portion 3 is binarized to the other logical value of the binary signal, for example, "0", and stores the pattern type thereof.

After this memorization operation is completed, the length measurement sensors S1, S
2, S3, and S4 is located at each bit position of the memory circuit 6, and from that position, the sensors S1,
Each logic value of a predetermined number of bit positions extending in the cross direction of S2 and sensors S3, S4 is taken into each sensor S1, S2, S3, S4, and the bits corresponding to guard sensors G1, G2 are also taken in. Capture each logical value of the position.

Assuming that such capture occurs, for example, at a bit position P as shown in FIG. 3, the defect inspection at this bit position is as follows.

Bit position P (logic “0”) of sensors S1 and S2
It is. ) in the left-right direction from these sensors S1, S
The number of logical "0"s existing in the subtraction circuit 8 is input to the subtraction circuit 8, that is, the length is measured in the left and right directions, and the difference between these two is outputted from the subtraction circuit 8. The difference is compared with a reference value in the comparator circuit 11, and if a logic "0" is generated from the comparator circuit, which indicates that no output can be obtained from the comparator circuit 11, that is, the bit position P cannot be centered, then the next bit is determined. The above-described processing is performed on a position to determine whether it can be used as a center.

When the output from the comparator circuit 11 is a logic "1", that is, the center can be found at the bit position P (the center can be found), the guard sensor G1 and the guard sensor G2 have a logic "0" at either of the bit positions. ”, a logic “1” is input to each input of the AND circuit 10, a logic “1” is generated from its output, and therefore a logic “1” is also generated from the AND circuit 12.
occurs.

On the other hand, the number of logic "0"s present in the sensors S3, S4 in the vertical direction from the bit position P of the sensors S3, S4 is input to the adder circuit 9, that is, the length is measured in the vertical direction. If the sum output of the adder circuit 9 is not within the range set in the comparator circuits 14 and 15, logic "0" is output to the NAND circuit 16 output.
occurs. Therefore, no defect signal is generated from the AND circuit 13. Conversely, if the sum output is within the range set in the comparison circuits 14 and 15, the NAND circuit 16 generates a defect signal.

In defect inspection for such a bit position P, guard sensor G1 or card sensor G2
If any one of them contains logic "1" in all its bit positions (for example, in the example shown in FIG. 3, all bit positions of Gar sensor G2 contain logic "1"), the center can be found as described above. Even if the output of the AND circuit 10 is a logic "0", the AND circuit 12 does not generate a logic "1". In other words, testing for that bit position P is prohibited. Therefore, malfunctions in defect inspection caused by small protrusions A as shown in FIG. 3 can be prevented. Such defect inspection malfunction prevention function is also exhibited in the quantization error portion of the pattern, and reliability of pattern defect inspection can be obtained.

Also, a sensor such as that described above may be provided at a 90 degree position change, and associated circuitry may be provided to produce the same processing as described above.

In the above embodiment, the circuit can also be constructed with the pattern portion set to logic "0" and the non-pattern section set to logic "1".

(7) Effects of the Invention In summary, according to the present invention, a guard sensor is provided at a position a predetermined value away from the intersection of intersecting length measurement sensors in a direction intersecting the direction for finding the center. Since defect inspection is prohibited depending on whether the outputs are in a predetermined relationship or not, it is possible to prevent malfunctions caused by small pattern protrusions or quantization errors and to perform reliable defect inspection. Such an effect can be achieved by adding a relatively simple circuit.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of an apparatus for carrying out the present invention, FIG. 2 is a detailed diagram of an inspection circuit, and FIG. 3 is an enlarged diagram of a part of a pattern of a sample to be inspected. In the figure, 1 is the sample to be inspected, 4 is the imaging system, and 5
is a binarization circuit, 6 is a storage circuit, 7 is a test circuit, S
1, S2, S3, S4 are length measurement sensors, G1, G2
is a guard sensor, 8 is a subtraction circuit, 9 is an addition circuit,
10, 12, 13 are AND circuits, 11 is a comparison circuit, 14 is an upper limit comparison circuit, 15 is a lower limit comparison circuit,
16 is a NAND circuit.

Claims (1)

[Scope of Claims] 1. A pattern is optically read and binarized, the type of the pattern is saved and memorized, and each inspection bit position where there is a signal representing a non-pattern part in the binarized pattern is read. one of the directions intersecting
determining the presence or absence of the center at the inspection bit position by measuring the length of non-pattern portions of a predetermined number of bit positions including the inspection bit position in two directions;
A pattern defect candidate signal is generated by measuring the length of a non-pattern part of a predetermined number of bit positions including the inspection bit position in a direction intersecting with the one direction, and the determination of the presence of the center occurs, and 1 above, including this at the determination prohibited bit position which is separated from the inspection bit position by a predetermined number of bit positions on both sides in the intersecting direction.
A defect inspection method that outputs the pattern defect candidate signal as a pattern defect signal only when there are no signals representing a predetermined number of pattern parts within a predetermined number of bit positions in one direction. 2. The defect inspection method according to claim 1, wherein the intersections are orthogonal. 3. A non-pattern part within a predetermined number of bit positions including the test bit position in one of the directions that intersect for each test bit position where a signal regarding a non-pattern part in the binarized pattern of the storage circuit is detected. first sensor circuits 31, 32 that output signals, respectively, for the non-pattern portion, and detecting the test bit position in the one direction in response to the signals for the non-pattern portion from the first sensor circuits 31, 32; a center determination circuit 20 that outputs the center of a non-pattern portion in a direction intersecting the one direction for each inspection bit position, and a signal for a non-pattern portion within a predetermined number of bit positions including the inspection bit position in a direction intersecting the one direction; second sensor circuits 33, 3 that output each of
4; a pattern defect candidate signal generation circuit 22 that generates a pattern defect candidate signal in response to signals regarding non-pattern portions from the second sensor circuits 33 and 34; said both sides outputting each of the signals for a pattern portion within a predetermined number of bit positions in said one direction, including the determination inhibited bit position which is separated by a predetermined number of bit positions on both sides from the inspection bit position; a pattern portion determination circuit 24 responsive to the outputs of the third sensor circuits 41 and 42, and a pattern portion determination circuit 24 responsive to the outputs of the center determination circuit 20 and the pattern portion determination circuit 24. A defect inspection apparatus characterized by controlling whether or not a pattern defect candidate signal from the pattern defect candidate signal generation circuit 22 is output as a pattern defect signal. 4. The defect inspection device according to claim 3, wherein the intersections are orthogonal.