JPS58202673A - Solid-state image pickup element - Google Patents

Solid-state image pickup element

Info

Publication number
JPS58202673A
JPS58202673A JP57084779A JP8477982A JPS58202673A JP S58202673 A JPS58202673 A JP S58202673A JP 57084779 A JP57084779 A JP 57084779A JP 8477982 A JP8477982 A JP 8477982A JP S58202673 A JPS58202673 A JP S58202673A
Authority
JP
Japan
Prior art keywords
film
electrode
substrate
transparent electrode
junction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57084779A
Other languages
Japanese (ja)
Inventor
Norio Koike
小池 紀雄
Taiji Shimomoto
下元 泰治
Toshihisa Tsukada
俊久 塚田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP57084779A priority Critical patent/JPS58202673A/en
Publication of JPS58202673A publication Critical patent/JPS58202673A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/148Charge coupled imagers
    • H01L27/14806Structural or functional details thereof
    • H01L27/14812Special geometry or disposition of pixel-elements, address lines or gate-electrodes
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70SSIS architectures; Circuits associated therewith
    • H04N25/76Addressed sensors, e.g. MOS or CMOS sensors

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)

Abstract

PURPOSE:To prevent the breakdown of a photoelectric converting film, by contacting a metallic electrode provided to an image pickup element which extracts a transparent electrode to the outside with a junction type diode of a different type from an element substrate and them utilizing the breakdown of said junction to shunt the high voltage applied to the electrode toward the substrate. CONSTITUTION:An oxide film 9 for insulation is formed on a semiconductor substrate 1 of the 1st conduction type, and a diffusion layer 16 is formed in the stages to form a source 3 and a drain 4 of an MOS switch 2. Electrodes 17, 6 and 14 are formed on the film 9, and at the same time a photoelectric converting film 7 is vapor deposited at the region of the switch 2 by a sputtering or glow discharge method. In addition, a transparent electrode 8 for application of target voltage is formed to the electrode 14 formed on the film 7 and the layer 16 to drive the film 7 by a sputtering or glow discharge method. In this case, the high voltage generated within a sputtering device is shunted toward the substrate 1 via the electrode 14 and the layer 16 by means of the junction different from the substrate 1 and formed to the lower layer of the electrode 14. Thus the breakdown is avoided for the film 7.

Description

【発明の詳細な説明】 (1)  発明の利用分野 本発明は半導体基板上に走査回路および光電変換膜を集
積化した固体撮像素子に関するものである。
DETAILED DESCRIPTION OF THE INVENTION (1) Field of Application of the Invention The present invention relates to a solid-state image sensor in which a scanning circuit and a photoelectric conversion film are integrated on a semiconductor substrate.

(2)従来技術 固体撮像素子を構成する有力な担手としてCCD(Ch
arge Coupled 、Devices )およ
びMOS型(MOSスイッチのソース接合を光ダイオー
ドとして利用する素子)の2種類が考えられてきた。
(2) Prior art CCD (Ch
Two types have been considered: a MOS type (a device that uses the source junction of a MOS switch as a photodiode) and a MOS type (a device that uses the source junction of a MOS switch as a photodiode).

これらの素子はいずれも集積度の高いMOSプロセス技
術を用いて製作できるという利点を有している。しかし
乍ら、感光部が電極の下(CODの場合)または走査ス
イッチおよび信号出力線と同一平面上(MOS型の場合
)にあるため、電極やスイッチ部によシ光の入射がさま
たげられる領域が多く、すなわち光損失が大きいという
欠点がある。さらに、感光部と走査部が前述のように同
一平面上あるため絵素の占有面積が大きくなる、すなわ
ち絵素の集積度を上げることが出来なくて解像度を上げ
ることができないという問題点を有している。
All of these devices have the advantage that they can be manufactured using highly integrated MOS process technology. However, since the photosensitive section is located below the electrode (in the case of COD) or on the same plane as the scanning switch and signal output line (in the case of MOS type), there is an area where the incidence of light is blocked by the electrode or switch section. The disadvantage is that there is a large amount of light loss, that is, there is a large optical loss. Furthermore, since the photosensitive section and the scanning section are on the same plane as mentioned above, the area occupied by the picture elements becomes large.In other words, there is a problem in that the density of the picture elements cannot be increased and the resolution cannot be increased. are doing.

これら問題点(光感度、解像度)を解決する構造として
、考案者らは走査部の上に感光用の光電変換膜を設ける
二階建構造の固体撮像素子を出願した(特願昭49−7
6372.特出願昭49年7月5日)。この二階建固体
撮像素子をMO8型素子で構成した場合を例にとり、素
子構造の概略を第1図に示す(CCD型で構成される場
合もあり、この場合はMO8電界効果トランジスタをC
ODで置き換えればよい)。1は第1導伝型の半導体基
板、2は走査回路(図示すず)あるいは走査回路の出力
によって開閉するスイッチを構成するMO8電界効果ト
ランジスタであり、ソース3゜ドレイン4.ゲート5か
ら成る6は1絵素の寸法を決める電極でここではソース
に接続されている。
As a structure to solve these problems (photosensitivity, resolution), the inventors applied for a two-story solid-state image sensor in which a photosensitive photoelectric conversion film is provided above the scanning section (Japanese Patent Application No. 49-7
6372. (Patent application filed July 5, 1972). Taking as an example the case where this two-story solid-state image sensor is constructed with MO8 type elements, the outline of the element structure is shown in Figure 1.
(You can replace it with OD). 1 is a semiconductor substrate of a first conductivity type; 2 is an MO8 field effect transistor constituting a scanning circuit (not shown) or a switch that is opened and closed by the output of the scanning circuit; Reference numeral 6 consisting of the gate 5 is an electrode that determines the dimensions of one picture element, and is connected to the source here.

7は感光材料となる光電変換膜、また8は光電変換膜を
駆動するターゲット電圧印加用の透明電極である。また
、9は絶縁用の酸化膜である。この図から分るように、
半導体基板1と走査回路およびスイッチ2を集積化した
走査IC基板と7および8から成る光電変換部とが二階
建構造になっている。したがって、面積利用η;高く絵
素当りの寸法10が小さくなる、すなわち解像度が高い
7 is a photoelectric conversion film serving as a photosensitive material, and 8 is a transparent electrode for applying a target voltage to drive the photoelectric conversion film. Further, 9 is an oxide film for insulation. As you can see from this figure,
A semiconductor substrate 1, a scanning IC substrate on which a scanning circuit and a switch 2 are integrated, and a photoelectric conversion section 7 and 8 have a two-story structure. Therefore, the area utilization η is high and the dimension 10 per picture element is small, that is, the resolution is high.

光電変換部が入射光11に対して上部にあるため光損失
がなく、光感度が高い。さらに、光電変換膜を選択する
ことにより所望の分光感度を得ることができる等、従来
の固体撮像素子に較べて極めて優れた性能を期待するこ
とができるものである。
Since the photoelectric conversion section is located above the incident light 11, there is no light loss and the light sensitivity is high. Furthermore, by selecting a photoelectric conversion film, a desired spectral sensitivity can be obtained, and extremely superior performance can be expected compared to conventional solid-state imaging devices.

しかし乍ら、本素子の開発を進める過程で透明電極(例
えば、金属の薄膜、5no2膜、■TO膜)を形成する
際、既に積層した光電変換部(例えば5e−As−’I
’e膜、CdTe膜、PbO,、CdS。
However, in the process of developing this device, when forming transparent electrodes (e.g., metal thin film, 5NO2 film, ■TO film), it was necessary to
'e film, CdTe film, PbO,, CdS.

Se B A S 2など)が破壊し、点状の欠陥(モ
ニタ上では白点となって現われ、画質を低下させる)が
発生するという極めてやつ介な問題を抱えていることが
判明した。この破壊の原因はスパッタ装置等の装置内で
高電圧が発生し、光電変換膜が耐圧以上の電圧にさらさ
れるためであることが判明した。
It has been found that the camera has an extremely troublesome problem in that the film (such as SeBAS 2) is destroyed and point-like defects (which appear as white spots on the monitor and degrade the image quality) occur. It has been found that the cause of this destruction is that high voltage is generated within a device such as a sputtering device, and the photoelectric conversion film is exposed to a voltage higher than the withstand voltage.

(3)本発明の目的 本発明の目的は透明電極を積層する際に下層に□1・て
1 ある光電変換膜が破壊されるのを防止する固体撮像素子
を提供することである。
(3) Purpose of the Present Invention The purpose of the present invention is to provide a solid-state imaging device that prevents the underlying photoelectric conversion film from being destroyed when transparent electrodes are laminated.

(4)発明の詳細な説明 本発明は上記目的を達成するため、具体的には透明電極
を外部に取出すために撮像素子内に設ける金属電極に素
子基板とは異なる型の不純物層(接合型ダイオード)を
接触せしめ、本接合のブレークダウンを利用して透明電
極に加わる高電圧を素子基板側に逃がすようにしたもの
である。
(4) Detailed Description of the Invention In order to achieve the above object, the present invention specifically provides an impurity layer of a type different from that of the element substrate (a bonding type The high voltage applied to the transparent electrode is released to the element substrate side by using the breakdown of this junction.

(5)実施例 以下、本発明を実施例を参照して詳細に説明する。第2
図は本発明の固体撮像素子の全体的な構造を示す図であ
る。7は光導電性膜(例えば、S e −A s −T
 e 、 Cd’pe、水素化非晶質シリコンなど)、
8は透明電極(SnOl、I’L”0膜などkまた1〜
6は第1図の説明の通りである。12は絵素電極が二次
元状に配列された光電変換領域、13は走査回路が集積
された領域を示している。
(5) Examples Hereinafter, the present invention will be explained in detail with reference to Examples. Second
The figure is a diagram showing the overall structure of the solid-state imaging device of the present invention. 7 is a photoconductive film (for example, S e -A s -T
e, Cd'pe, hydrogenated amorphous silicon, etc.),
8 is a transparent electrode (SnOl, I'L"0 film, etc.)
6 is as explained in FIG. Reference numeral 12 indicates a photoelectric conversion area in which picture element electrodes are arranged in a two-dimensional manner, and reference numeral 13 indicates an area in which scanning circuits are integrated.

14は素子チップの周辺に設けられたターゲット電圧を
印加する電極(例えばAt、Moなど)であり、領域1
5の部分で透明電極8とオーミックな接触をしている。
14 is an electrode (for example, At, Mo, etc.) provided around the element chip for applying a target voltage;
It is in ohmic contact with the transparent electrode 8 at the portion 5.

16は電極14とオーミック接触した基板1(例えばP
型)と異なる不純物原子からなる拡散層16(例えばN
型)である。また、17はチップ周辺に設けられる複数
個のポンディングパッド電極(電極14と同じ材料でよ
い)の1つを示しておシ、18は本チップを収納するパ
ッケージのピン端子とパッド電極を結ぶボンディングワ
イヤを示している。
16 is a substrate 1 (for example, P) that is in ohmic contact with the electrode 14.
diffusion layer 16 made of impurity atoms different from the type (for example, N
type). In addition, 17 indicates one of the plurality of bonding pad electrodes (which may be made of the same material as the electrode 14) provided around the chip, and 18 connects the pad electrode to the pin terminal of the package that houses the chip. Bonding wires are shown.

先ず、本素子の走査用IC基板が通常のMOS・LSI
技術により製作され、電極17,6゜14の形成まで完
了する。ここで、拡散層16はMO8スイッチ2のソー
スおよびドレインの形成と同一の工程で作られる。続い
て、光導電性膜がスパッタあるいはグロー放電により蒸
着される(重膜の加工は通常のホトエツチング技術ある
いはマスク蒸着法によって行われる)。最後に、透明電
極8がスパッタ法あるいはグロー放電法によシ蒸着され
る。本電極膜の蒸着の際、前の工程で製作された光導電
性膜にはスパッタ装置内に発生する高電圧に蒸着期間中
さらされる。発生電圧は電極膜製作のためのスパッタバ
イアス条件にもよるが50Vから数百■に及ぶ。光導電
性膜の強度は材料にもよるが膜厚1μm当シ50〜10
0■であシ、数μmの膜厚に設定される場合が多く、現
行の光電変換膜は光電変換領域のほぼ全域で破壊する。
First, the scanning IC board of this device is a normal MOS/LSI.
The electrodes 17, 6° 14 are formed using the same technique. Here, the diffusion layer 16 is formed in the same process as the source and drain of the MO8 switch 2. Subsequently, a photoconductive film is deposited by sputtering or glow discharge (the processing of the heavy film is carried out by conventional photoetching techniques or by mask evaporation). Finally, a transparent electrode 8 is deposited by sputtering or glow discharge. During the deposition of this electrode film, the photoconductive film produced in the previous step is exposed to a high voltage generated within the sputtering apparatus during the deposition period. The generated voltage ranges from 50 V to several hundred volts, depending on the sputter bias conditions for producing the electrode film. The strength of the photoconductive film is 50 to 10 per 1 μm of film thickness, although it depends on the material.
In most cases, the film thickness is set to several μm, and the current photoelectric conversion film is destroyed in almost the entire photoelectric conversion region.

きらに、光電変換膜の感度向上のため膜厚は将来薄膜化
する方向に進み、破壊の度合は増増大きくなる。しかし
乍ら、本発明の構造においては、電極14の下層に拡散
層16によるnp接合(−!たけpn接合)が設けられ
ているため高電圧は積層状態にある透明電極膜を介して
電極14、拡散層16、基板1へと逃がされる。ここで
基板へ逃がす役割を受持つのは高電圧によってブレーク
ダウンする接合(すなわちダイオード)である。
Furthermore, as the sensitivity of photoelectric conversion films increases, the film thickness will become thinner in the future, and the degree of destruction will increase and increase. However, in the structure of the present invention, since the np junction (-!take pn junction) is provided by the diffusion layer 16 in the lower layer of the electrode 14, the high voltage is applied to the electrode 14 through the laminated transparent electrode film. , the diffusion layer 16, and the substrate 1. Here, a junction (that is, a diode) that breaks down due to high voltage is responsible for discharging the energy to the substrate.

接合の耐圧は基板1の不純1吻濃度にも依存するが、一
般のIC基板として使用される5×10′4〜lXl0
”個/釧8の濃度では20〜40Vであシ、この結果、
光電変換膜に加わる電圧は高々20〜40Vにおさえる
ことができる。また、ブレーク′11 ダウンを起した際に流れる接合ダイオードに電流は無視
できる程僅かであるため接合のブレークダウンは瞬時的
なものであり、電圧の印加から開放されれば全く問題な
く正常な接合に立直り、撮像動作時に印加するターゲッ
ト電圧(一般に5〜10■)に十分耐えることができる
The breakdown voltage of the junction depends on the impurity concentration of the substrate 1, but it is 5×10′4 to 1×10 used as a general IC substrate.
``At the concentration of 8 pieces per piece, it is 20 to 40 V, and as a result,
The voltage applied to the photoelectric conversion film can be suppressed to 20 to 40V at most. In addition, the breakdown of the junction is instantaneous because the current that flows through the junction diode when a breakdown occurs is so small that it can be ignored, and once the voltage is removed, there is no problem and the junction is normal. It can fully withstand the target voltage (generally 5 to 10 μm) applied during the imaging operation.

第3図は不発明の固体撮像素子の平面構成を示す図であ
る。同図(a)は第2図に示した走査用IC基板にMO
8型基板を用いた場合の構成を示す図である。19は撮
像素子チップ、20は水平走査回路、13′は垂直走査
回路、7′は光電変換膜が形成される領域、8′は透明
電極が形成される領域、17’−1は例えば走査回路等
を駆動するための電源を印加するためのポンディングパ
ッド、18’−1,18’ −2はボンディング用ワイ
ヤである。ここで、透明電極8′は一部(本例ではチッ
プ下方の一部分)で拡散層16′を備えたターゲット電
極14′と接触している。また、17’−2は電極14
′の一部に設けたターゲット電圧印加用のポンディング
パッドである。
FIG. 3 is a diagram showing the planar configuration of the solid-state imaging device according to the invention. The same figure (a) shows MO on the scanning IC board shown in Figure 2.
It is a figure which shows the structure when an 8-type board|substrate is used. 19 is an image sensor chip, 20 is a horizontal scanning circuit, 13' is a vertical scanning circuit, 7' is a region where a photoelectric conversion film is formed, 8' is a region where a transparent electrode is formed, and 17'-1 is, for example, a scanning circuit. Bonding pads 18'-1 and 18'-2 are bonding wires for applying power to drive the components and the like. Here, a portion of the transparent electrode 8' (in this example, a portion below the chip) is in contact with a target electrode 14' provided with a diffusion layer 16'. In addition, 17'-2 is the electrode 14
This is a bonding pad for applying a target voltage provided in a part of .

同図(1)は走査用等・C基よKCCD型基板を用にた
場合の構成を示す図である。21は水平CCDシフトレ
ジスタ、7′は光電変換膜領域であシこの下層に垂直C
ODシフトレジスタのアレーが配置されている。8′は
透明電極領域であシ、一部(本例ではチップ上方の一部
)で拡散層16′を備えた電極14′と接触している。
FIG. 1 (1) is a diagram showing the configuration when a KCCD type substrate is used for scanning or the like. 21 is a horizontal CCD shift register, and 7' is a photoelectric conversion film area.
An array of OD shift registers is arranged. Reference numeral 8' denotes a transparent electrode region, which is in contact with an electrode 14' provided with a diffusion layer 16' at a portion (in this example, a portion above the chip).

また、17’−1は例えば垂直CODシフトレジスタを
駆動するための電源を印加するためのポンディングパッ
ド、17’−2は電極14′の一部に設けたターゲット
電圧印加用のポンディングパッドである。一方、同図(
C)は同図(b)と同じ<CCD型基板を用いた例であ
るが、透明電極8′につながら電極14″を光電変換領
域を取シ囲むように形成し、さらに、電極14“の下層
につながる拡散層16〃を複数個のブロックに分割して
設けるようにした場合を示している。スパッタ装置内で
発生する高電界により拡散接合16“がブレークダウン
を起す場合、本拡散層に流れる電流は前述のように極め
て僅かであるから、本拡散層は同図(a)、 (b)の
ように面積的に大きな値を取る必要はなく、本例のよう
に分割してその面積を電流容量に応じた必要な値まで減
らしてもよい。
Further, 17'-1 is a bonding pad for applying power for driving a vertical COD shift register, and 17'-2 is a bonding pad for applying a target voltage provided on a part of the electrode 14'. be. On the other hand, the same figure (
C) is an example using the same <CCD type substrate as in FIG. A case is shown in which the diffusion layer 16 connected to the lower layer is divided into a plurality of blocks. When the diffusion junction 16'' breaks down due to the high electric field generated in the sputtering equipment, the current flowing through the main diffusion layer is extremely small as described above, so the main diffusion layer is It is not necessary to take a large value in terms of area as in this example, and the area may be reduced to a necessary value according to the current capacity by dividing it as in this example.

(9) 透明電極形成時に光電変換膜に加わる電圧は電極14の
構造を第4図の様にすることによシさらに低下させるこ
とができる。16は第2図に記載した電極14の下に設
けた基板1と異なる型の不純物層、22は不純物1−1
6のさらに下層に設けた基板と同型かつ基板よシ濃度の
高い不純物層である。本構造においては不純物層16と
22で作る接合のブレークダウン電圧が低くなり、この
ブレークダウン電圧の値は不純物層22の不純物濃度の
設定により1v〜数十■の範囲で所望の値を得ることが
できる。ただし、本ブレークダウン電圧は撮像時に加え
るターゲット電圧よりは大きく設定しておく必要がある
。この様に不純物層16のブレークダウン電圧を第2図
の場合より下げることにより光電変換膜の破壊防止効果
はさらに高めることができる。
(9) The voltage applied to the photoelectric conversion film during the formation of the transparent electrode can be further reduced by making the structure of the electrode 14 as shown in FIG. 16 is an impurity layer of a different type from the substrate 1 provided under the electrode 14 shown in FIG. 2, and 22 is an impurity layer 1-1.
This is an impurity layer of the same type as the substrate provided further below the layer 6 and of a higher concentration than the substrate. In this structure, the breakdown voltage of the junction formed by the impurity layers 16 and 22 is low, and the value of this breakdown voltage can be set to a desired value in the range of 1 V to several tens of volts by setting the impurity concentration of the impurity layer 22. I can do it. However, this breakdown voltage needs to be set higher than the target voltage applied during imaging. In this way, by lowering the breakdown voltage of the impurity layer 16 than in the case of FIG. 2, the effect of preventing destruction of the photoelectric conversion film can be further enhanced.

畢発明者らは本発明の素子構造によって、光電変換膜の
破壊をほぼ100%防止できることを確認し、製作時に
おける欠陥の発生防止は元よシ、初期には観測されなか
った欠陥(前述の白点)の(10) 発生も減少し画質および信頼性も著しく向上することを
確認した。したがって、本発明は実用的に極めて高い価
値を有するものである。
The inventors have confirmed that the device structure of the present invention can prevent almost 100% destruction of the photoelectric conversion film. It was confirmed that the occurrence of white spots (10) was also reduced and the image quality and reliability were significantly improved. Therefore, the present invention has extremely high practical value.

なお、前述の実施例では走査用IC基板の構成素子とし
てMOS)ランジスタを使用したが、前述のようにCC
Dで構成した場合、さらにCIDにおいても、本発明の
構造は全く同じ形で適用できることは自明である。
In the above embodiment, a MOS (MOS) transistor was used as a component of the scanning IC board, but as mentioned above, a CC
It is obvious that the structure of the present invention can be applied in exactly the same manner to the case of D and also to CID.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の固体撮像素子の絵素構造を示す図、第2
図は本発明の固体撮像素子の全体の構造を示す図、第3
図は本発明の固体撮像素子の平面構成を示す図、第4図
は本発明の固体撮像素子の第2図とは別の素子構造を示
す図である。 代理へ弁理士 薄田利幸 (11) 第 3 回 芽 3 図 (C) VJ4図
Figure 1 is a diagram showing the pixel structure of a conventional solid-state image sensor;
The figure shows the overall structure of the solid-state image sensing device of the present invention.
The figure shows the planar configuration of the solid-state image sensing device of the present invention, and FIG. 4 is a diagram showing a device structure different from that shown in FIG. 2 of the solid-state image sensing device of the present invention. Patent attorney Toshiyuki Usuda (11) 3rd Bud 3 Diagram (C) VJ4 diagram

Claims (1)

【特許請求の範囲】[Claims] 1、二次元状に配列した複数個の絵素電極、該絵電極に
つながるスイッチ、順次これらのスイッチを介して取出
した光電荷を転送する走査素子を集積化した走査用半導
体集積回路基板の上部に積層され該光電荷を発生する光
導電性膜および透明電極膜を有する固体撮像素子におい
て、該光導電性膜の駆動電界として該透明電極に所定の
ターゲット電圧を加えるために該透明電極の周辺領域の
一部分でオーミック接触する該ターゲット電圧入力用の
金属層が該走査用半導体基板上に形成した異なる型の不
純物層に接続されたことを特徴とする固体撮像素子。
1. The upper part of a scanning semiconductor integrated circuit board that integrates a plurality of picture element electrodes arranged in a two-dimensional manner, switches connected to the picture electrodes, and scanning elements that transfer photocharges sequentially taken out via these switches. In a solid-state imaging device having a photoconductive film and a transparent electrode film that are laminated to generate the photocharge, the area around the transparent electrode is used to apply a predetermined target voltage to the transparent electrode as a driving electric field for the photoconductive film. 1. A solid-state imaging device, wherein the target voltage input metal layer that makes ohmic contact in a part of the region is connected to a different type of impurity layer formed on the scanning semiconductor substrate.
JP57084779A 1982-05-21 1982-05-21 Solid-state image pickup element Pending JPS58202673A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57084779A JPS58202673A (en) 1982-05-21 1982-05-21 Solid-state image pickup element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57084779A JPS58202673A (en) 1982-05-21 1982-05-21 Solid-state image pickup element

Publications (1)

Publication Number Publication Date
JPS58202673A true JPS58202673A (en) 1983-11-25

Family

ID=13840169

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57084779A Pending JPS58202673A (en) 1982-05-21 1982-05-21 Solid-state image pickup element

Country Status (1)

Country Link
JP (1) JPS58202673A (en)

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