JP3360928B2 - Method for manufacturing solid-state imaging device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a solid-state image pickup device.

[0002]

2. Description of the Related Art Nowadays, with the remarkable progress of semiconductor LSI technology and thin film technology, it has become possible to realize a multifunctional three-dimensional integrated circuit, and a semiconductor integrated circuit which performs a parallel image processing function. A hybrid semiconductor device including a high-sensitivity photoelectric conversion film laminated on the upper surface is attracting attention.

An example of this is a solid-state image sensor in which an amorphous selenium (a-Se) film having an avalanche multiplication function is laminated on a pixel electrode. Here, when the photoconductive film made of an amorphous selenium semiconductor is operated in the avalanche amplification mode, the film is 1 × 10 ⁶ to 1 × 1.
A high electric field of 0 ⁷ V / cm is applied. For example, it is necessary to apply a high voltage of about 240 V to a 2 μm selenium film.

At this time, if there are large steps or irregularities on the surface of the selenium film, an electric field considerably larger than the average electric field is locally applied, and a local breakdown occurs. Therefore, when this solid-state image pickup device is used for an image pickup tube, white flaws or spots are conspicuous on the screen and the image quality is deteriorated.

Further, in the case of a solid-state image pickup device using crystalline silicon as a substrate, not only the problem of image quality but also a high voltage of several hundreds of volts is applied between the source and the drain of the MOS switch or between the source and the substrate through the breakdown generating portion. Is applied to the entire substrate through the signal line or the crystalline silicon substrate, and there is a risk of destroying elements on the entire substrate.

In order to solve such a problem, a method for manufacturing a solid-state image pickup device while flattening a photoconductive film is as follows.
The "Super flattening technology of the surface of a solid-state image sensor" of C-545 of the 993 spring meeting of the Institute of Electronics, Information and Communication Engineers has been proposed. FIG. 15 is a diagram showing a pixel cross-sectional structure of a solid-state image sensor used in this technique. As shown in FIG. 15, this solid-state imaging device is one in which an amorphous selenium photoconductive film 50 is laminated on an AMI (Amplified MOS Imager).

In this method, SiO _{2 is formed on} the top of the AMI.
The insulating film 52 made of and the contact electrode 53 made of an alloy having a hardness close to that of the insulating film 52 are laminated, and the upper surfaces thereof are polished and flattened by using a diamond polishing machine, and then the pixels are formed on the polished surface. This is a method of forming an electrode 51 to form a solid-state image sensor. According to this method, the maximum unevenness of the deposition surface of the pixel electrode 51 can be reduced to about 500 ohm strong, and accordingly, the unevenness of the selenium photoconductive film 50 can be reduced.

In addition to this, Japanese Patent Publication No. 62-44695.
There is a method described in. In this method, a switching MOS, a transistor, and the like are formed on a semiconductor substrate, and then a Se—As layer of about 3 μm containing 5% by weight of arsenic and 50% by weight or more of selenium is formed on this substrate. Then, in a nitrogen gas atmosphere, the substrate is heat-treated for 5 minutes at a temperature not lower than the glass transition point (110 ° C.) of the Se-As amorphous film to soften the Se-As amorphous film and flatten it. Turn into.

[0009]

In the case of flattening by polishing, the alloy forming the contact electrode has almost the same hardness as the hardness of the insulating film and is suitable for the semiconductor processing process and contact with other metals. Must. However, it is extremely difficult to produce an alloy that satisfies all these requirements. Further, the photoconductive film is apt to be partially thinned on the gaps between the pixel electrodes, so that a step difference of at least about several hundred angstroms occurs in the photoconductive film.

Further, although the steps on the gaps between the pixel electrodes can be flattened by the flattening by the heat treatment, the unevenness corresponding to the edges of the pixel electrodes is only slightly smoothed, and the flattening is performed. Was insufficient. Further, all the process temperatures after the heat treatment are limited to 100 ° C. or lower, and it is impossible to form an avalanche photoelectric conversion film or a superlattice-structured light receiving or emitting film in which the deposition or processing temperature exceeds 100 ° C. There were also points.

The present invention has been made to solve the above-mentioned problems, and a solid-state image pickup device having a semiconductor layer such as an extremely flat photoconductive film can be produced, and an avalanche photoelectric conversion film or a superlattice structure can be formed. It is an object of the present invention to provide a method for manufacturing a solid-state imaging device having a wide range of applications, such as forming a light-receiving film as a semiconductor layer that generates carriers.

[0012]

In order to solve the above-mentioned problems, the manufacturing method of the first type of the present invention comprises (a) a first step of forming a plurality of pixel electrodes on a substrate, (B)
The second step of stacking a switch array layer including a plurality of switches connected to each pixel electrode, (c) the third step of removing the substrate, and (d) the pixel electrode exposed by the third step. A fourth step of forming a carrier generation film including a semiconductor layer that generates carriers upon incidence of light or electrons on a surface including a surface, and (e) a fifth step of laminating a conductive layer on the carrier generation film. It has and.

Here, the second step may be a step of first laminating an insulating layer and then laminating a switch array layer by forming a plurality of switches on the insulating layer.

Further, the third step can be a step of removing the substrate by etching, polishing or the like.

Next, the second type of manufacturing method of the present invention comprises (a) a first step of forming an intermediate layer on a substrate;
(B) a second step of forming a plurality of pixel electrodes on the intermediate layer, and (c) a third step of laminating a switch array layer including a plurality of switches connected to each pixel electrode on the pixel electrode. And (d) a fourth step of utilizing the intermediate layer as an etching stop layer for protecting the pixel electrode from etching and removing the substrate by etching, and (e) exposing the surface of the intermediate layer exposed by etching to light or The method includes a fifth step of forming a carrier generation film including a semiconductor layer that generates carriers by the incidence of electrons, and (f) a sixth step of laminating a conductive layer on the carrier generation film.

Here, the first step is preferably a step of forming the intermediate layer by using a material that prevents injection of carriers into the semiconductor layer.

In the first and second types of manufacturing method, crystalline silicon, glass, metal or the like can be used as the substrate material.

In the first and second types of manufacturing method, after stacking the switch array layers, prior to removing the substrate, element protection is performed to protect the pixel electrodes and the switch array layers while exposing the surface of the substrate. It is preferable to further include a step of accommodating and fixing this substrate in a container.

[0019]

In the manufacturing method of the first type of the present invention, the surface formed on the substrate and exposed by removing the substrate becomes a flat surface according to the flatness of the substrate surface. In this manufacturing method, since the carrier generation film is formed on this flat surface, an extremely flat semiconductor layer can be formed.

Further, since the semiconductor layer can be produced by a generally known method, the kind of semiconductor material used is not limited. Therefore, this manufacturing method has a wide application range.

In the second type of manufacturing method of the present invention, the surface of the intermediate layer formed on the substrate and exposed by etching the substrate is a flat surface according to the flatness of the substrate surface. In this manufacturing method, since the carrier generation film is formed on the flat surface formed by the surface of the intermediate layer, an extremely flat semiconductor layer can be formed.

Since the semiconductor layer can be produced by a generally known method like the first type, the kind of semiconductor material used is not limited. Therefore, this manufacturing method has a wide application range.

Further, when the intermediate layer is formed by using a material that blocks the injection of carriers into the semiconductor layer, the intermediate layer functions as an etching stop layer and also as a carrier injection blocking layer for suppressing dark current. Will be equipped with. Therefore, when manufacturing a solid-state imaging device including a carrier injection blocking layer, the step of independently forming only the carrier injection blocking layer can be omitted, and the manufacturing process can be simplified.

In the first and second types of manufacturing methods, after the switch array layer is laminated on the substrate, the substrate is housed in the element protection container and then the substrate is etched. It is possible to easily prevent damage to the electrodes and the switch array layer.

[0025]

Embodiments of the present invention will now be described in detail with reference to the accompanying drawings. In the description of the drawings, the same elements will be denoted by the same reference symbols, without redundant description.

FIG. 1 is a sectional view showing the first step.
As shown in FIG. 1, first, a mirror-polished crystalline silicon substrate 1 (n-type 110 surface) is prepared, washed, and then p ⁺ -type a-SiC: H is formed by using a general plasma CVD apparatus.
An etch stop layer 2 of about 100 Å is deposited. The stop layer 2 has a function of preventing the etching from proceeding to the pixel electrode when the substrate 1 is etched using a silicon etchant containing nitric acid in a later step.

The maximum unevenness on the surface of the silicon substrate 1 can be set to about 5 to 10 angstroms by mirror polishing.

Further, the stop layer 2 made of p ⁺ -type a-SiC: H also functions as an electron injection blocking layer for blocking electron injection from the pixel electrode into the semiconductor layer in the completed solid-state image pickup device. If the layer is too thin, the above two effects disappear, and if it is too thick, a part of the voltage is applied to the p ⁺ -type a-SiC: H layer and the bias voltage of the photoconductive film is lowered by that amount, and the avalanche multiplication is performed at a predetermined voltage. Does not happen. Therefore, the thickness of the stop layer 2 is preferably about 50 to 200 angstroms.

Then, using a sputtering apparatus, a Cr layer having a thickness of about 400 Å is deposited on the upper surface of the stop layer 2, and then a groove is formed in the Cr layer by dry etching.
A plurality of pixel electrodes 3 each having a substantially square planar shape are formed (FIG. 1). The aperture ratio can be set to about 95% by adjusting the distance between the pixel electrodes.

Next, FIGS. 2 to 5 are sectional views showing a second step of laminating the switch array layer on the pixel electrode 3.
In this second step, first, as shown in FIG.
An interlayer insulating film 4 made of a-SiN is deposited to a thickness of about 0.7 μm using a D device. As a result, the insulating a-SiN comes to be present in the gap between the pixel electrodes.

Subsequently, known inverse stagger type TFTs (thin film transistors) are laminated by a general manufacturing method. The manufacturing method will be briefly described below.

First, as shown in FIG. 2, an Al film having a thickness of about 0.3 μm is deposited on the interlayer insulating film 4 by a sputtering apparatus to form a gate electrode 5. Then, after anodizing the gate electrode 5, using a plasma CVD apparatus,
About 0.3 μm gate insulating film 6 covering the gate electrode 5
Are deposited on the upper surface of the interlayer insulating film 4.

The material of the gate insulating film 6 is a-SiN, which is the same as the material of the interlayer insulating film 4 in order to form a source contact hole later (FIG. 2).

Next, as shown in FIG. 3, a channel layer 7 made of a-Si: H is deposited on the gate insulating film 6 by using a plasma CVD device, and a channel layer 7 is continuously formed on the upper surface of the channel layer 7 by a.
A passivation film 8 of about 0.1 μm made of —SiN is deposited.

Next, the passivation film 8 and the channel layer 7
Is partially etched, and then a contact layer 9 made of n ⁺ type a-Si: H is deposited by a plasma CVD apparatus (FIG. 3).

Next, as shown in FIG. 4, a contact hole with the pixel electrode 3 penetrating the gate insulating film 6 and the interlayer insulating film 4 is formed by dry etching, and then the thickness is reduced to about 0 using a sputtering device. The Al layer of 0.7 μm is formed as shown in FIG.
Are deposited on the upper surfaces of the gate insulating film 6 and the contact layer 9 (FIG. 4).

Subsequently, as shown in FIG. 5, the Al layer and the contact layer 9 on the passivation film 8 are removed by dry etching. As a result, the Al layer is divided,
The drain 10 and the source 11 are formed to form an inverted stagger type TFT. Next, a passivation film 12 of about 2 μm made of polyimide is formed on the TFT to protect the TFT (FIG. 5).

By the above second step, the pixel electrode 3 of FIG.
A TFT switch array layer 21 composed of an inverted stagger type TFT connected to the interlayer insulating film 4 and each pixel electrode 3 is laminated on the above, and a TFT array element 20 is manufactured.

Next, for convenience of manufacture, after connecting the necessary electronic circuit to the TFT array element 20, the TFT array element 20 is fixed in a package in which a plurality of pins for connecting to an external device are attached. The third step will be described below. 6 to 9 are sectional views showing this third step.

FIG. 6 is a first cross-sectional view showing the third step, showing the TFT array element 20 housed in a ceramic package 30 having a substantially cylindrical outer shape. As shown in the figure, on the etching stop layer 2, an IC chip (not shown) for vertical scanning for performing gate control around the switch array layer 21, a preamplifier array for signal amplification, and a multiplexer IC for horizontal scanning. The signal reading chip 22 composed of a chip is fixed, and a gate line and a signal line drawn out from the switch array layer 21 are bonded to each.

Next, the substrate 1 is placed on a disk-shaped temporary fixing lid 31 made of ceramic, and then the temporary fixing lid 31 is placed.
The package 30 is attached to and fixed. Then, the output line of the signal reading chip 22 is bonded to the connecting pin 33. Similarly, an IC chip including a vertical scanning circuit is also connected to a connection pin (not shown) (FIG. 6). Of course, the vertical scanning circuit and the signal reading circuit may be formed on the substrate 1.

Next, as shown in FIG. 7, the ultraviolet curable resin 35 is used.
Is filled in the package 30, and then the glass alternative substrate 32 is attached to the package 30 to encapsulate the ultraviolet curable resin 35 (FIG. 7).

Subsequently, as shown in FIG. 8, ultraviolet rays are irradiated from above the substitute substrate 32 attached to the package 30 toward the central region of the switch array element 20. As a result, the resin 35 is partially cured, so that the switch array element 20 is temporarily fixed (FIG. 8).

Then, as shown in FIG. 9, after removing the temporary fixing lid 31, the entire surface of the alternative substrate 32 is irradiated with ultraviolet rays,
All the resin 35 is cured to completely fix the switch array element 20 (FIG. 9).

In the above work, the ultraviolet curable resin 3
It is also possible to use a thermosetting resin instead of 5.
At this time, the resin is hardened by heating to fix the switch array element 20.

Next, a fourth manufacturing process for removing the substrate 1 by etching will be described. 10 and 11 are
It is sectional drawing which shows this 4th process. First, as shown in FIG. 10, a resist material is applied to a portion of the package 30 or the like which is not removed by etching to protect it, and then the central portion of the silicon substrate 1 is completely removed by etching with a silicon etchant containing nitric acid. At this time, the progress of etching is stopped by the etching stop layer 2, and the corrosion of the pixel electrode 3 by nitric acid is prevented (FIG. 10).

Since the etchant is generally selected in relation to the pixel electrode material and the substrate material, the etching stop layer 2 can be omitted by selecting an etchant that does not damage the electrodes. However, in this embodiment, the etching stop layer 2 has a function as an electron injection blocking layer to simplify the manufacturing process, and therefore the etching stop layer 2 is formed.

Next, as shown in FIG. 11, after the surface of the etching stopper layer 2 exposed by etching is washed, an a-Se (amorphous selenium) film 23 is deposited on the surface while using a mask by using a vapor deposition apparatus. Deposit. here,
The a-Se film 23 is a semiconductor layer that generates carriers upon incidence of light or electrons, and also has an avalanche multiplication function.

As described above, in this embodiment, the maximum unevenness is 5
By forming the photoconductive film 23 on the etching stopper layer 2 exposed by etching after being formed on the substrate 1 having a thickness of about 10 Å, the maximum unevenness of the photoconductive film 23 is reduced to 5
It can be suppressed to about 20 Å. Therefore, the solid-state imaging device including the photoconductive film 23 performs uniform operation over the entire area of the device. For example, when a bias voltage is applied, the occurrence of local breakdown due to the unevenness of the photoconductive film is suppressed, and the local deterioration of image quality can be reduced.

Next, using a sputtering apparatus, this aS
A transparent electrode 24 made of ITO (Sn-doped indium) is deposited on the surface of the e film 23 by about 0.1 μm. As described above, the switch array layer 21 is laminated on one surface of the etching stopper layer 2 and the a-Se film 23 is formed on the other surface.
Then, the solid-state imaging device of this embodiment in which the transparent electrode 24 is laminated is manufactured.

Then, the transparent electrode 24 is connected to the electrode of the connecting pin 34 attached to the package 30 by wire bonding. The connecting pin 34 is a-Se.
The film 23 is connected to an external power source that applies a bias voltage. As described above, the solid-state imaging device including this embodiment is completed (FIG. 11).

According to the above embodiment, the etching stop layer 2
Since it also functions as an electron injection blocking layer, it is not necessary to newly form the electron injection blocking layer, and therefore, the solid-state imaging device including the electron injection blocking layer can be efficiently manufactured.

Next, FIG. 12 is a partial plan view showing the arrangement of the pixel electrode 3 of the solid-state image pickup device manufactured as described above and the TFT switch connected to this pixel electrode 3. Note that the insulating film, the channel layer, the contact layer, and the passivation film included in the switch array layer 21 are not shown in this figure.

As shown in FIG. 12, in this embodiment, the pixel electrode 3 and the source 11 of the TFT switch are in contact with each other through the source contact hole. Here, for example, when a drive pulse voltage from the vertical operating circuit via the gate electrode 5 second phi _j rows are applied, each column through the channel layer in which carriers (not shown) accumulated in each pixel electrode 3 of phi _j row Move to the drain 10 of. The carriers that have moved to the drain 10 of each column are sequentially taken out by the horizontal operation circuit provided in the signal read chip 22. At this time, the carrier current is amplified by the preamplifier connected to the drain 10 of each column. As described above, the operation as the solid-state image sensor is achieved.

In this embodiment, the TFT switch corresponding to each pixel electrode is output in order to minimize the noise induced by the driving pulse of each TFT to the pixel electrode 3 through the interlayer insulating film (not shown). Are provided on the pixel electrodes of the adjacent row to be read out first. In addition, the TFT corresponding to each pixel
Since the switches are separated from each other by etching, even if a breakdown occurs at one pixel,
There is no risk of spreading to the next switch.

Next, the second embodiment will be described.
FIG. 13 is a cross-sectional view of the solid-state image sensor manufactured in this example. This is an electron implantation multiplication type solid-state imaging device.

The method of manufacturing the solid-state image sensor of FIG. 13 differs from that of the first embodiment in the following points. That is, in the second embodiment, Sb ₂ S ₃ is used as the material of the etching stopper layer 2. Further, in the present embodiment, the hole injection blocking layer 25 for blocking the hole injection from the outside into the a-Se film 23 is formed on the a-Se film 23 having the avalanche multiplication effect by CeO.
₂ is deposited by a vapor deposition device and then Al
The electrode 26 is deposited.

The etching stop layer 2 made of Sb ₂ S _{3 functions} as an electron injection blocking layer for preventing injection of electrons from the pixel electrode 3 as in the first embodiment. Therefore, the solid-state imaging device manufactured in this example includes an electron injection blocking layer (also serving as an etching stop layer) and a hole injection blocking layer 25 as carrier injection blocking layers.

FIG. 14 shows a two-dimensional element 4 including the solid-state image sensor of FIG. 13 as an example of using the solid-state image sensor of FIG.
8 is a view showing an X-ray II tube 40 using No. This II
Briefly explaining the operation of the tube 40, the X-rays that have entered the II tube 40 first pass through the entrance window 41 and enter the fluorescent screen 42. As a result, visible light is emitted from the phosphor screen 42 and is incident on the photocathode 43. Photoelectric surface 43 due to the incidence of visible light
When photoelectrons are emitted from the photoelectron beam, the photoelectron beam is accelerated and focused by the electric field applied by the focus electrodes 44 to 46, and reaches the two-dimensional element 48 disposed near the anode 47.

When photoelectrons enter the Al electrode 26 of the solid-state image pickup device of FIG. 14 in this manner, photoelectrons are emitted from the Al electrode 2
6 and the hole injection blocking layer 25 to pass through the a-Se film 2
It is incident on 3. As a result, electron implantation multiplication based on the avalanche multiplication action occurs in the a-Se film 23.
Image enhancement of the incident X-ray image is possible.

The present invention is not limited to the above embodiment, but various modifications can be made. For example, the channel layer of the TFT of the above embodiment may be formed using an amorphous silicon material other than a-Si: H, or may be formed using polysilicon or cadmium selenide.

Instead of the TFT of the above embodiment, a PN or PIN thin film diode switch made of an amorphous silicon material may be formed. Further, instead of the a-Se film of the above embodiment, a thin film made of an amorphous silicon-based or amorphous selenium-based semiconductor material having a photocurrent multiplying function, an a-SiC (amorphous silicon carbide) -based or a-SiN ( A light receiving film having a superlattice structure made of an amorphous silicon nitride-based semiconductor material may be formed.

[0063]

As described above in detail, in the first-type manufacturing method of the present invention, the carrier generation film including the semiconductor layer is laminated on the surface including the surface of the pixel electrode exposed by removing the substrate. Therefore, a solid-state image sensor having an extremely flat semiconductor layer can be manufactured.

Further, since the kind of semiconductor material used is not limited, the avalanche photoelectric conversion film or the light receiving film having a superlattice structure can be formed as a semiconductor layer, and the manufacturing method of the present invention has a wide range of application.

In the second type of manufacturing method of the present invention, the carrier generation film is laminated on the surface of the intermediate layer which is formed on the substrate and is exposed by the etching of the substrate using the intermediate layer as the etching stop layer. A very flat semiconductor layer can be formed.

Further, as in the case of the first type, since the kind of the semiconductor material used is not limited, an avalanche photoelectric conversion film or a light receiving film having a superlattice structure can be formed as a semiconductor layer. The manufacturing method has a wide range of applications.

Furthermore, when the intermediate layer is formed using a material that blocks carrier injection into the semiconductor layer, the step of forming the carrier injection blocking layer can be omitted and the manufacturing process can be simplified. The labor required for can be reduced. Therefore, it is possible to improve productivity and reduce costs.

In the first and second types of manufacturing method, after the switch array layer is laminated on the substrate, the substrate is housed in the element protection container and then the substrate is etched. It is possible to easily prevent damage to the electrodes and the switch array layer. This makes it possible to increase productivity and improve yield.

Further, since the solid-state image pickup device manufactured according to the present invention is provided with the extremely flat semiconductor layer as described above, local breakdown is unlikely to occur, and therefore, the solid-state image pickup device can be used in an image pickup device such as a pickup tube. When used, deterioration of image quality can be suppressed.

[Brief description of drawings]

FIG. 1 is a sectional view showing a first step of a first embodiment.

FIG. 2 is a first sectional view showing a second step of the first embodiment.

FIG. 3 is a second sectional view showing a second step.

FIG. 4 is a third sectional view showing a second step.

FIG. 5 is a fourth cross-sectional view showing the second step.

FIG. 6 is a first sectional view showing a third step of the first embodiment.

FIG. 7 is a second sectional view showing a third step.

FIG. 8 is a third cross-sectional view showing the third step.

FIG. 9 is a fourth cross-sectional view showing the third step.

FIG. 10 is a first sectional view showing a fourth step of the first embodiment.

FIG. 11 is a second sectional view showing a fourth step.

FIG. 12 is a partial plan view of the solid-state imaging device manufactured in the first example.

FIG. 13 is a cross-sectional view of a solid-state image sensor manufactured in a second example.

14 is a diagram showing an X-ray II tube using the solid-state image sensor of FIG.

FIG. 15 is a diagram for explaining a conventional method.

[Explanation of symbols]

1 ... Silicon substrate, 2 ... Etching stop layer, 3 ... Cr pixel electrode, 4 ... Interlayer insulating film, 5 ... Gate electrode, 6 ... Gate insulating film, 7 ... Channel layer, 8 ... Passivation film, 9 ...
Contact layer, 10 ... Drain, 11 ... Source, 12 ...
Passivation film, 20 ... switch array element, 21 ...
Switch array layer, 22 ... Signal reading chip, 23 ...
a-Se film, 24 ... ITO transparent electrode.

─────────────────────────────────────────────────── ─── Continuation of front page (56) Reference JP-A-1-291460 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 27/146

Claims (5)

(57) [Claims] 1. A first step of forming a plurality of pixel electrodes on a substrate, a second step of stacking a switch array layer including a plurality of switches connected to each pixel electrode, and removing the substrate. And a fourth step of forming a carrier generation film including a semiconductor layer that generates carriers by the incidence of light or electrons on the surface including the surface of the pixel electrode exposed by the third step. And a fifth step of stacking a conductive layer on the carrier generating film, the method for manufacturing a solid-state image sensor. 2. The second step is a step of first laminating an insulating layer and then laminating the switch array layer by forming the plurality of switches on the insulating layer. The method for manufacturing a solid-state image sensor according to claim 1. 3. A first step of forming an intermediate layer on a substrate, a second step of forming a plurality of pixel electrodes on the intermediate layer, and connecting each pixel electrode on the pixel electrode. A third step of stacking a switch array layer including a plurality of switches, a fourth step of using the intermediate layer as an etching stop layer for protecting the pixel electrode from etching, and removing the substrate by etching, On the surface of the intermediate layer exposed by the etching,
Fabrication of a solid-state imaging device comprising: a fifth step of forming a carrier generation film including a semiconductor layer that generates carriers by incidence of light or electrons; and a sixth step of laminating a conductive layer on the carrier generation film. Method. 4. The solid-state imaging device according to claim 3, wherein the first step is a step of forming the intermediate layer by using a material which prevents injection of carriers into the semiconductor layer. Of manufacturing. 5. After stacking the switch array layer, prior to removing the substrate, the substrate is housed in an element protection container that protects the pixel electrodes and the switch array layer while exposing the surface of the substrate. The method for manufacturing a solid-state image sensor according to claim 1, further comprising a step of fixing the solid-state image sensor.