JPH05167056A - Lamination-type solid-state image sensing device - Google Patents

Lamination-type solid-state image sensing device

Info

Publication number
JPH05167056A
JPH05167056A JP3352868A JP35286891A JPH05167056A JP H05167056 A JPH05167056 A JP H05167056A JP 3352868 A JP3352868 A JP 3352868A JP 35286891 A JP35286891 A JP 35286891A JP H05167056 A JPH05167056 A JP H05167056A
Authority
JP
Japan
Prior art keywords
solid
film
pixel electrode
state image
photoconductive film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP3352868A
Other languages
Japanese (ja)
Inventor
Shuichi Araki
秀一 荒木
Yuji Inoue
祐治 井上
Yukio Matsuzawa
幸雄 松沢
Junichi Yamazaki
順一 山崎
Hirotaka Maruyama
裕孝 丸山
Kazunori Miyagawa
和典 宮川
Fumihiko Ando
文彦 安藤
Kazuhisa Taketoshi
和久 竹歳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Olympus Corp
Japan Broadcasting Corp
Original Assignee
Nippon Hoso Kyokai NHK
Japan Broadcasting Corp
Olympus Optical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Hoso Kyokai NHK, Japan Broadcasting Corp, Olympus Optical Co Ltd filed Critical Nippon Hoso Kyokai NHK
Priority to JP3352868A priority Critical patent/JPH05167056A/en
Publication of JPH05167056A publication Critical patent/JPH05167056A/en
Withdrawn legal-status Critical Current

Links

Abstract

PURPOSE:To achieve the low after image, the low sticking and the high sensitivity of a lamination-type solid-state image sensing device by a method wherein a voltage which can cause an avalanche multiplication operation or the like can be applied to a photoconductive film in the lamination-type solid-state image sensing device wherein the photoconductive film has been laminated on a solid-state image sensing element chip. CONSTITUTION:A charge storage part 2 and a charge transfer part 3 are formed on a semiconductor substrate 1; a pixel electrode 13 which has been connected electrically to the charge storage part 2 via a second metal electrode 11 is formed; an electric-field relaxation layer 14 which is composed of a high- resistance body is formed in a region around the end part of the pixel electrode 13. A photoconductive film 15 is laminated on the pixel electrode 13 and the electric-field relaxation layer 14; a transparent electrode 16 is formed on it. Thereby, a lamination-type solid-state image sensing device is constituted.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は、固体撮像素子チップ
上に光導電膜を積層して構成した積層型固体撮像装置に
関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a laminated solid-state image pickup device having a photoconductive film laminated on a solid-state image pickup element chip.

【0002】[0002]

【従来の技術】一般にCCD(Charge Coupled Devic
e)等を用いた固体撮像装置においては、光電変換を行
うフォトダイオード部と信号電荷の読み出しを行う回路
部とが、シリコン基板の同一平面上に配置されるため、
入射された光の利用率が悪く、高感度化に限界がある。
2. Description of the Related Art Generally, a CCD (Charge Coupled Devic
In the solid-state imaging device using e) or the like, since the photodiode unit that performs photoelectric conversion and the circuit unit that reads out the signal charges are arranged on the same plane of the silicon substrate,
The utilization rate of incident light is poor, and there is a limit to high sensitivity.

【0003】そのためフォトダイオード部を構成する各
フォトダイオードの上部に凸形状の微小レンズを設けて
画素毎に光を集める方法や、撮像管で使用されている光
導電膜を固体撮像素子上に積層する方法が提案されてい
る。特に光導電膜を積層する方法は、感光部が素子の最
上部に配置されるため、紫外線や青色光等の利用率も高
くでき、また積層膜材料を選択することによって分光感
度を自由に設計できる利点が得られるものである。
Therefore, a method of collecting light for each pixel by providing a convex minute lens on each photodiode constituting the photodiode section, or stacking a photoconductive film used in an image pickup tube on a solid-state image pickup element The method to do is proposed. In particular, in the method of stacking photoconductive films, since the photosensitive part is located at the top of the device, the utilization rate of ultraviolet rays, blue light, etc. can be increased, and the spectral sensitivity can be freely designed by selecting the laminated film material. The advantage that can be obtained is obtained.

【0004】かかる積層型固体撮像装置としては、既
に、例えば、CCDチップ上にa−Si:H(水素化アモ
ルファスシリコン)膜を積層したもの(テレビジョン学
会全国大会論文集,3−5,1983,pp45〜46),MOS
撮像素子上にSe−As−Te(サチコン)膜を積層したもの
(テレビジョン学会技術報告,ED480 ,1980,pp41〜
46),AMI(Amplified MOS Imager)撮像素子上にa
−Se膜を積層したもの(テレビジョン学会全国大会論文
集,2−15,1989,pp41〜42)等が学会等で報告されて
おり、光利用効率を100 %近くに向上できること、スミ
アや偽信号(疑似信号)を低減できること等の利点が確
かめられている。
An example of such a laminated solid-state image pickup device is one in which an a-Si: H (hydrogenated amorphous silicon) film is laminated on a CCD chip (Television Society National Conference Proceedings, 3-5, 1983). , Pp45-46), MOS
Laminated Se-As-Te (saticon) film on the image sensor (Technical Report of the Television Society of Japan, ED480, 1980, pp41-)
46), a on the AMI (Amplified MOS Imager) image sensor
-Se films laminated (Television Society National Conference Proceedings, 2-15, 1989, pp41-42) have been reported by academic societies, etc., and can improve light utilization efficiency to nearly 100%, smear and false It has been confirmed that the signal (pseudo signal) can be reduced.

【0005】しかし、撮像管においては、光導電膜を平
滑性に優れたガラス基板上に形成し、電子ビームによっ
て信号電荷を連続的に読み出すように構成されているの
に対し、積層型固体撮像装置においては、各画素毎に分
離した画素電極上に光導電膜を積層して構成しているた
め、下地の凹凸や不均一性に起因した暗電流の増加や、
白キズと呼ばれる画像欠陥が発生し易い問題がある。
However, in an image pickup tube, a photoconductive film is formed on a glass substrate having excellent smoothness and signal charges are continuously read out by an electron beam, whereas a stacked solid-state image pickup device is used. In the device, since the photoconductive film is laminated on the pixel electrode separated for each pixel, dark current increases due to unevenness and unevenness of the base,
There is a problem that image defects called white scratches are likely to occur.

【0006】このため、下地の平坦化に対しては、各画
素電極の間隙に絶縁体を埋め込む方法が、例えば特開平
1−295457号公報において、既に提案されてい
る。次に上記公報開示の固体撮像装置の一画素部の一部
省略した断面構造及び平面構造を図7の(A),(B)
に示す。図において、101 は画素電極、102 は画素電極
間の間隙に埋め込まれた画素分離層、103 は画素電極10
1 及び画素分離層102 上に形成された光導電膜、104 は
光導電膜103 上に設けられた透明電極、105 は配線用Al
電極、106 は半導体基板107 上に形成された信号電荷蓄
積部、108 は絶縁膜であり、画素電極間に埋め込まれた
画素分離層102 により下地の平坦化を計っている。
Therefore, for flattening the underlayer, a method of burying an insulator in the gap between the pixel electrodes has already been proposed, for example, in Japanese Patent Application Laid-Open No. 1-295457. Next, a cross-sectional structure and a planar structure of a pixel portion of the solid-state imaging device disclosed in the above publication are partially omitted, and FIGS.
Shown in. In the figure, 101 is a pixel electrode, 102 is a pixel separation layer embedded in a gap between the pixel electrodes, and 103 is a pixel electrode 10
1 and the photoconductive film formed on the pixel separation layer 102, 104 is a transparent electrode provided on the photoconductive film 103, and 105 is Al for wiring.
An electrode, 106 is a signal charge storage portion formed on the semiconductor substrate 107, and 108 is an insulating film, and the base is flattened by the pixel separation layer 102 embedded between the pixel electrodes.

【0007】[0007]

【発明が解決しようとする課題】ところで上記公報開示
の構成では、画素電極と画素電極間隙との段差は減少で
きるが、光導電膜に印加する電圧を徐々に高めていく
と、画素電極の中央部よりも先に周辺部で急激に暗電流
が増加するエッジ・ブレークダウン現象が生じる。これ
は光導電膜を挟んで形成されている透明電極及び画素電
極が完全に無限遠の平行平板ではなく、画素電極が島状
に分離して配列されていることや、蓄積信号電荷量が画
素電極毎に異なる等の不均一性に起因して、画素電極の
端部周辺領域上にある光導電膜の方が、画素電極中央部
の真上にある光導電膜よりも、膜内電界が強まる電界集
中が生じるためである。これにより、光導電膜に印加で
きる最大電圧が制限され、光導電性の残像や焼き付けが
十分に改善できないという問題点があった。
In the structure disclosed in the above publication, the step between the pixel electrode and the pixel electrode gap can be reduced, but when the voltage applied to the photoconductive film is gradually increased, the center of the pixel electrode is reduced. An edge breakdown phenomenon occurs in which the dark current sharply increases in the peripheral area before the area. This is because the transparent electrode and the pixel electrode formed by sandwiching the photoconductive film are not completely parallel plates at infinity, but the pixel electrodes are separated and arranged in an island shape, and the accumulated signal charge amount is Due to non-uniformity such as different for each electrode, the intra-film electric field is higher in the photoconductive film on the peripheral region of the edge of the pixel electrode than on the photoconductive film directly above the central part of the pixel electrode. This is because the intensifying electric field concentration occurs. As a result, the maximum voltage that can be applied to the photoconductive film is limited, and there is a problem that the photoconductive afterimage and printing cannot be sufficiently improved.

【0008】また、既に特開昭63−304551号公
報において、撮像管における光導電膜内でのアバランシ
ェ増倍動作について提案がなされているが、このアバラ
ンシェ増倍動作は通常の光導電膜の動作電圧よりも大幅
に高い印加電圧を必要とする。例えば、膜厚が2μmの
a−Se光導電膜の場合、通常の動作電圧が25V程度であ
るのに対して、アバランシェ増倍動作で10倍の増幅を行
わせる場合には、印加電圧は約240 Vを必要とする。
In Japanese Patent Laid-Open No. 63-304551, there has already been proposed an avalanche multiplication operation in a photoconductive film of an image pickup tube. This avalanche multiplication operation is a normal photoconductive film operation. It requires an applied voltage significantly higher than the voltage. For example, in the case of an a-Se photoconductive film having a film thickness of 2 μm, the normal operating voltage is about 25 V, whereas when amplification of 10 times is performed by the avalanche multiplication operation, the applied voltage is about It requires 240V.

【0009】前記特開平1−295457号公報開示の
平坦化を施した積層型固体撮像装置の場合、アバランシ
ェ増倍動作に必要な高い電界を光導電膜を印加していく
と、エッジブレークダウンが引き金となって、画像上に
白点キズが多数発生し、やがて透明電極と画素電極が電
気的に短絡して、最終的には撮像素子全体が破壊してし
まうという問題点もあった。
In the case of the flattened laminated solid-state image pickup device disclosed in Japanese Patent Laid-Open No. 1-295457, edge breakdown occurs when the photoconductive film is applied with a high electric field required for avalanche multiplication operation. As a trigger, many white spots are generated on the image, and eventually the transparent electrode and the pixel electrode are electrically short-circuited, and eventually the entire image sensor is destroyed.

【0010】本発明は、従来の積層型固体撮像装置にお
ける上記問題点を解消するためになされたもので、画素
電極周辺部で生じるエッジ・ブレークダウン現象を阻止
し、十分高い電圧を光導電膜に均等に印加できるように
した、低残像,低焼き付きで高感度の積層型固体撮像装
置を提供することを目的とする。
The present invention has been made in order to solve the above-mentioned problems in the conventional stacked type solid-state image pickup device, and prevents the edge breakdown phenomenon occurring in the peripheral portion of the pixel electrode and provides a sufficiently high voltage photoconductive film. It is an object of the present invention to provide a high-sensitivity stacked solid-state imaging device which has a low afterimage, low image sticking, and which can be uniformly applied to the solid-state imaging device.

【0011】[0011]

【課題を解決するための手段及び作用】上記問題点を解
決するため、本発明は、半導体基板上に信号電荷蓄積部
及び信号電荷読み出し部が複数個配列され、且つ最上部
に各信号電荷蓄積部に電気的に接続された画素電極が形
成された固体撮像素子チップと、該固体撮像素子チップ
上に積層された光導電膜とを備えた積層型固体撮像装置
において、前記画素電極の端部周辺領域を高抵抗体から
なる電界緩和層で覆い、該画素電極の端部周辺領域と前
記光導電膜との間に電界緩和層を介在させて構成するも
のである。
In order to solve the above problems, the present invention provides a plurality of signal charge accumulating portions and a plurality of signal charge reading portions arranged on a semiconductor substrate, and each signal charge accumulating portion at the uppermost portion. A solid-state imaging device chip in which a pixel electrode electrically connected to the solid-state imaging device chip is formed, and a photoconductive film laminated on the solid-state imaging device chip, wherein an end portion of the pixel electrode is provided. The peripheral region is covered with an electric field relaxation layer made of a high resistance material, and the electric field relaxation layer is interposed between the peripheral region of the end portion of the pixel electrode and the photoconductive film.

【0012】このように構成した積層型固体撮像装置に
おいては、画素電極の端部周辺領域上に電界緩和層が設
けられているため、画素電極の端部周辺領域における電
界集中が緩和され、光導電膜にアバランシェ増倍動作が
生じ得る高い電圧を印加しても、画素電極周辺領域での
局所的な電界の集中に基づく暗電流の増加が生じないた
め、画素電極全域で光導電膜の安定したアバランシェ増
倍が行えると同時に、光導電膜内での信号電荷の走行性
が高まるため、光導電性の残像や焼き付きが低減され
る。
In the laminated solid-state image pickup device having such a structure, since the electric field relaxation layer is provided on the peripheral area of the end portion of the pixel electrode, the electric field concentration in the peripheral area of the end portion of the pixel electrode is mitigated, and Even if a high voltage that can cause avalanche multiplication operation is applied to the conductive film, the dark current does not increase due to the local concentration of the electric field in the pixel electrode peripheral region, so that the photoconductive film is stable over the entire pixel electrode. The avalanche multiplication can be performed, and at the same time, the traveling property of the signal charge in the photoconductive film is enhanced, so that the afterimage and burn-in of the photoconductive property are reduced.

【0013】[0013]

【実施例】次に実施例について説明する。図1の(A)
は、本発明に係る積層型固体撮像装置の第1実施例の一
画素部の概略構造を示す断面図であり、図1の(B)は
その平面図である。この実施例は、信号読み出し部にM
OSを用いたもので、図において、1はp型半導体基
板、2,3は該半導体基板1上に形成されたMOSのn
+ 電荷蓄積部及び電荷転送部、4はp+ 画素分離領域、
5は該画素分離領域4上に形成されたフィールド絶縁膜
である。6はゲート絶縁膜、7はMOSのゲート電極、
8は第1絶縁膜、9は第1絶縁膜8に設けたコンタクト
ホールを介して電荷転送部3と電気的に導通された第1
金属電極、10は第2絶縁膜、11は第2絶縁膜10に設けら
れたコンタクトホールを介して電荷蓄積部2と電気的に
導通され画素毎に独立して設けられた第2金属電極であ
る。12は第3絶縁膜、13は第3絶縁膜上に形成され第2
金属電極11と電気的に導通された画素電極、14は該画素
電極13の端部周辺領域を覆うように設けられた断面がテ
ーパー面を有する台形状の高抵抗体からなる電界緩和
層、15は画素電極13及び電界緩和層14上に設けられた光
導電膜、16は該光導電膜15上に形成された透明電極であ
る。
EXAMPLES Next, examples will be described. Figure 1 (A)
FIG. 1 is a sectional view showing a schematic structure of a pixel portion of a first embodiment of a laminated solid-state imaging device according to the present invention, and FIG. 1 (B) is a plan view thereof. In this embodiment, the signal reading unit has M
In the figure, 1 is a p-type semiconductor substrate, and 2 and 3 are n-type MOSs formed on the semiconductor substrate 1.
+ Charge storage unit and charge transfer unit, 4 is a p + pixel separation region,
A field insulating film 5 is formed on the pixel isolation region 4. 6 is a gate insulating film, 7 is a MOS gate electrode,
Reference numeral 8 is a first insulating film, 9 is a first conductive film electrically connected to the charge transfer portion 3 through a contact hole formed in the first insulating film 8.
A metal electrode, 10 is a second insulating film, 11 is a second metal electrode which is electrically connected to the charge storage unit 2 through a contact hole provided in the second insulating film 10 and is provided independently for each pixel. is there. 12 is a third insulating film, and 13 is a second insulating film formed on the third insulating film.
A pixel electrode electrically connected to the metal electrode 11, 14 is an electric field relaxation layer formed of a trapezoidal high resistance body having a tapered surface in cross section, which is provided so as to cover the peripheral region of the end of the pixel electrode 13. Is a photoconductive film provided on the pixel electrode 13 and the electric field relaxation layer 14, and 16 is a transparent electrode formed on the photoconductive film 15.

【0014】次に、図1に示した第1実施例の積層型固
体撮像装置の製造工程を、図2に基づいて説明する。ま
ず図2の(A)に示すように、p型半導体1の表面層の
トランジスタ領域に相当する部分を除く領域にp+ 画素
分離領域4を備えたフィールド絶縁膜5を形成する。次
にゲート絶縁膜6を形成した後、多結晶シリコンあるい
はMo等よりなるMOSのゲート電極7を形成する。更に
イオン注入法によりMOSの電荷蓄積部2と電荷転送部
3を形成する。
Next, the manufacturing process of the laminated solid-state image pickup device of the first embodiment shown in FIG. 1 will be described with reference to FIG. First, as shown in FIG. 2A, a field insulating film 5 having ap + pixel isolation region 4 is formed in a region of the surface layer of the p-type semiconductor 1 excluding a portion corresponding to a transistor region. Next, after forming the gate insulating film 6, a MOS gate electrode 7 made of polycrystalline silicon or Mo is formed. Further, the charge storage portion 2 and the charge transfer portion 3 of the MOS are formed by the ion implantation method.

【0015】次いで図2の(B)に示すように、これら
の上に第1絶縁膜8を堆積した後に、第1絶縁膜8に設
けたコンタクトホールを介して電荷転送部3と電気的に
導通された第1金属電極9を形成する。更にこの上に第
2絶縁膜10を堆積した後に、該第2絶縁膜10に設けたコ
ンタクトホールを介して電荷蓄積部2と電気的に導通さ
れ画素毎に独立して第2金属電極11を形成する。この段
階では素子の表面には数μmの凹凸が生じている。そこ
で、次に形成される画素電極の表面形状を平坦にする目
的で、無機系又は有機系材料を用いたSOG(スピン・
オン・ガラス)法等により第3絶縁膜12を形成し、更に
第3絶縁膜12の表面を異方性又は等方性のドライ又はウ
ェットエッチングにより削って、第2金属電極11の一部
を露出させる。
Then, as shown in FIG. 2B, after the first insulating film 8 is deposited on these, the charge transfer portion 3 is electrically connected to the charge transfer portion 3 through a contact hole formed in the first insulating film 8. The conductive first metal electrode 9 is formed. Further, after the second insulating film 10 is deposited on this, the second metal electrode 11 is electrically connected to the charge storage unit 2 through the contact hole provided in the second insulating film 10 to form the second metal electrode 11 independently for each pixel. Form. At this stage, unevenness of several μm occurs on the surface of the device. Therefore, in order to flatten the surface shape of the pixel electrode formed next, SOG (spin
The third insulating film 12 is formed by an on-glass method or the like, and the surface of the third insulating film 12 is removed by anisotropic or isotropic dry or wet etching to partially remove the second metal electrode 11. Expose.

【0016】次に図2の(C)に示すように、これらの
上に金属等よりなる画素電極13を形成する。この際、画
素電極13は平坦に形成される。次いで、この画素電極13
上に再び無機系又は有機系材料を用いてSOG法等によ
り第4絶縁膜17を、およそ0.5μmの膜厚に形成する。
更に画素電極周辺部及び画素電極間の間隙部の上部に相
当する部分を覆うようにレジストパターン18を形成す
る。続いて図2の(D)に示すように、ウェット又はド
ライ等の等方性エッチング法によりエッチングすること
によって、断面がテーパー面をもつ台形状の電界緩和層
14を形成し、レジストパターン18を除去することによ
り、図2の(E)に示すように、画素電極13の端部周辺
領域に電界緩和層14を備えたMOS型固体撮像素子チッ
プが得られる。
Next, as shown in FIG. 2C, a pixel electrode 13 made of metal or the like is formed on these. At this time, the pixel electrode 13 is formed flat. Then, this pixel electrode 13
The fourth insulating film 17 is again formed on the above by an SOG method or the like using an inorganic or organic material to a film thickness of about 0.5 μm.
Further, a resist pattern 18 is formed so as to cover the peripheral portions of the pixel electrodes and the portions corresponding to the upper portions of the gaps between the pixel electrodes. Subsequently, as shown in FIG. 2D, a trapezoidal electric field relaxation layer having a tapered surface is formed by etching by an isotropic etching method such as wet or dry.
By forming 14 and removing the resist pattern 18, as shown in FIG. 2E, a MOS type solid-state imaging device chip having an electric field relaxation layer 14 in the peripheral region of the edge of the pixel electrode 13 is obtained. ..

【0017】次に、このチップ上に図2では図示しない
が、光導電膜15を積層する(図1参照)。光導電膜15と
しては、電子注入阻止強化層として膜厚1000ÅのAs2 Se
3 を、また光電変換層として膜厚2μmのa−Seを順次
クラスターイオンビーム蒸着法により積層し、次いで正
孔注入阻止強化層として膜厚160 ÅのCeO2 を高真空蒸
着法により積層して形成する。最後に、透明電極16とし
て膜厚500 ÅのITOをスパッタ法により成膜して、積
層型固体撮像装置を完成する。
Next, although not shown in FIG. 2, a photoconductive film 15 is laminated on this chip (see FIG. 1). As the photoconductive film 15, an As 2 Se film having a film thickness of 1000 Å was used as an electron injection blocking enhancement layer.
3 and a-Se having a film thickness of 2 μm as a photoelectric conversion layer are sequentially laminated by a cluster ion beam vapor deposition method, and then CeO 2 having a film thickness of 160 Å is laminated as a hole injection blocking enhancement layer by a high vacuum vapor deposition method. Form. Finally, an ITO film having a film thickness of 500 Å is formed as the transparent electrode 16 by a sputtering method to complete the stacked solid-state imaging device.

【0018】図3は、上記実施例に基づいて製作した積
層型固体撮像装置に対して透明電極に印加する正の電圧
を変化させた場合の装置の出力信号電流(室温で青色光
照射)及び暗電流の変化を示す図であり、また比較のた
め従来の平坦化法による積層型固体撮像装置の特性も合
わせて示している。図3において、曲線a,bは本発明
に係る固体撮像装置の信号電流及び暗電流であり、曲線
a′,b′は従来装置の信号電流及び暗電流である。
FIG. 3 shows the output signal current (blue light irradiation at room temperature) of the device when the positive voltage applied to the transparent electrode is changed with respect to the stacked type solid-state image pickup device manufactured according to the above embodiment. FIG. 3 is a diagram showing changes in dark current, and also shows characteristics of a stacked solid-state imaging device by a conventional flattening method for comparison. In FIG. 3, curves a and b are the signal current and dark current of the solid-state imaging device according to the present invention, and curves a ′ and b ′ are the signal current and dark current of the conventional device.

【0019】図3からわかるように、本発明に係る積層
型固体撮像装置の場合、印加電圧を高めても暗電流は従
来装置よりも極めて低く抑えられている。そのため、a
−Seからなる光導電膜内でアバランシェ増倍が生じる24
0 Vという高い電圧を印加することができ、その時の信
号電流は50V印加時の約10倍の高い値が得られる。また
本発明による積層型固体撮像装置においては、白キズが
少なく、焼き付きや残像も認められなかった。
As can be seen from FIG. 3, in the case of the laminated solid-state image pickup device according to the present invention, the dark current is suppressed to be extremely lower than that of the conventional device even if the applied voltage is increased. Therefore, a
Avalanche multiplication occurs in the photoconductive film made of −Se 24
A high voltage of 0 V can be applied, and the signal current at that time is about 10 times higher than that when 50 V is applied. Further, in the laminated solid-state image pickup device according to the present invention, there were few white scratches, and no image sticking or afterimage was observed.

【0020】図4の(A),(B)は、本発明の第2実
施例を示す一部省略した断面図及び平面図である。この
実施例は、画素電極間の間隙部に沿って凹部が形成され
たテーパー面を有する電界緩和層24を設けたものであ
る。このような構成の電界緩和層24を形成するには、図
2に示した第1実施例の製造工程における図2の(C)
に示した工程において、平坦な画素電極13を形成した
後、高抵抗材料であるSiO2 被膜をCVD法あるいはス
パッタ法により膜厚0.1μmに形成する。次に画素電極
周辺部のみを覆うレジストパターンを形成して、他の部
分を異方性又は等方性のエッチング法により画素電極13
が露出するまでエッチングして、上記形状の電界緩和層
24を形成する。その後、第1実施例と同様に、光導電膜
15と透明電極16を積層して、積層型固体撮像装置を得
る。
4A and 4B are a partially omitted sectional view and a plan view showing a second embodiment of the present invention. In this embodiment, the electric field relaxation layer 24 having a tapered surface in which a concave portion is formed along the gap between the pixel electrodes is provided. In order to form the electric field relaxation layer 24 having such a structure, FIG. 2C in the manufacturing process of the first embodiment shown in FIG.
In the step shown in (1), after the flat pixel electrode 13 is formed, a SiO 2 film which is a high resistance material is formed to a film thickness of 0.1 μm by the CVD method or the sputtering method. Next, a resist pattern is formed so as to cover only the peripheral portion of the pixel electrode, and the other portion is etched by the anisotropic or isotropic etching method.
Etching to expose the electric field relaxation layer having the above shape.
Forming 24. Then, as in the first embodiment, the photoconductive film is formed.
15 and the transparent electrode 16 are laminated to obtain a laminated solid-state imaging device.

【0021】この実施例による積層型固体撮像装置で
は、第1実施例と同様に、光導電膜に高い電圧を印加で
き、高感度で且つ低暗電流,低残像,低焼き付きが得ら
れる。
In the laminated solid-state image pickup device according to this embodiment, as in the first embodiment, a high voltage can be applied to the photoconductive film, and high sensitivity and low dark current, low afterimage, and low image sticking can be obtained.

【0022】図5及び図6は、第3及び第4実施例を示
す一部省略した概略断面図である。図5に示した第3実
施例は、断面を3角形状とした電界緩和層34を用いたも
ので、このような形状の電界緩和層34を形成するには、
図2に示した第1実施例の製造工程における図2の
(C)に示した第4絶縁膜17のウェットエッチングをオ
ーバーぎみにすることにより形成する。図6に示した第
4実施例は、高抵抗膜を画素電極13の端部のみに形成し
電界緩和層44としたものであり、このような電界緩和層
44を形成した場合には、光導電膜15は基板1の回転と斜
め方向からの蒸着法の併用により積層形成する。
FIG. 5 and FIG. 6 are schematic cross sectional views showing the third and fourth embodiments with a part thereof omitted. The third embodiment shown in FIG. 5 uses the electric field relaxation layer 34 having a triangular cross section. To form the electric field relaxation layer 34 having such a shape,
It is formed by over-wetting the fourth insulating film 17 shown in FIG. 2C in the manufacturing process of the first embodiment shown in FIG. In the fourth embodiment shown in FIG. 6, a high resistance film is formed only on the end portion of the pixel electrode 13 to form an electric field relaxation layer 44.
When 44 is formed, the photoconductive film 15 is formed by laminating the substrate 1 and the oblique evaporation method.

【0023】電界緩和層の構成材料としては、上記実施
例ではSiO2を用いたものを示したが、この他に、TiO
2 ,CeO2 ,GeO2 ,Al2 3 ,Ta2 5 ,WO3 ,Mo
3 ,MgO,PbO,BeO,V2 5 ,NiO,Co2 3
SiC,Si3 4 ,As2 Se3 等を主成分とし、比抵抗が光
導電膜と同等もしくはそれ以上の高抵抗材料であれば同
様に用いることができ、電界緩和層の膜厚としては、50
Å以上で1μm以下が望ましく、特に断面がテーパー形
状をもつものが最適である。
As the constituent material of the electric field relaxation layer, the one using SiO 2 is shown in the above-mentioned embodiment.
2 , CeO 2 , GeO 2 , Al 2 O 3 , Ta 2 O 5 , WO 3 , Mo
O 3 , MgO, PbO, BeO, V 2 O 5 , NiO, Co 2 O 3 ,
A high resistance material containing SiC, Si 3 N 4 , As 2 Se 3 or the like as a main component and having a specific resistance equal to or higher than that of the photoconductive film can be used in the same manner. , 50
Å or more and 1 μm or less is desirable, and one having a tapered cross section is particularly suitable.

【0024】また上記実施例では、固体撮像素子チップ
としてMOS型撮像素子チップを用い、積層する光導電
膜としてa−Se膜を用いたものを示したが、固体撮像素
子チップとしてはCCDやAMI素子等を用いたものに
も本発明を適用することができ、また光導電膜として
も、a−Se膜以外にa−Si:H,a−Si:B:H,a−
SiC:H等も用いることができる。更に本発明は2次元
の固体撮像装置のみならず、1次元の固体撮像装置にも
適用でき、同様の作用効果が得られる。
In the above embodiment, the MOS type image pickup element chip is used as the solid-state image pickup element chip and the a-Se film is used as the photoconductive film to be laminated. However, the solid-state image pickup element chip is a CCD or AMI. The present invention can be applied to a device using an element and the like, and as a photoconductive film, a-Si: H, a-Si: B: H, a- other than the a-Se film.
SiC: H or the like can also be used. Furthermore, the present invention can be applied not only to the two-dimensional solid-state image pickup device but also to the one-dimensional solid-state image pickup device, and the same effects can be obtained.

【0025】[0025]

【発明の効果】以上実施例に基づいて説明したように、
本発明によれば、画素電極の端部周辺領域上に電界緩和
層が設けられているので、光導電膜に高い電圧を印加し
ても画素電極周辺領域での局所的な電界の集中に基づく
暗電流の増加が生じないため、画素電極全域で光導電膜
の安定したアバランシェ増倍が行え、高感度で残像や焼
き付きの低減した積層型固体撮像装置が得られる。
As described above on the basis of the embodiments,
According to the present invention, since the electric field relaxation layer is provided on the peripheral region of the end portion of the pixel electrode, even if a high voltage is applied to the photoconductive film, it is possible to prevent the electric field from being locally concentrated in the peripheral region of the pixel electrode. Since a dark current does not increase, stable avalanche multiplication of the photoconductive film can be performed over the entire area of the pixel electrode, and a stacked solid-state imaging device with high sensitivity and reduced afterimage and image sticking can be obtained.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明に係る積層型固体撮像装置の第1実施例
を示す概略断面図及び平面図である。
FIG. 1 is a schematic sectional view and a plan view showing a first embodiment of a laminated solid-state imaging device according to the present invention.

【図2】第1実施例の製造工程を示す図である。FIG. 2 is a diagram showing a manufacturing process of the first embodiment.

【図3】第1実施例及び従来例の印加電圧に対する信号
電流及び暗電流特性を示す図である。
FIG. 3 is a diagram showing signal current and dark current characteristics with respect to applied voltage in the first example and the conventional example.

【図4】第2実施例を示す概略断面図及び平面図であ
る。
FIG. 4 is a schematic cross-sectional view and a plan view showing a second embodiment.

【図5】第3実施例を示す概略断面図である。FIG. 5 is a schematic sectional view showing a third embodiment.

【図6】第4実施例を示す概略断面図である。FIG. 6 is a schematic sectional view showing a fourth embodiment.

【図7】従来の平坦化した積層型固体撮像装置の構成例
を示す概略断面図及び平面図である。
7A and 7B are a schematic cross-sectional view and a plan view showing a configuration example of a conventional flattened stacked solid-state imaging device.

【符号の説明】[Explanation of symbols]

1 p型半導体基板 2 電荷蓄積部 3 電荷転送部 4 画素分離領域 5 フィールド絶縁膜 6 ゲート絶縁膜 7 ゲート電極 8 第1絶縁膜 9 第1金属電極 10 第2絶縁膜 11 第2金属電極 12 第3絶縁膜 13 画素電極 14 電界緩和層 15 光導電膜 16 透明電極 1 p-type semiconductor substrate 2 charge storage part 3 charge transfer part 4 pixel separation region 5 field insulating film 6 gate insulating film 7 gate electrode 8 first insulating film 9 first metal electrode 10 second insulating film 11 second metal electrode 12 second 3 insulating film 13 pixel electrode 14 electric field relaxation layer 15 photoconductive film 16 transparent electrode

───────────────────────────────────────────────────── フロントページの続き (72)発明者 松沢 幸雄 東京都渋谷区幡ケ谷2丁目43番2号 オリ ンパス光学工業株式会社内 (72)発明者 山崎 順一 東京都世田谷区砧1丁目10番11号 日本放 送協会放送技術研究所内 (72)発明者 丸山 裕孝 東京都世田谷区砧1丁目10番11号 日本放 送協会放送技術研究所内 (72)発明者 宮川 和典 東京都世田谷区砧1丁目10番11号 日本放 送協会放送技術研究所内 (72)発明者 安藤 文彦 東京都世田谷区砧1丁目10番11号 日本放 送協会放送技術研究所内 (72)発明者 竹歳 和久 東京都世田谷区砧1丁目10番11号 日本放 送協会放送技術研究所内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yukio Matsuzawa 2-43-2 Hatagaya, Shibuya-ku, Tokyo Olympus Optical Co., Ltd. (72) Inventor Junichi Yamazaki 1-10-11 Kinuta, Setagaya-ku, Tokyo Broadcasting Technology Institute of Japan Broadcasting Corporation (72) Hirotaka Maruyama 1-10-11 Kinuta, Setagaya-ku, Tokyo Inside Broadcasting Technology Laboratory of Japan Broadcasting Corporation (72) Inventor Kazunori Miyagawa 1-10 Kinuta, Setagaya-ku, Tokyo No. 11 Inside the Broadcasting Technology Research Institute of the Japan Broadcasting Corporation (72) Inventor Fumihiko Ando 1-10-11 Kinuta, Setagaya-ku, Tokyo Inside the Broadcasting Technology Research Institute of the Japan Broadcasting Corporation (72) Inventor Kazuhisa Taketoshi Kinuta 1 Setagaya-ku, Tokyo 10-11, Japan Broadcasting Corporation Broadcasting Technology Research Institute

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板上に信号電荷蓄積部及び信号
電荷読み出し部が複数個配列され、且つ最上部に各信号
電荷蓄積部に電気的に接続された画素電極が形成された
固体撮像素子チップと、該固体撮像素子チップ上に積層
された光導電膜とを備えた積層型固体撮像装置におい
て、前記画素電極の端部周辺領域を高抵抗体からなる電
界緩和層で覆い、該画素電極の端部周辺領域と前記光導
電膜との間に電界緩和層を介在させたことを特徴とする
積層型固体撮像装置。
1. A solid-state image sensor chip having a plurality of signal charge accumulating portions and a plurality of signal charge reading portions arranged on a semiconductor substrate, and a pixel electrode electrically connected to each signal charge accumulating portion formed on the uppermost portion. And a photoconductive film laminated on the solid-state imaging element chip, in a laminated solid-state imaging device, a peripheral region of an end portion of the pixel electrode is covered with an electric field relaxation layer formed of a high resistance, A stacked solid-state imaging device, characterized in that an electric field relaxation layer is interposed between an edge peripheral region and the photoconductive film.
【請求項2】 前記電界緩和層の比抵抗は、光導電膜と
同等もしくはそれ以上で、その膜厚は50Å以上1μm以
下であることを特徴とする請求項1記載の積層型固体撮
像装置。
2. The stacked solid-state image pickup device according to claim 1, wherein the electric field relaxation layer has a specific resistance equal to or higher than that of the photoconductive film, and a film thickness of 50 Å or more and 1 μm or less.
【請求項3】 前記電界緩和層は、その厚さ方向の断面
がテーパ形状であることを特徴とする請求項1又は2記
載の積層型固体撮像装置。
3. The stacked solid-state imaging device according to claim 1, wherein the electric field relaxation layer has a tapered cross section in the thickness direction.
【請求項4】 前記光導電膜に、膜内でアバランシェ増
倍が生じ得る高い電圧を印加できるように構成されてい
ることを特徴とする請求項1〜3のいずれか1項に記載
の積層型固体撮像装置。
4. The laminate according to claim 1, wherein the photoconductive film is configured so that a high voltage that can cause avalanche multiplication in the film can be applied. Type solid-state imaging device.
JP3352868A 1991-12-17 1991-12-17 Lamination-type solid-state image sensing device Withdrawn JPH05167056A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3352868A JPH05167056A (en) 1991-12-17 1991-12-17 Lamination-type solid-state image sensing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3352868A JPH05167056A (en) 1991-12-17 1991-12-17 Lamination-type solid-state image sensing device

Publications (1)

Publication Number Publication Date
JPH05167056A true JPH05167056A (en) 1993-07-02

Family

ID=18426998

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3352868A Withdrawn JPH05167056A (en) 1991-12-17 1991-12-17 Lamination-type solid-state image sensing device

Country Status (1)

Country Link
JP (1) JPH05167056A (en)

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