JPS582024A - Lead-out method for selective plated electrode - Google Patents
Lead-out method for selective plated electrodeInfo
- Publication number
- JPS582024A JPS582024A JP9837481A JP9837481A JPS582024A JP S582024 A JPS582024 A JP S582024A JP 9837481 A JP9837481 A JP 9837481A JP 9837481 A JP9837481 A JP 9837481A JP S582024 A JPS582024 A JP S582024A
- Authority
- JP
- Japan
- Prior art keywords
- contact hole
- layer
- electrode contact
- electrode
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims description 11
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 238000007747 plating Methods 0.000 claims abstract description 15
- 229910052751 metal Inorganic materials 0.000 claims abstract description 13
- 239000002184 metal Substances 0.000 claims abstract description 13
- 239000004065 semiconductor Substances 0.000 claims abstract description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 24
- 235000012239 silicon dioxide Nutrition 0.000 claims description 12
- 239000000377 silicon dioxide Substances 0.000 claims description 12
- 239000008151 electrolyte solution Substances 0.000 claims description 3
- 230000001678 irradiating effect Effects 0.000 claims description 2
- 239000003792 electrolyte Substances 0.000 abstract description 6
- 230000008020 evaporation Effects 0.000 abstract 1
- 238000001704 evaporation Methods 0.000 abstract 1
- 238000000059 patterning Methods 0.000 abstract 1
- 229910052782 aluminium Inorganic materials 0.000 description 18
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 18
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 239000011521 glass Substances 0.000 description 4
- 238000005530 etching Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 239000002689 soil Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】 本発明は選択メッキ電極引き出し方法に関する。[Detailed description of the invention] The present invention relates to a selective plating electrode extraction method.
半導体装置を製造する際、単結晶基板上に金属配線層を
形成するため該基板上の絶縁層をエツチングすることに
より電極コンタクトホールを形成する工程がある。通常
該電極コンタクトホールを形成した後、電極配線層はア
ルミニウムを蒸着することによって形成されている。そ
の要部について説明すると第１図は従来の１実施例を示
す概略断面図であり、単結晶シリコン基板ｌ上に二酸化
シリコン膜２を約１０００Ｘの厚さに形成し、更に該二
酸化シリコン膜２上に９んがラス（ＰＳＧ ）層３を約
１μｍの厚さに形成し、該りんｆラス層３と二酸化シリ
コン膜２とをエツチングし電極コンタクトホール５を形
成し、更にアルミニウム４が配線層として形成されてい
る。第１図において該りんガラス３のエツジ部３′とア
ルミニウム４が近接する点Ａ′で従来アルミニウムに段
差が生じエレクトロマイグレーシ璽／に対する耐性が不
足するとか更には断線を起す等牛導体デ・−イスの信頼
性を損ねる問題があった。第２図は前述の問題点を解決
した選択メッキ法による１実施例であり電極部の基板は
ｐ層層になっておシ、そしてシんガラス３上にレノスタ
６が載置されているのが第１図と異なっている構造であ
ってこの構造が電解液Ｂ中に浸漬せしめられており、ア
ルミニウム電ｆｉｌ（＋）７から出たイオンが電極コン
タクトホール５内の基板ｐ土層上に選択的にアルミニウ
ムメッキ層４Ｉが形成されている。この選択メッキ法は
第２図に示されたように電極部の基板がｐ層層になって
お）電極部以外の基板がｎ層になっているのでメッキの
際に順方向バイアスとなりアルミニウムメッキ層４′が
形成される。しかしながら逆に第２図に示した電極部の
基板かｎ層であシ基板がｐ層となった場合はｎ層とｐ層
の間にダイオード特性及作用し、メッキの際逆方向バイ
アスとなってメッキに不具合を起こす。When manufacturing a semiconductor device, in order to form a metal wiring layer on a single crystal substrate, there is a step of etching an insulating layer on the substrate to form electrode contact holes. Usually, after forming the electrode contact hole, the electrode wiring layer is formed by vapor depositing aluminum. To explain the main parts, FIG. 1 is a schematic cross-sectional view showing one conventional embodiment, in which a silicon dioxide film 2 is formed to a thickness of about 1000× on a single crystal silicon substrate l, and the silicon dioxide film 2 A phosphor lath layer 3 (PSG) layer 3 with a thickness of about 1 μm is formed on top, the phosphor lath layer 3 and the silicon dioxide film 2 are etched to form an electrode contact hole 5, and an aluminum layer 4 is formed as a wiring layer. It is formed as. In Fig. 1, at a point A' where the edge portion 3' of the phosphor glass 3 and the aluminum 4 are close to each other, a step is formed in the aluminum, resulting in a lack of resistance to electromigration or even breakage of the conductor. There was a problem that damaged the reliability of the chair. FIG. 2 shows an example of a selective plating method that solves the above-mentioned problems. The substrate of the electrode part is a p-layer layer, and the renostar 6 is placed on the thin glass 3. is a structure different from that in FIG. 1, and this structure is immersed in electrolyte B, and ions emitted from the aluminum electrolyte fil(+) 7 are deposited on the substrate p soil layer in the electrode contact hole 5. An aluminum plating layer 4I is selectively formed. In this selective plating method, as shown in Figure 2, the substrate of the electrode part is a p-layer layer, and the substrate other than the electrode part is an n-layer, so there is a forward bias during plating, and the aluminum plating is applied. Layer 4' is formed. However, if the substrate of the electrode section shown in Figure 2 is an N layer and the substrate is a P layer, a diode characteristic will occur between the N layer and the P layer, resulting in a reverse bias during plating. This will cause problems with the plating.
本発明の葉キカ泪的はｐ形半導体基板の一層の電極コン
タクトホール部内に金属層を形成することによる新しい
改良された電極引き出し方法を提供することである。The purpose of the present invention is to provide a new and improved method for drawing out an electrode by forming a metal layer within the electrode contact hole in one layer of a p-type semiconductor substrate.
本発明の目的はｐ形半導体基板上に二酸化シリコン膜を
形成し、次にレジストを塗布して・々ターニングし、該
レノストをマスクとして該二酸化シリコン膜をエツチン
グし電極コンタクトホールを形成し、次に該電極コンタ
クトホールに電極引き出しを形成する方法において、前
記電極コンタクトホールを形成した後、前記レジストを
除去し、該電極コンタクトホールが形成された半導体基
板を金属電解液中に浸漬して、少なくともｎ層とｐ層と
の間に光を照射することによって前記電極コンタクトホ
ール内の基板上に金属を選択メッキせしめて金属層を形
成することを特徴とする選択メッキ電極引き出し方法に
よって達成される。The purpose of the present invention is to form a silicon dioxide film on a p-type semiconductor substrate, then apply a resist, turn the silicon dioxide film, and then use the resist as a mask to etch the silicon dioxide film to form an electrode contact hole. In the method of forming an electrode extension in the electrode contact hole, after forming the electrode contact hole, the resist is removed, and the semiconductor substrate on which the electrode contact hole is formed is immersed in a metal electrolyte solution, and at least This is achieved by a selective plating electrode drawing method characterized in that a metal layer is formed by selectively plating metal on the substrate in the electrode contact hole by irradiating light between the n layer and the p layer.
本発明は従来、基板上の電極コンタクトホールのエツジ
部に段差が生じていたが、該電極コンタクトホール内に
選択メッキにより金属を埋めるととＫよりこの段差を解
消するものである。まだ該基板の電極形成部一層と、基
地のｐ層との境界に二酸化シリコン膜上方から可視光又
は紫外光を照射することによって、電子と正孔（電子・
正孔対）を基板内に発生せしめこの電子正孔対にキャリ
ヤーの働きさせて通常ｐ層上のｎ層という構成では不可
能であうた電解メッキを可能にすることが特徴と力って
いる。In the present invention, although a step has conventionally occurred at the edge of an electrode contact hole on a substrate, this step can be eliminated by filling the electrode contact hole with metal by selective plating. Electrons and holes (electrons and
The main feature of this method is that it generates electron-hole pairs in the substrate and causes these electron-hole pairs to act as carriers, thereby enabling electrolytic plating, which is normally impossible with a structure of an n-layer on a p-layer.
以下本発明の一実施例を第３図に基づいて説明する。An embodiment of the present invention will be described below with reference to FIG.
第３図は電解液中で本発明に係る選択メッキを実施して
いる概略断面図である。FIG. 3 is a schematic cross-sectional view showing selective plating according to the present invention carried out in an electrolytic solution.
ｐ形シリコン基板１を乾燥酸素中で約１０００℃程度の
高温で約５００Ｘの厚さに熱酸化し、レゾストを塗り、
電極部を開孔する。この開孔部の酸化膜を通し、Ａｌを
５０ ｋＶで１０ ｃｍｇ 程度イオン注入し、レ
ノストを除去した後、０２中で１０５０℃に約４０分間
保ち、アニールし、Ａｓを活性化させる。このとき酸化
膜厚は約１×１０３ｘにまで増大する。その上にりんガ
ラス（Ｐ２Ｏ）層３をＣＶＯ法により約８Ｘ１０３Ｘの
厚みに形成する。A p-type silicon substrate 1 is thermally oxidized in dry oxygen at a high temperature of about 1000° C. to a thickness of about 500×, and then coated with a resist.
Open the electrode part. Approximately 10 cmg of Al is ion-implanted at 50 kV through the oxide film in the opening to remove the renost, and then kept at 1050° C. for about 40 minutes in O2 to anneal and activate As. At this time, the oxide film thickness increases to approximately 1×10 3×. A phosphor glass (P2O) layer 3 is formed thereon to a thickness of approximately 8.times.10.sup.3 by the CVO method.
次に該ＰＥＧ層３上にレジスト（図示せず）を塗布して
電極部形成のためにノリーニングする０次に露出したＰ
２Ｏ層をスノ母ツタエツチングし、更に二酸化シリコン
膜をＱ伊、ｆスのグッズマでエツチングすることによっ
て除去し電極コンタクトホールを形成する。次にＰＥＧ
ｆｇ ３に残されたレノスト（図示せず）を０２ｆラ
ズマ中で燃焼させて除去しアルミニウム電解液８に浸漬
する。この場合ｐ形シリコン基板１を陰極にアルミニウ
ム電極７を陽極とする。基板のｎ土層と電解液との間に
電流を流すためにｎ層層とｐ形シリコン基板の境界を含
めた領域に可視又社紫外光を照射する。この照射が行な
われている間アルミニウム４／のメッキがなされる。こ
の場合電圧と光の強度の制御を行なうことによシミ極引
出しのためのメ、ツキ速度が制御せしめられる。ＰＳＧ
層３の上端とメッキされたアルミニウム４′の上端との
差が±１０００Ｘが好ましい。Next, a resist (not shown) is applied on the PEG layer 3, and the exposed P of the 0th order is subjected to nolining to form an electrode part.
The 2O layer is removed by etching the silicon dioxide layer, and the silicon dioxide film is further etched with a QI, FS material to form an electrode contact hole. Next, PEG
The renost (not shown) left in fg 3 is removed by burning in an 02f plasma and immersed in aluminum electrolyte 8. In this case, the p-type silicon substrate 1 is used as a cathode and the aluminum electrode 7 is used as an anode. In order to flow a current between the n-layer of the substrate and the electrolyte, a region including the boundary between the n-layer and the p-type silicon substrate is irradiated with visible or ultraviolet light. While this irradiation is being carried out, aluminum 4/ is plated. In this case, by controlling the voltage and the intensity of the light, the speed of removal of the stain electrode can be controlled. P.S.G.
Preferably, the difference between the top of layer 3 and the top of plated aluminum 4' is ±1000X.
それ以上であると従来と同様にアルミニウム配線層が絶
縁層のエツジ近接部で段差又は断線等の不具合を生せし
める可能性がある。If it is more than that, there is a possibility that the aluminum wiring layer will cause problems such as steps or disconnections in the vicinity of the edge of the insulating layer, as in the conventional case.
第４図は電気回路を含めた本発明の方法を示す一実施例
である。第４図において１１は甘こう電極、１２は電橋
であり、電位の正しい伝達をするものである。また第４
図ではｐ形シリコン基板１上に二酸化シリコン膜２のみ
を形成したコンタクトホールにアルミニウム４′がメッ
キされている。FIG. 4 is an embodiment of the method of the present invention including an electrical circuit. In FIG. 4, reference numeral 11 is an agaric electrode, and 12 is an electric bridge, which ensures correct transmission of electric potential. Also the fourth
In the figure, a contact hole in which only a silicon dioxide film 2 is formed on a p-type silicon substrate 1 is plated with aluminum 4'.
１０は電解槽、１３はバイアスである。10 is an electrolytic cell, and 13 is a bias.
本発明によって形成された選択メッキ電極は第５図に示
されたように蒸着アルミニウム層４′をほぼ平坦に形成
せしめることが出来る。従って信頼性のある半導体装置
を製造しうるものである。The selective plating electrode formed according to the present invention can form a substantially flat evaporated aluminum layer 4' as shown in FIG. Therefore, a reliable semiconductor device can be manufactured.
第１図は従来の１実施例を示す概略断面図であシ、第２
図は従来の他の実施例を示す概略断面図であり、第３図
、第４図は本発明に係る実施例を示したものであり、第
５図は本発明の利点を示す説明図である。
１．９形シリコン基板、２・・・二酸化シリコン膜、３
・・・りんがラス（ＰＳＧ ）、４’、 ４’・・・メ
ッキされたアルミニウム、４・・・蒸着されたアルミニ
ウム、５・・・電極゛コンタクトホール、６・・・レジ
スト、７・・・アルミニウム電極、８・・・アルミニウ
ム電解液、９・・・光、ｌＯ・・・電解槽、ｌｌ・・・
甘こう電極、１２・・・電橋、１３・・・ノ櫂イアス。
特許出願人
富士通株式会社
特許出願代理人
弁理士 青 木 朗
弁理士 西舘和之
弁理士 内田幸男
弁理士 山 口 昭 之
第２図 −−−
− ５ 図
１′FIG. 1 is a schematic sectional view showing one conventional embodiment.
The figure is a schematic sectional view showing another conventional embodiment, FIGS. 3 and 4 show an embodiment according to the present invention, and FIG. 5 is an explanatory diagram showing the advantages of the present invention. be. 1.9-type silicon substrate, 2... silicon dioxide film, 3
...Phosphor glass (PSG), 4', 4'...Plated aluminum, 4...Vapour-deposited aluminum, 5...Electrode (contact hole), 6...Resist, 7...・Aluminum electrode, 8... Aluminum electrolyte, 9... Light, lO... Electrolytic tank, ll...
Amako Electrode, 12...Denbashi, 13...No Kai Iasu. Patent applicant Fujitsu Limited Patent agent Akira Aoki Patent attorney Kazuyuki Nishidate Patent attorney Yukio Uchida Akira Yamaguchi Figure 2 ---- - 5 Figure 1'
Claims (1)
、次にレジストを塗布して・ダター二／グし、該レジス
トをマスクとして咳二酸化シリコン膜をエツチングし電
極コンタクトホールを形成し、次に該電極コンタクトホ
ールに金属を充填させ電極引き出しを形成する方法にお
いて、前記電極コンタクトホールを形成した彼、前記レ
ジストを除去し、該電極コンタクトホールが形成された
半導体基板を金属電解液中に浸漬して、少な゛くとも一
層とｐ層との間に光を照射することＫよって前記電極コ
ンタクトホール内の基板上に金属を選択メッキせしめて
金属層を形成することを特徴とする選択メッキ電極引き
出し方法。1. Form a silicon dioxide film on a p-type semiconductor substrate, then apply a resist and etch the silicon dioxide film using the resist as a mask to form an electrode contact hole. In the method of filling the electrode contact hole with metal and forming an electrode lead-out, the electrode contact hole is formed, the resist is removed, and the semiconductor substrate on which the electrode contact hole is formed is immersed in a metal electrolytic solution. A selective plating electrode drawer characterized in that a metal is selectively plated on the substrate in the electrode contact hole by irradiating light between at least one layer and the p layer to form a metal layer. Method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9837481A JPS582024A (en) | 1981-06-26 | 1981-06-26 | Lead-out method for selective plated electrode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9837481A JPS582024A (en) | 1981-06-26 | 1981-06-26 | Lead-out method for selective plated electrode |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS582024A true JPS582024A (en) | 1983-01-07 |
Family
ID=14218099
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9837481A Pending JPS582024A (en) | 1981-06-26 | 1981-06-26 | Lead-out method for selective plated electrode |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS582024A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60232843A (en) * | 1984-04-27 | 1985-11-19 | ザ・ワーナー・アンド・スウエーシイ・カンパニイ | Machine tool |
| JP2007297714A (en) * | 2006-05-04 | 2007-11-15 | Internatl Business Mach Corp <Ibm> | Apparatus and method for electrochemical processing of thin film on resistive semiconductor wafer |
-
1981
- 1981-06-26 JP JP9837481A patent/JPS582024A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60232843A (en) * | 1984-04-27 | 1985-11-19 | ザ・ワーナー・アンド・スウエーシイ・カンパニイ | Machine tool |
| JPH0543449B2 (en) * | 1984-04-27 | 1993-07-01 | Warner Swasey Co | |
| JP2007297714A (en) * | 2006-05-04 | 2007-11-15 | Internatl Business Mach Corp <Ibm> | Apparatus and method for electrochemical processing of thin film on resistive semiconductor wafer |
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