JPS58200572A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To contrive to improve the gate withstand voltage by a method wherein, utilizing the difference of etching speeds by impurities, a semiconductor region wherein an impurity is not introduced is let to remain in the form of islands with smooth side surfaces, and then a gate insulation film is adhered to the thickness of approx. uniformity. CONSTITUTION:A single crystal Si layer 6 and an Si oxide film 7 are deposited on a sapphire substrate 5, and boron is ion-implanted by patterning, resulting in the formation of boron layers 9 of high density. When isotropic etching is performed by chemical dry etching, the single crystal Si layer 6 has a high etching speed on the upper side and low etching speed on the lower side wherein the boron layer 9 are formed, and accordingly the side surfaces of the single crystal Si layer 6 remaining in the form of islands becomes smooth slopes of 15-30l. The Si dioxide film 7 is removed and thermally oxidized into the gate insulation film 3. Thereafter, an SOS/MOS transistor is manufactured in accordance with the normal processes.

Description

[Detailed Description of the Invention] [Technology of the Invention Minute Hand] What is the present invention? pJh, relates to a method of manufacturing an MOa type semiconductor device in which a semiconductor region is formed on edge sand.
゛[Technology of the Invention B-j Background and Axis Points] In general, as a semiconductor device in which a semiconductor region is provided on an insulating substrate, 1, for example, S
A typical example is a transistor (O8/MO8). This SO8
/MO8) Device isolation methods for semiconductor films provided on the edge board during the manufacture of transistors include a conventional process in which the semiconductor film between the elements is removed by etching, and a coplanar process in which a thick insulating film is embedded in a time-consuming process.・Process (H Kei Electronics, 1979.7, 23%)'
122”).

Compared to the coplanar process, this method of separation using conventional floss can reduce the difference in size, leading to higher density.

Figure 81 shows the structure of a (7) MOS transistor formed by a conventional process. On an insulating base 1, an element region 2 separated into trapezoidal islands is provided, and on top of this is provided an element region 2 separated into trapezoidal islands. A gate electrode 4 is formed with a gate insulating film 3 interposed therebetween.

The sides of the trapezoidal device region 2 formed by the conventional conventional process have a steep slope. When element quality M is performed by directional etching, the single crystal silicon-A plane becomes (1,0,0
> song, one peak of the element region 2 becomes a <1, 1, 1> song, and the angle formed between this @l and the lobe edge base 81!1 is 54
．． 7 becomes a fake. When gate loquat $S is deposited on top of this, since the sides of the main area 2 are steep, the gate insulating film 3 becomes;! A
Figure 1 (as shown in Bl surrounded by kW, i of element region 2
It becomes koji in the vicinity of the height 1 between ll+m and the insulating substrate 1. If the VCC gate membrane 3 becomes locally thin, it will cause a decrease in gate earth resistance (Nikkei Electronics, 1999).
79.7.23% PI 22 reference fF@).

For this reason, the relationship between the side angle of the element region 2 and the gate breakdown voltage in the conventional process has been studied. LiteratureTEEgTransactions on
Electron Devices (Vol.
ED-28No, 3 Murch 1981, P242
), it has been reported that by setting the l1ID angle on the opposite side to 35 or more F, it is possible to significantly increase the gate withstand voltage even in conventional fluorocesses.

Based on this knowledge, the present invention has developed a method for forming an element region in a single ridge, one square shape, and a conventional process for element isolation. In addition to increasing the pressure r, high-density glare Jt71
I] Provides a method for manufacturing a semiconductor device that enables the above-mentioned functions.

[Summary of the invention]

In the present invention, impurities are selectively increased in the vicinity of the interface with the insulating substrate of a semiconductor film deposited on an insulating substrate, and then the semiconductor I! 1It-isotropic etching technique is used to etch the insulating substrate until it comes out, and by taking advantage of the difference in etching speed due to the wood purity, the semiconductor region into which impurities have not been introduced is left in the shape of an island with gentle sides. This method is characterized in that the gate voltage is improved by dipping the gate insulator and depositing a gate insulator thereon with a substantially uniform thickness.

Examples of insulating substrates used in the present invention include 1, for example, sapphire substrates, glass substrates, spinel (^l: IO, +
M)O)substrate etc.

Examples of the semiconductor film used in the present invention include single crystal silicon, polycrystalline silicon, and amorphous silicon.

In the present invention, the impurity introduced into the semiconductor film is preferably 1, for example, holon, and by increasing the acceleration voltage during boron ion implantation, boron can be selectively introduced into the vicinity of the interface between the semiconductor film and the insulating substrate.

In the present invention, a region of a semiconductor film heavily contaminated with impurities is etched by isotropic etching, such as chemical dry etching (ODE).
) By using i, the etching rate on the substrate interface side into which impurities have been introduced is increased, and the island-like semiconductor region can be made to have a gentle slope. This one
i11th] and the insulating substrate is 15 to 30!
It is preferable to have an axial rotation of f, and if it is less than 152, the (l
J! The slope becomes too flat and the width of the sides becomes large.
This is because the element gap widens, and if it exceeds 30 degrees,
This is because the gate insulating layer deposited on the semiconductor region becomes wider in the vicinity of the substrate interface, lowering the gate breakdown voltage.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention applied to a transistor (1i80s/MO8) will be described in detail with reference to figures twJ2.

First, as shown in Figure 2, 5 is placed on the sapphire substrate 5.
After a single crystal silicon layer 6 with a thickness of 000 Ie is grown by epitaxial technology, a silicon dioxide film 7t is further deposited thereon by OVD technology. Next, after applying resist to the entire surface, take a photo &! A resist pattern g is formed in a portion that will become an element formation region by marking.

Next, using the resist pattern 8 as an etching-resistant mask, the silicon dioxide 11 film 1 is selectively etched away, and the single crystal silicon layer 6 is exposed as shown in the figure (B1).

After that, as shown in the same figure (C), using the patterned divalent silicon film 7 as a mask, boron is accelerated at an electric ratio of 20.
0 Key, 5X10 ~IX10 /Ujb
Then, ions ε are emitted to form a high #1 boron layer 9 near the interface between the single crystal 71137 layer 6 and the fire substrate 5.

Next, resist pattern 8. , and isotropically etched by chemical dry etching using the patterned silicon dioxide film 7 as a mask. -Sculptor's body. Etsu F7
G speed□8. o, the same figure (as shown in Dl, the slope of the single crystal silicon layer C remaining in the form of islands can be made into a gentle slope of 15 to 30 degrees!

Thereafter, after the silicon dioxide film 1 is removed, the silicon dioxide film 1 is aged, and as shown in FIG. At this time, single crystal silicon in contact with sapphire radix 5 + 9'e 6 1llttn
It is also possible to form three gate insulating films with sufficient number of gates.

Next, a polycrystalline silicon film containing phosphorus is applied over the entire surface as shown at tFl in the figure to form a gate [value 4].

P#I Loquat 10 is deposited according to the L direction of Tsugu, and the source 11 and drain 12 are formed by introducing impurity sound into the island-shaped monocrystalline silicon J-6 that will be the top of the element. After completing 7, external 'v! 5 shown in the same figure (Gl).
t) Manufacturing an S/MO8 transistor.

〔Effect of the invention〕

As explained earlier, according to the method for manufacturing a semiconductor device according to the present invention, elements can be separated in almost the same steps as conventional conventional processes, and high-density integration can be achieved. The method of the present invention can improve the pressure by about 1.5 times compared to the conventional conventional process, and when the electric field is increased to 5. .5~
It is possible to obtain a semiconductor device with excellent pressure resistance of 6.5 MV/+31.

[Brief explanation of drawings]

! l! The lid is a perspective view of a 5081 MO8 transistor fabricated using the conventional conventional process. It is a 1ITIlkI diagram sequentially showing the steps of manufacturing an example 808/MO8) transistor. 1... Insulating substrate, 2... Element region, 3... Gate-insulating film, 4... Kate electrode. 5...Sapphire base number, 6...Single crystal silicon j-17...Silicon dioxide film, 8...Resist pattern, 9...Poron layer, 10...Layered loquat edge film, IJ... sauce, 12...
・Drain, 13... Gaijakudenkyou.

Claims (2)

[Claims] (1) A step of depositing a semiconductor film on an insulating substrate, a step of selectively adding an impurity near the interface between the semiconductor film and the insulating substrate, and isotropic etching of the region where the impurity is introduced. Technique: A step in which the insulating substrate is etched until it bulges out, leaving areas with no impurities in an island shape with a trapezoidal cross section, and the semiconductor that reverberates in this island shape.
1. A method for wiring a semiconductor device, comprising the steps of forming a gate and an insulating film on the surface of the semiconductor region, and forming an element on the front half-layer region. (2) The semiconductor device according to claim 1, characterized in that boron is used as an impurity and boron t-(on-implanted) is selectively introduced into the vicinity of the interface of the insulating substrate of the semiconductor device. (Claim 1) A flexible semiconductor device in which aEFt is defined as forming an angle between the @ plane of the semi-integrated region remaining in the form of an island and the insulating substrate to be 15 to 30 degrees. manufacturing method.