JPS58200499A - Error detecting system in control storage section - Google Patents

Abstract

PURPOSE:To detect error in a control storage section quickly and accurately with less amount of processing, by using an error detecting and correcting function for the confirmation of justice of data and using a redundancy bit for a failure of address systems. CONSTITUTION:The control storage section 1 is accessed with an address advanced sequentially from the initial value via an address register 21 and a microinstruction word is stored in a microinstruction register 3. A check bit of the microinstruction is inputted to an error detecting and correcting circuit 5, where the detection of presence of an error in an instruction work data and the correction of 1-bit error and the like are done. On the other hand, a redundancy bit of the instruction word stored in the register 3 is impressed to an operating circuit 4 to which a direct data 0 and the like from a register 6 is applied at the initial state to detect the presence of a failure of address system by means of an exclusive OR processing. Thus, the data and data error are detected accurately and quickly with less amount of processing without full-bit processing.

Description

[Detailed Description of the Invention] Technical Field of the Invention] The present invention is an error detection method in the control storage section. Micro 7'o because it makes it easier to design the hardware and keep you waiting for the 7billiai meeting.
The wholesale control method described below is often used. The micronogram specifies all the hardware operations for each cycle of the machine, and one software program θl is executed by combining several microprograms. The microprograms are stored in a memory dedicated to retrieval, usually called a control unit, and are sequentially reloaded and executed one after another in accordance with a counter called a microprogram/strategy counter.

However, when writing a microprogram into the ECC machine's removable control storage that holds the microprogram, it is necessary to confirm whether or not it has been correctly written after the writing is completed. Conventional confirmation methods include sequentially reading out the written contents from the control storage unit and comparing them with the correct values, or reading out the contents stored in the control storage unit and detecting errors using a hardware ECC function. There are nine ways.

However, while the former confirmation method allows comprehensive confirmation including address system failures, the confirmation time becomes longer as the number of bits compared with all data bits increases. Confirmation of address system failures is insufficient. That is, written r
- There was a drawback that it could not be confirmed whether the data was written to the correct address.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned drawbacks, and performs a comprehensive check including address system failures, and confirms rotor locking performance by using the ECC function of the hardware and address system failures. The purpose is to provide an error detection method t-a in the control storage unit that reduces the amount of data processing required for confirmation and shortens the confirmation time by using redundant pits (check pits). shall be.

[wt, cost of invention]

The present invention is an error detection means for a control storage unit having redundant pits (checks and pits) for error checking, and is capable of collating and confirming data in all pits by using a hardware ECC function. Furthermore, by using redundant pits to deal with errors in the address direction, the amount of data processing needed to confirm the contents written in the control storage section is reduced.

This saves approximately one hour and provides an efficient error detection means.

[Embodiments of the invention]

The present invention will be explained below using Figure rki.

FIG. 1 shows, in a block diagram, an example of the configuration of a microglodallum control MI device realized by the present invention. In the figure, reference numeral 1 denotes a control storage section in which microprograms are stored, and in addition to each microprogram 1t8ti stored in the control memory tK section and the data section, an error checker,
It has redundant bits for reuse. 2 is an addressing circuit for the control storage section 1, and normally +X* new circuit 22
The address of the control storage unit 1 is updated sequentially through ``'', but the address is unconditionally jumped to ``Om'' while waiting for error processing. Therefore, the address register 21 is supplied with the direct data "0" and the +1 update times %22 output, respectively. J is a microinstruction register. 15 from ii control storage unit 1 to microinstruction register 3! The issued microinstruction candy is held, and the output of this microinstruction register 3 is supplied to the ECC function circuit 5, and some pits are also supplied to the arithmetic circuit 4.

FCC Error ChIcKing & Corr
It is an abbreviation of @ct1@n, which detects and corrects consecutive r-tabi, g-), and only detects errors of 2 pins or more. It is the law. In recent years, LSIs that realize this function have appeared (
7, and the functional circuit section 5 is constituted by this LSI. The error (I) positive output by this ECC function circuit section 5 is supplied to the microinstruction register J via the (G) 77.

There is data that is given to the staff register 6 via the other large sword of the E distribution calculation circuit 4. Although the data generally stored in this register 6 differs depending on the fc detection method, according to the embodiment of the present invention, direct data 1o" supplied from the outside is supplied. In other examples, the arithmetic circuit 4 is It is also possible to use the calculation output r - 7 via the calculation (ro) path 4 as the calculation output r - 7 (AND, EOR, A
DD, SUM -) f is a well-known logic.

FIG. 2 is a flowchart illustrating an example of an error detection method according to the present invention.

The operation of the microprogram control device shown in FIG. 1 will be explained below with reference to the flowchart shown in FIG. m2. Step 201 indicates an initial reset routine, which clears the contents of the register 6 and f address register 21. In step 203, the address of the control storage unit 1 addressed by the address register 21 and the The micro-instruction l-, that is, the data, check, and cupid are output and loaded into the micro-instruction register 3.The successively outputted data is sent to the ECC@function circuit 5, and the data is sent to the ECC @ function circuit 5. ) II Detection is performed. At step 204, the presence or absence of ECCCC nira-0 is checked. If there is an error, the process goes to error processing routine 110; if there is no error, the process goes to step 204.

At step 205, an exclusive OR is performed on some fields of the microinstruction register 3, such as check, cupit, and 'W' (which is "O" when the θ address is successively issued), and the result is ``w'' again.

That is, if there is no error, some pits set in microinstruction register 3 and data "0" set in register 6
'' is compared in the arithmetic circuit 4 -gtL, 6.
;,.

Next, in step 206, it is checked whether Stella f203, 204, and 205 have been actually applied to all addresses of the control storage unit 1, and if not, the address f: Pengji+-1 update circuit 2
Counter by 2! (Step, ypxor) L, Step, f208.204° Repeat the processing of 205. Step, f203, 104.205 (D is executed for all addresses, and if the next step is step 208, step 2o5 is executed.
The calculation result obtained in is compared with the correct value known in advance, and if there is a match, the control storage unit 111C is determined that the content is correct, so the process proceeds to Stella 1209 and ends. . Further, if it is determined that there is a mismatch, it is known that the contents stored in the control storage section 1 are incorrect, and the process proceeds to the error processing routine of step 210.

In the embodiment of the present invention, the exclusive OR is performed between the check pits in the tjmJ circuit 4, but it is also possible to perform an operation based on an arithmetic formula, such as a CRC check or an evening method, instead of the exclusive sum. is a sight.

[, Young fruit of Mima]

If the present invention is implemented as described above, E
By using the CC function, it is possible to check the validity of the r-data without checking the entire pit width, and redundant bits can also be used to check errors in the address direction. This makes it possible to detect errors by providing efficient error detection means.

[Brief explanation of drawings]

Figure 881 shows a microgram system in which the present invention is practiced.
FIG. 2 is a flowchart showing the operation of the present invention. DESCRIPTION OF SYMBOLS 1... Control storage unit, 2... Addresser circuit, 3...
...Microinstruction register, 4...Arithmetic circuit, 5...
・ECC function circuit・

Claims (1)

[Scope of Claims] (1) In a data processing device having a control memory section having nine redundant pits, the contents of all addresses in the control memory section are sequentially read to determine whether or not there are errors caused by the redundant pits. means for detecting, means for sequentially performing nine predetermined operations on specific part of pit positions regarding the data of all addresses stored in the control storage unit, and the results of the operations are added in advance. An error detection method in the control storage section whose main feature is to have means for detecting whether or not the value matches the value. A system for detecting errors in a control storage unit according to claim 1.