JPS58200170A - Current consumption measuring circuit - Google Patents

Current consumption measuring circuit

Info

Publication number
JPS58200170A
JPS58200170A JP57081606A JP8160682A JPS58200170A JP S58200170 A JPS58200170 A JP S58200170A JP 57081606 A JP57081606 A JP 57081606A JP 8160682 A JP8160682 A JP 8160682A JP S58200170 A JPS58200170 A JP S58200170A
Authority
JP
Japan
Prior art keywords
current
circuit
load
output
load current
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57081606A
Other languages
Japanese (ja)
Other versions
JPH0366622B2 (en
Inventor
Iwao Uchiyama
内山 巖
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP57081606A priority Critical patent/JPS58200170A/en
Publication of JPS58200170A publication Critical patent/JPS58200170A/en
Publication of JPH0366622B2 publication Critical patent/JPH0366622B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R21/00Arrangements for measuring electric power or power factor

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Testing Electric Properties And Detecting Electric Faults (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

PURPOSE:To eliminate complicated calculation for correction while improving the measuring accuracy and the frequency response by automatically performing a calculation for correction of a load current of an object to be measured by a circuit function. CONSTITUTION:An internal logic operation is performed for an object 5 to be measured based on binary-coded logic signals from a signal source 1 and the results are outputted. The output is applied to a detection circuit 2 and compared with the expected value thereof. Here, as the output of the object 5 goes to 'H', currents IR1-IRN flow through a load resistance 3. Output voltage V0 of a load current detection circuit 6 and a reference voltage for the object 5 are supplied to the input of a load current correction circuit 7 and the output thereof provides a voltage VS higher by a voltage generated of the circuit 6 than the reference voltage. As a result, the load currents IR1-IRN are cancelled out with current from the circuit 7 keeping the load current from flowing through a current consumption measuring circuit 4 and instead, only the current consumed in the object 5 being measured is supplied thereby assuring a highly accurate measurement.

Description

【発明の詳細な説明】 (技術分野) 本発明は簡単な回路構成で、電気回路の機能試験時の被
測定物内部で消費する電源電流の測定をする回路に関す
るものである。
DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a circuit with a simple circuit configuration that measures power supply current consumed inside a device under test during a functional test of an electric circuit.

′ (背景技術) 従来の機能試験時の消費電流の測定回路図を第1図に示
す。第1図において、1は機能試験用入力信号源、2は
コンパレータ回路による機能横用回路、3は機能試験時
の負荷抵抗R1〜RN、4は演算増幅器による消費電流
測定回路、5は被測定物の如く構成されており、電気回
路特にICなどの被測定物5は機能試験用入力信号源l
より出力される’11”又はL 11レベルの論理信号
入力に対して、内部論理動作を行ない、その結果を出力
端子0UT−1〜0UT−Nに出力する。そしてこれら
出力端子には、各々R1〜RNの負荷抵抗3および検出
回路2が接続され、出力レベルが’ H”の時はR,〜
RNを通して、IRI〜IRN、なる負荷電流が(jN
Dへ流れる。出力レベルがIt L Itの時には、各
々IRIL −IRNLの出力01i’ Fリーフ電流
のみで−ぼ零となる。又この時検出回路2は、各出力端
子の出力レベルが期待値と一致するか否かを常時看視し
ている。
(Background Art) Figure 1 shows a conventional circuit diagram for measuring current consumption during a functional test. In Fig. 1, 1 is an input signal source for functional testing, 2 is a functional horizontal circuit using a comparator circuit, 3 is a load resistance R1 to RN during a functional test, 4 is a current consumption measurement circuit using an operational amplifier, and 5 is a device to be measured. The device under test 5, such as an electric circuit, especially an IC, is an input signal source for functional testing.
An internal logic operation is performed on the logic signal input of '11' or L11 level output from When the load resistor 3 and detection circuit 2 of ~RN are connected and the output level is 'H', R, ~
Through RN, the load current from IRI to IRN is (jN
Flows to D. When the output level is It L It, only the output 01i'F leaf current of IRIL -IRNL becomes -0. Also, at this time, the detection circuit 2 constantly monitors whether the output level of each output terminal matches the expected value.

消費電流測定回路4は、被測定物5のVDD端子に接続
され被測定物内部で消費される電流IDDおよび出力電
流として外部負荷へ流出するIR1〜IRNの総合計が
loとして計測される。
The current consumption measuring circuit 4 measures the total sum of the current IDD connected to the VDD terminal of the device under test 5 and consumed inside the device under test and IR1 to IRN flowing out to an external load as an output current as lo.

1、 = DUT (被測定物)の消費電流+負荷電流
−= IDD +IRI−N = IDD −) IB
この総合電流の中の負荷電流IRO値は、外部負荷抵抗
の大きさおよび”)I”出力端子の数等の変化により、
その都度弯動する。従って、従来の消費電流測定方法で
は常時外部負荷回路への電流分を含んだ形での測定しか
できないことになる。従って、精度良く測定を行なうた
めには負荷抵抗の値および”H”出力端子の数等の計算
を常時性ない、補正作業を要するといった欠点があった
1, = current consumption of DUT (device under test) + load current - = IDD + IRI-N = IDD -) IB
The load current IRO value in this total current varies depending on the size of the external load resistance and the number of ")I" output terminals, etc.
It shifts each time. Therefore, the conventional current consumption measuring method can only measure the current that always includes the current flowing to the external load circuit. Therefore, in order to carry out accurate measurements, there are disadvantages in that the value of the load resistance, the number of "H" output terminals, etc. must be constantly calculated and correction work is required.

(発明の課題) 本発明は、従来の消費電流測定の欠点である外部負荷に
よる影響を複雑な計算による補正作業を要スるといった
欠点を除去するため、自動補正同機は、電源供給端子(
VDD)より電流の供給をうけ、人力信号に従って行っ
た処理の結果を負荷に出力する被測定回路(5)の、電
源供給端子よりの流入電流と負荷への流出電流(IR)
の挙である消費電流を測定する回路において、負荷電流
(IR)と所定の値(RL)との積に対応する電圧(V
o )を発生する負荷電流検出回路(6)と、該電圧(
Vo)と供給電源電圧(VDD)との和又は差に対応す
る電圧を抵抗(Rt、)を介して前記電源供給端子に提
供することにより供給電流から負荷電流(IR)を補償
する負荷電流補償回路と、供給電源から電源供給端子に
供給する電流のうち前記負荷電流補償回路により補償さ
れた値を差し引いた電流を計測する消費電流測定回路と
を有jるごとき消費電流測定回路にある。
(Problems to be solved by the invention) In order to eliminate the drawback of conventional current consumption measurement, which requires correction work using complicated calculations to compensate for the influence of external loads, the automatic correction device has a power supply terminal (
The inflow current from the power supply terminal and the outflow current (IR) to the load of the circuit under test (5) which receives current from the power supply terminal (VDD) and outputs the result of processing performed according to the human input signal to the load.
In a circuit that measures the current consumption, which is the following, the voltage (V
o)) and a load current detection circuit (6) that generates the voltage (
load current compensation for compensating the load current (IR) from the supply current by providing a voltage corresponding to the sum or difference between the power supply voltage (VDD) and the supply voltage (VDD) to the power supply terminal via a resistor (Rt); The current consumption measuring circuit includes a current consumption measuring circuit that measures a current obtained by subtracting a value compensated by the load current compensation circuit from among the current supplied from the power source to the power supply terminal.

(発明の構成および作用) 第2図は本発明の一実施例であって、1は機能へ 試験用入力信号源、2はコ/パレータ回路による機能試
験検出回路、3は機能試験時の負荷抵抗It、〜RN、
4は演算増幅器による消費電流測定回路、5は被611
1定物、6は演算増幅器による負荷電流検出回路、7は
演算増幅器による負荷電流補償回路である。
(Structure and operation of the invention) FIG. 2 shows an embodiment of the present invention, in which 1 is an input signal source for testing a function, 2 is a function test detection circuit using a co/parator circuit, and 3 is a load during a function test. Resistance It, ~RN,
4 is a current consumption measurement circuit using an operational amplifier, 5 is a 611 connected
1 is a constant, 6 is a load current detection circuit using an operational amplifier, and 7 is a load current compensation circuit using an operational amplifier.

次にこれら各回路の相互接続および動作について説明す
る。被測定物5の入力端子は機能試験入力信号源1に接
続され、出力端子は負荷抵抗3および検出回路2へ接続
される。VDD端子は消費電流測定回路4および負荷電
流補償回路7が接続される。負荷抵抗3の片1μmjは
全て短絡し、0■を基準レベルとする負荷電流検出回路
6の入力端子に接続される。負荷電流検出回路6の出力
端子は負荷電流補償回路7の入力に接続する。被測定物
5の出力は機能試験入力信号源lより出力される”H”
又はL”レベルの論理信号に基づき、内部論理動作を行
ないその結果を出力端子に11”又は”L I+ レベ
ルと、して出力される。検出回路2は、この出力の°’
H−”1・″を機能試験中は常時看視して、期待値と比
較し、判断処理を行なう。この時負荷抵抗3には、被測
定物5の出力がH”レベルになるとIR1=IRNの電
流が流れる。負荷電流検出回路6は、′串流−電圧変換
回路又はケルビンカ式による電流検出回路を使用するこ
とにより容易に実現できる。負荷電流補償回路7は、演
算増幅器を使用した反転増幅器および差動増幅器を組合
せた回路により実現できる。他は全て従来の測定回路で
第1図で説明したものと同じである。このIR1〜IR
Nの電流は0■を基準レベルとした負荷電流検出回路の
電流検出抵抗RLを通して流れるため検出抵抗の両端に ■oコニ−Ial+ IR2+・・・+IRN) X 
k[V)の電圧降下を生じる。負荷電流補償回路7の入
力には、負荷電流検出回路6の出力電圧■。と、被測定
物5のVDD端子に供給する電圧の基準電圧の2つが印
加され、この2つの電圧を加算あるいは減算させること
により、常にvDD供給電圧より負荷電流検出回路6で
発生する電圧分だけ高い電圧Vsが発生する。この′電
圧Vsを負荷電流検出回路6で使用する検出抵抗RLと
同じ値の抵抗7aを介して被測定物5のVDD端子に接
続することにより、被測定物5の出力端子より流出する
負荷電流(IR1〜IRN)は、負荷電流補償回路7よ
り全(同じ値の電流が供給され、見掛上キャンセルされ
ることになり、消費電流測定回路4には負荷電流は流れ
ないため、被測定物5の内部で消費する電流のみを供給
することになり、精度良(消費電流測定が行なえる。
Next, the interconnection and operation of each of these circuits will be explained. The input terminal of the device under test 5 is connected to the functional test input signal source 1, and the output terminal is connected to the load resistor 3 and the detection circuit 2. The consumption current measuring circuit 4 and the load current compensation circuit 7 are connected to the VDD terminal. The 1 μmj pieces of the load resistor 3 are all short-circuited and connected to the input terminal of a load current detection circuit 6 whose reference level is 0. The output terminal of the load current detection circuit 6 is connected to the input of the load current compensation circuit 7. The output of the DUT 5 is “H” output from the functional test input signal source 1.
Or, based on the L" level logic signal, internal logic operation is performed and the result is outputted to the output terminal as 11" or "L I+ level. The detection circuit 2 detects this output.
H-"1." is constantly monitored during the functional test, compared with the expected value, and judgment processing is performed. At this time, a current of IR1=IRN flows through the load resistor 3 when the output of the object to be measured 5 becomes H'' level. The load current compensation circuit 7 can be realized by a circuit that combines an inverting amplifier and a differential amplifier using an operational amplifier.All others are conventional measurement circuits as explained in FIG. This is the same as IR1~IR
Since the current of N flows through the current detection resistor RL of the load current detection circuit with 0 as the reference level, there is a current at both ends of the detection resistor.
A voltage drop of k[V] occurs. The input of the load current compensation circuit 7 is the output voltage ■ of the load current detection circuit 6. and the reference voltage of the voltage supplied to the VDD terminal of the device under test 5 are applied, and by adding or subtracting these two voltages, the voltage generated by the load current detection circuit 6 is always lower than the vDD supply voltage. A high voltage Vs is generated. By connecting this voltage Vs to the VDD terminal of the device under test 5 via a resistor 7a having the same value as the detection resistor RL used in the load current detection circuit 6, a load current flows out from the output terminal of the device under test 5. (IR1 to IRN) are supplied with all (the same value of current) from the load current compensation circuit 7 and are apparently canceled, and no load current flows through the current consumption measurement circuit 4, so the Since only the current consumed inside the device 5 is supplied, it is possible to measure the current consumption with good accuracy.

以上説明したように第1の実施例では、被測定物5の出
力端子より流出する負荷電流の補正計算が負荷電流検出
回路および補償回路の働きにより自動的に供給されるこ
とから、下記に示す様な利点がある。
As explained above, in the first embodiment, the correction calculation for the load current flowing out from the output terminal of the device under test 5 is automatically provided by the functions of the load current detection circuit and the compensation circuit. There are various advantages.

1 複雑な補正計算が不較。1. Complex correction calculations are incomparable.

2、 DUTの消費電流と負荷流出電流が無関係になる
ため精度良(測定ができる。
2. The current consumption of the DUT and the load outflow current are unrelated, allowing for accurate measurement.

3、外部負荷抵抗は被測定物の出力端子の駆動能力で制
限された値まで下げられるため、周波数応答性が良(な
る。
3. The external load resistance can be lowered to a value limited by the drive capability of the output terminal of the device under test, resulting in good frequency response.

4、被測定物の出力端子数は、測定の制限条件にならな
い。
4. The number of output terminals of the device under test is not a limiting condition for measurement.

第1の実施例では被測定物としてP−CH,FETによ
るオープンドレイン出力形式で説明しであるが、外部負
荷抵抗を通して、出力端子より流出電流か有る場合は負
荷電流検出および補償回路の働きにより電流補正効果が
生ずる。
In the first embodiment, the open-drain output format is explained using a P-CH and FET as the object to be measured, but if there is a current flowing out from the output terminal through an external load resistor, the function of the load current detection and compensation circuit will be used. A current correction effect occurs.

(11PNP)ランジスタのオーブンコレクタ出力の場
合を第3図に示す。
(11PNP) The case of the oven collector output of the transistor is shown in FIG.

(21N−Cl、FETによるソースホロウ出力の場合
を第4図に示す。
(Figure 4 shows the case of source hollow output using 21N-Cl and FET.

t:31  NPN)ランジスタによるエミッタホロウ
出力の場合を第5図に示す。
FIG. 5 shows the case of emitter hollow output using a transistor (t:31 NPN).

又前述の実施例では消費電流測定回路および負荷′電流
検出回路として、電流−電圧変換回路を使用しているが
、ケルビン方式による電流センス方式でも同様の効果が
生ずる。この例を第6図に示す。
Further, in the above embodiment, a current-to-voltage conversion circuit is used as the current consumption measuring circuit and the load current detection circuit, but the same effect can be obtained by using a Kelvin current sensing system. An example of this is shown in FIG.

第3図〜第6図の実施例は被測定物の出力形態の相違の
みで他は全て同じものである。
The embodiments shown in FIGS. 3 to 6 are the same except for the output form of the object to be measured.

(発明の効果) 本発明は負荷電流補償回路を有しているので、外部負荷
に流出する電流の補償が自動的に行なえる利点があり、
被測定物の出力端子の数および負荷抵抗の大小等の制限
が大幅に緩和するので機能試験時の消費電流測定に利用
することができる。
(Effects of the Invention) Since the present invention has a load current compensation circuit, it has the advantage that it can automatically compensate for the current flowing into the external load.
Since restrictions on the number of output terminals of the device under test and the size of load resistance are significantly relaxed, it can be used for measuring current consumption during functional tests.

【図面の簡単な説明】 第1図は従来の消費′電流測定方法による回路図、第2
図は本発明の測定方法による第1の実施例の回路図、第
3図、第4図、第5図および第6図は本発明による他の
実施例の回路図である。 1・・機能試験用入力信号源 2・・・コンパレータ回路による機能検出回路3・・・
機能試験時の負荷抵抗R1〜RN4・・・演算増幅器に
よる消費電流測定回路5・・・被測定物 6・・・演算増幅器による負荷電流検出回路7・・・演
算増幅器による負荷電流検出回路特  許  出  願
  人 沖電気工業株式会社 特許出願代理人 弁理士 山 本 恵 −
[Brief explanation of the drawings] Figure 1 is a circuit diagram based on the conventional consumption current measurement method;
The figure is a circuit diagram of a first embodiment according to the measuring method of the present invention, and FIGS. 3, 4, 5, and 6 are circuit diagrams of other embodiments according to the present invention. 1...Input signal source for functional test 2...Function detection circuit using a comparator circuit 3...
Load resistance R1 to RN4 during functional test... Current consumption measurement circuit using an operational amplifier 5... DUT 6... Load current detection circuit using an operational amplifier 7... Load current detection circuit using an operational amplifier Patent Application: Hitoki Electric Industry Co., Ltd. Patent application agent Megumi Yamamoto −

Claims (1)

【特許請求の範囲】[Claims] 電源供給端子(VDD )より電流の供給をうけ、入力
信号に従って行った処理の結果を負荷に出力する被測定
回路(5)の、電源供給端子よりの流入電流と負荷への
流出電流(IR)の差である消費電流を測定する回路に
おいて、負荷電流(IR)と所定の値(RL)との積に
対応する電圧(Vo )を発生する負荷電流検出回路(
6)と、該電圧(Vo)と供給電源電圧(VDD )と
の和又は差に対応する電圧を抵抗(Rt、)を介して前
記電源供給端子に提供することにより供給電流から負荷
電流(IR)を補償する負荷電流補償回路と、供給電源
から電源供給端子に供給する電流のうち前記負荷電流検
出回路により補償された値を差し引いた電流を計測する
消費電流測定回路とを有することを特徴とする消費電流
測定回路。
Inflow current from the power supply terminal and outflow current (IR) to the load of the circuit under test (5) which receives current from the power supply terminal (VDD) and outputs the result of processing performed according to the input signal to the load. In a circuit that measures current consumption, which is the difference between
6), and the load current (IR ); and a current consumption measuring circuit that measures the current supplied from the power supply to the power supply terminal minus the value compensated by the load current detection circuit. Current consumption measurement circuit.
JP57081606A 1982-05-17 1982-05-17 Current consumption measuring circuit Granted JPS58200170A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57081606A JPS58200170A (en) 1982-05-17 1982-05-17 Current consumption measuring circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57081606A JPS58200170A (en) 1982-05-17 1982-05-17 Current consumption measuring circuit

Publications (2)

Publication Number Publication Date
JPS58200170A true JPS58200170A (en) 1983-11-21
JPH0366622B2 JPH0366622B2 (en) 1991-10-18

Family

ID=13750971

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57081606A Granted JPS58200170A (en) 1982-05-17 1982-05-17 Current consumption measuring circuit

Country Status (1)

Country Link
JP (1) JPS58200170A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02143172A (en) * 1988-11-25 1990-06-01 Nec Corp Logic analyzer
EP1550878A1 (en) * 2003-12-31 2005-07-06 Teradyne, Inc. Parallel source/capture architecture for automatic test equipment

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02143172A (en) * 1988-11-25 1990-06-01 Nec Corp Logic analyzer
EP1550878A1 (en) * 2003-12-31 2005-07-06 Teradyne, Inc. Parallel source/capture architecture for automatic test equipment
US7230553B2 (en) 2003-12-31 2007-06-12 Teradyne, Inc. Parallel source/capture architecture

Also Published As

Publication number Publication date
JPH0366622B2 (en) 1991-10-18

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