JPS5819966A - Ｄｍａ転送方式 - Google Patents

Ｄｍａ転送方式

Info

Publication number
JPS5819966A
JPS5819966A JP56119916A JP11991681A JPS5819966A JP S5819966 A JPS5819966 A JP S5819966A JP 56119916 A JP56119916 A JP 56119916A JP 11991681 A JP11991681 A JP 11991681A JP S5819966 A JPS5819966 A JP S5819966A
Authority
JP
Japan
Prior art keywords
address
slave
signal
memory
main memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56119916A
Other languages
English (en)
Japanese (ja)
Other versions
JPH024024B2 (enrdf_load_stackoverflow
Inventor
Kenichi Onishi
謙一 大西
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Omron Corp
Original Assignee
Tateisi Electronics Co
Omron Tateisi Electronics Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tateisi Electronics Co, Omron Tateisi Electronics Co filed Critical Tateisi Electronics Co
Priority to JP56119916A priority Critical patent/JPS5819966A/ja
Publication of JPS5819966A publication Critical patent/JPS5819966A/ja
Publication of JPH024024B2 publication Critical patent/JPH024024B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)
JP56119916A 1981-07-30 1981-07-30 Ｄｍａ転送方式 Granted JPS5819966A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56119916A JPS5819966A (ja) 1981-07-30 1981-07-30 Ｄｍａ転送方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56119916A JPS5819966A (ja) 1981-07-30 1981-07-30 Ｄｍａ転送方式

Publications (2)

Publication Number Publication Date
JPS5819966A true JPS5819966A (ja) 1983-02-05
JPH024024B2 JPH024024B2 (enrdf_load_stackoverflow) 1990-01-25

Family

ID=14773357

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56119916A Granted JPS5819966A (ja) 1981-07-30 1981-07-30 Ｄｍａ転送方式

Country Status (1)

Country Link
JP (1) JPS5819966A (enrdf_load_stackoverflow)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1985005709A1 (en) * 1984-06-05 1985-12-19 Fanuc Ltd Method of sending and receiving data

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1985005709A1 (en) * 1984-06-05 1985-12-19 Fanuc Ltd Method of sending and receiving data

Also Published As

Publication number Publication date
JPH024024B2 (enrdf_load_stackoverflow) 1990-01-25

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