JPS58198908A - Semiconductor device equipped with protecting circuit - Google Patents

Semiconductor device equipped with protecting circuit

Info

Publication number
JPS58198908A
JPS58198908A JP57081437A JP8143782A JPS58198908A JP S58198908 A JPS58198908 A JP S58198908A JP 57081437 A JP57081437 A JP 57081437A JP 8143782 A JP8143782 A JP 8143782A JP S58198908 A JPS58198908 A JP S58198908A
Authority
JP
Japan
Prior art keywords
layer
emitter
base
semiconductor device
breakdown
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57081437A
Other languages
Japanese (ja)
Inventor
Toshiaki Matsubara
松原 俊明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP57081437A priority Critical patent/JPS58198908A/en
Publication of JPS58198908A publication Critical patent/JPS58198908A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F1/00Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/52Circuit arrangements for protecting such amplifiers

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Abstract

PURPOSE:To increase the degree of integration and to prevent a surface breakdown between the emitter and base of a bipolar TR by forming a Zener diode structure between the 1st conduction type emitter area and the 2nd conduction type base area of the TR. CONSTITUTION:An epitaxial growth layer 3 is formed on a semiconductor substrate 1 and an island 10 is formed of an insulating layer 4. An N<+> layer 8 as a collector C and a P layer 5 as a base B are formed in the island 10 and an N<+> layer 7 as an emitter E is formed in a base B by impurity diffusion. Further, a P<+> layer 6 is formed at part of the P layer 5 in contact with at least the bottom surface part of the N<+> layer 7. In this case, the diameter B of the P<+> layer is less than the diameter A of the N<+> layer. Therefore, an area with higher dielectric strength than an original TR is formed at the contacting part between the P<+> layer 6 and emitter layer 7, so a breakdown occurs to not the surface, but this contacting part.

Description

【発明の詳細な説明】 この発明は、バイポーラ型トランジスタを具備する半導
体装置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device including a bipolar transistor.

半導体基板、例えばシリコン基板に形成されたバイポー
ラトランジスタ(以下トランジスタと称す)のベースに
高電圧が印加されるとエミッターベース間にブレークダ
ウンが生じるが、プレークズ9ンは、シリコン基板表面
付近で起こることが多い。
When a high voltage is applied to the base of a bipolar transistor (hereinafter referred to as a transistor) formed on a semiconductor substrate, such as a silicon substrate, a breakdown occurs between the emitter and the base. Breakdown occurs near the surface of the silicon substrate. There are many.

シリコ746表面でブレークダウンが起こると。When breakdown occurs on the surface of Silico 746.

基板の主表面に形成されている杷−−1例えば5i(J
、機と7リコン基板との界面に、ホットキャリアか生じ
その結束としてトランジスタのIll、流層−卓h□が
低下してしまう。
For example, 5i (J
, hot carriers are generated at the interface between the device and the silicon substrate, and as a result of their binding, the transistor's Ill and current-layer characteristics are reduced.

本発明は上述した欠点を是正し、集積度が高く、且つト
ランジスタのエミッターベースM表1i逆方1畑ブレー
クダウンを防止[7得る保繰回路付きの半導体装置な提
供することにある。
SUMMARY OF THE INVENTION The present invention corrects the above-mentioned drawbacks, and provides a semiconductor device with a retention circuit that has a high degree of integration and prevents the emitter base M table 1 i reverse 1 field breakdown of a transistor.

以F、実施例を用い1本発明を説明する。Hereinafter, the present invention will be explained using Examples.

第1図及び第2図iよ、半導体装置の構造を示し。FIGS. 1 and 2 i show the structure of a semiconductor device.

第3図はシンボル化した回路図な示すものである。FIG. 3 shows a symbolic circuit diagram.

また第4図はIIIの応用例、第5図は第2の応用例な
示すものである。
Further, FIG. 4 shows an application example of III, and FIG. 5 shows a second application example.

先ず、本発明の構造について述べるとよシリコンで形成
された半導体J&板lには、エピタキシヤシ成長層3が
形成され、さらに絶縁−4によってアイランド(島)1
0が形成されている。
First, the structure of the present invention will be described. An epitaxial growth layer 3 is formed on a semiconductor J & plate 1 made of silicon, and an island 1 is formed by an insulator 4.
0 is formed.

このアイランド10内には、コレクタCとなるN”1i
18.ベースBとなるP層5%ペースB内にはエミッタ
EとなるN+層7が不純物拡散により形成されている。
In this island 10, there are N"1i which becomes the collector C.
18. In the P layer 5% space B, which becomes the base B, an N+ layer 7, which becomes the emitter E, is formed by impurity diffusion.

セして、注目すべきことは、工ミ1りEとなるN+層7
の底面部に少なくとも接するように、ペース8となるP
層の一部KP”1l16が形成されている。なS、上記
p+ l−の直径Bは、N+層の直径人に対しB<Aと
なるように形成されている。
The important thing to note is that the N+ layer 7 has an E of 1
P, which is pace 8, so that it is at least in contact with the bottom part of
A part of the layer KP''116 is formed.The diameter B of the above p+ l- is formed so that B<A with respect to the diameter of the N+ layer.

このような構成によれば、P”+、16とエミッター7
の接触部(第2図に太線で示す)K、本来のトランジス
タの耐圧より低い耐圧を有する部分が形成されたことK
なり、ブレークダウンは表面でおこらず、この接触部で
おこることKなるう上述の如く構成された半導体装置を
、電子回路に図示すると第3図に示す如きペース・エミ
ッタ間にツェナーダイオードZDが接続されることKな
る。このとき、ツェナーダイオードの耐圧v8は、トラ
ンジスタ本来の、工きツタ−ベース間ブレークダウン電
圧Bv[1OK比べ小さくなっている。第3図に示すト
ランジスタ回路において、ベースV−嵩電圧が供給され
た場合のような逆方向動作時にツェナーダイオードが働
く。このツェナーダイオードは堀め込み型となっている
ことによって、ペース表面の安定化が行なわれる。すな
わち。
According to such a configuration, P”+,16 and emitter 7
The contact portion (shown by the thick line in Figure 2) K, which has a lower breakdown voltage than the original transistor breakdown voltage, has been formed.
Therefore, breakdown does not occur at the surface, but at this contact point.If a semiconductor device configured as described above is illustrated in an electronic circuit, a Zener diode ZD is connected between the pace emitter and the emitter as shown in Figure 3. It will be done. At this time, the breakdown voltage v8 of the Zener diode is smaller than the transistor-to-base breakdown voltage Bv[1OK, which is the original voltage of the transistor. In the transistor circuit shown in FIG. 3, the Zener diode operates during reverse operation, such as when a base V-bulk voltage is supplied. This Zener diode is of a recessed type, thereby stabilizing the surface of the paste. Namely.

通常の場合はペースの表面でブレークダウンし。Normally it breaks down on the surface of the pace.

これに起因するSin、Ps界面へのキャリア打ち込み
等により表面不安定となり、ベース表面での再結合電流
が増大しh□劣化するが、本発明を用いることKよりブ
レークダウン領域なベース低面部とすることができ、ペ
ース表面における特性劣化を防止することができる。
This causes the surface to become unstable due to the injection of carriers into the Sin and Ps interfaces, increasing the recombination current at the base surface and causing H□ deterioration. This makes it possible to prevent property deterioration on the surface of the paste.

また、トランジスタのコレクタに1161Vc、、ベー
スにペース電流■bが供給され、順方向動作するときベ
ース1lCRIbもツェナーダイオードZDKtILれ
ようとするがB<Aなる関係からその電流量は少く特性
劣化する心配はない。
In addition, 1161Vc is supplied to the collector of the transistor, and a pace current b is supplied to the base, and when the transistor operates in the forward direction, the base 11CRIb also tries to pass through the Zener diode ZDKtIL, but since the relationship B<A, the amount of current is small and there is a concern that the characteristics will deteriorate. There isn't.

また半導体基板内にトランジスタとツェナーダイオード
とな一体に形成できるので、集M度が向上する。
Further, since the transistor and the Zener diode can be integrally formed within the semiconductor substrate, the degree of M concentration is improved.

なお1本構造の形成法としては、まずペースを形成し次
にエミッタ形成領域の1部に、B(はう素)などのアク
セプタ不純物をイオン打ち込4し、P+^−貧領域を形
成した後、エミッタ形成領域にアクセプタ不純物をデポ
ジットし、熱拡散(ドライブ−イン)してエミッター7
およびP+層6を同時に形成すればよい。なおP+層6
はベース層を貫通してNaI!エピタキシャル113に
至る構造となっていてもよい。
The method for forming a single structure was as follows: First, a paste was formed, and then an acceptor impurity such as B (boron) was ion-implanted into a part of the emitter formation region to form a P+^-poor region. After that, acceptor impurities are deposited in the emitter formation region and thermally diffused (drive-in) to form the emitter 7.
and P+ layer 6 may be formed at the same time. Note that P+ layer 6
penetrates the base layer and NaI! The structure may extend to the epitaxial layer 113.

第4図は1本発明の他の実施例を示すものであり、用い
られている符号は@2図と対応している。
FIG. 4 shows another embodiment of the present invention, and the symbols used correspond to those in FIG. 2.

ここではP+1m6のかわりに、エミッタ層7内KN+
+層11を形成し、ブレークダウン領域(図に太−で示
す)がエミツタ層底面部くくるようにしている。
Here, instead of P+1m6, KN+ in the emitter layer 7
A + layer 11 is formed so that the breakdown region (indicated by a thick - mark in the figure) wraps around the bottom surface of the emitter layer.

また、他の実施例としてエミツタ層(N”JI)゛の周
辺表面部のドナー濃度を抑え、N一層とし。
In another embodiment, the donor concentration at the peripheral surface of the emitter layer (N''JI) is suppressed to form a single N layer.

表面部におけるブレークダウンを防止する構造としても
よい。
A structure may be used to prevent breakdown in the surface portion.

上述の如き構造の半導体装着は第4図に示すような差動
増幅回路に好適である、すなわち、従来の差動増幅回路
においては、トランジスタQI。
The semiconductor mounting structure as described above is suitable for a differential amplifier circuit as shown in FIG. 4. That is, in the conventional differential amplifier circuit, the transistor QI.

Q、に高電圧レベルの差動人力が供給されると、エミッ
タ・ペース間でブレークダウンする。この結果、電流増
幅率h□が低下する。しかし、第3図に示す差動増幅回
路においては、ツェナーダイオードZL)、、ZD、の
動作により、上述の如き欠陥が発生しない。
When Q is supplied with a high voltage level differential power, it will break down between the emitter and pace. As a result, the current amplification factor h□ decreases. However, in the differential amplifier circuit shown in FIG. 3, the above-mentioned defects do not occur due to the operation of the Zener diodes ZL), , ZD.

また、本発明を第5図に示す如き自走マルチバイブレー
タに適用してよい。自走マルチバイブレータにおい【、
トランジスタQI −Q*のベースに高吐出が供給され
るので、従来構造のままではベース・エミッタ間でブレ
ークダウンが発生し易い。しかし、第5図に示す回路構
成では、ツェナーダイオードZD、、ZD、の動作によ
り、上述の如き欠陥が発生しない。そして、トランジス
タQ、、Q、、ツXす−fイオードZD、、zO,。
Further, the present invention may be applied to a self-propelled multivibrator as shown in FIG. Self-propelled multivibrator smell [,
Since a high discharge voltage is supplied to the base of the transistor QI-Q*, breakdown is likely to occur between the base and emitter if the conventional structure is used. However, in the circuit configuration shown in FIG. 5, the above-mentioned defects do not occur due to the operation of the Zener diodes ZD, , ZD. and transistors Q, , Q, and diodes ZD, , zO,.

更に負荷抵抗RL、、RL、等を同一半導体1体上に形
成できるので、半導体集積回路化する際に。
Furthermore, since the load resistors RL, RL, etc. can be formed on the same semiconductor, when fabricating a semiconductor integrated circuit.

集積層が向上する。The stacking layer is improved.

以上の如く、本発明の半導体装置は、高電圧レベルの入
力信号が供給される電子回路に適用した際、半導体装着
の劣化、すなわち電流増幅率h□の低下等が発生せず、
安定した回路動作を行うことができる。また、集積度が
向上するので、半導体集積回路化に好適である。
As described above, when the semiconductor device of the present invention is applied to an electronic circuit to which a high voltage level input signal is supplied, there is no deterioration of the semiconductor mounting, that is, a decrease in the current amplification factor h□, etc.
Stable circuit operation can be performed. Furthermore, since the degree of integration is improved, it is suitable for semiconductor integrated circuits.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例である半導体装置の構造を示
す要部の平面図。 第2図は第1図の置一層線に沿う断面図。 第3図は半導体装置をシンボル化した回路図。 第4図は本発明の他の実施例を説明するための要部の断
面図、 第5図は第1の応用例を示す回路図、 #I6図は第2の応用例を示す回路図である。 l・・半導体基板、2・・・堀め込み層、3・・・Nl
lエピタキシャル層、6・・・P+層、9・・・絶縁膜
、11・・・N++層、Q、、Q、・・・トランジスタ
、ZD、。 ZD、、、、ツェナーダイオード、Rb1.Rb3.R
e1゜Rel・・抵抗。 馨にン 第  1  図 第  2  図 第  3  図       第  5  同第  4
  図 z
FIG. 1 is a plan view of essential parts showing the structure of a semiconductor device that is an embodiment of the present invention. FIG. 2 is a sectional view taken along the first layer line in FIG. 1. Figure 3 is a circuit diagram symbolizing a semiconductor device. Fig. 4 is a sectional view of the main part for explaining another embodiment of the present invention, Fig. 5 is a circuit diagram showing the first application example, and Fig. #I6 is a circuit diagram showing the second application example. be. l...Semiconductor substrate, 2...Drilling layer, 3...Nl
l epitaxial layer, 6...P+ layer, 9...insulating film, 11...N++ layer, Q,,Q,...transistor, ZD,. ZD, , Zener diode, Rb1. Rb3. R
e1゜Rel...Resistance. Figure 1 Figure 2 Figure 3 Figure 5 Figure 4
Figure z

Claims (1)

【特許請求の範囲】[Claims] 半導体基板にバイポーラトランジスタが形成されている
半導体装t11において、前記バイポーラトランジスタ
の第−導電型工きツタ領域と112導電型ペース餉緘の
間にツェナーダイオード構造を形成したことを特徴とす
る保腫回路を具備した半導体装置。
A semiconductor device t11 in which a bipolar transistor is formed on a semiconductor substrate, characterized in that a Zener diode structure is formed between the -th conductivity type Ivy region of the bipolar transistor and the 112 conductivity type paste layer. A semiconductor device equipped with a circuit.
JP57081437A 1982-05-17 1982-05-17 Semiconductor device equipped with protecting circuit Pending JPS58198908A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57081437A JPS58198908A (en) 1982-05-17 1982-05-17 Semiconductor device equipped with protecting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57081437A JPS58198908A (en) 1982-05-17 1982-05-17 Semiconductor device equipped with protecting circuit

Publications (1)

Publication Number Publication Date
JPS58198908A true JPS58198908A (en) 1983-11-19

Family

ID=13746367

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57081437A Pending JPS58198908A (en) 1982-05-17 1982-05-17 Semiconductor device equipped with protecting circuit

Country Status (1)

Country Link
JP (1) JPS58198908A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62263721A (en) * 1986-05-09 1987-11-16 Mitsubishi Electric Corp D-a converter

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62263721A (en) * 1986-05-09 1987-11-16 Mitsubishi Electric Corp D-a converter

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